An input buffer, an analog-to-digital converter

Abstract

The present application relates to an input buffer and an analog-to-digital converter, and more specifically to the technical field of input buffers. In the first bias protection circuit of the input buffer, the first target voltage terminal is connected to the first voltage terminal in sequence through a third resistor and a twenty-fifth switch tube; the enable terminal in the first bias protection circuit is connected to the control terminal of the twenty-fourth switch tube through a first NOT gate; the control terminal of the twenty-fourth switch tube is connected to the control terminal of the twenty-third switch tube through a second NOT gate; the first target voltage terminal is also connected to the second voltage terminal in sequence through a fourth resistor and a twenty-eighth switch tube; the enable terminal is also connected to the control terminal of the twenty-seventh switch tube through a first NOT gate; and the second bandgap reference current source is connected to the second voltage terminal through the twenty-sixth switch tube. Based on the above circuit, the switch tubes in the circuit will not be damaged when the bandgap reference has not yet been established.

Description

Technical Field

[0001] The present application relates to the technical field of input buffers, and in particular to an input buffer and an analog-to-digital converter. Background Art

[0002] Pipelined ADC plays a role in wireless communications, high-speed data acquisition systems and other fields due to its high speed and high precision.

[0003] The input of a pipelined analog-to-digital converter typically uses a large sampling capacitor to sample the signal source. If the signal source has large voltage fluctuations, the pipeline ADC needs to draw a large current from the signal source. Typically, the signal source cannot provide such a large current, so the signal obtained by the sampling capacitor will be severely distorted. The input buffer has a high input impedance and a large output current, which can solve the problem of insufficient signal source drive capability.

[0004] However, due to the requirements on linearity and speed of the input buffer, the supply voltage of the input buffer will be correspondingly higher, which may cause the terminal voltage of the transistor in the input buffer to exceed the withstand voltage value and be damaged. Summary of the Invention

[0005] The present application provides an input buffer and an analog-to-digital converter, and the technical solution is as follows.

[0006] An input buffer is provided, comprising an input buffer circuit, a bias circuit, and a first bias protection circuit;

[0007] In the input buffer circuit, the first target voltage terminal is connected to the voltage output terminal through the third switch tube M3; the voltage output terminal is connected to the common ground terminal through the second switch tube M2 and the first switch tube M1 in sequence;

[0008] The control terminal of the third switch tube M3 is connected to the input voltage terminal; the input voltage terminal is also connected to the common ground terminal through the third capacitor C3 and the first switch tube M1 in sequence;

[0009] In the bias circuit, the first voltage terminal is connected to the common ground terminal through the tenth switch tube M10 and the ninth switch tube M9 in sequence; the second voltage terminal is connected to the common ground terminal through the eighth switch tube M8 and the seventh switch tube M7 in sequence;

[0010] In the first bias protection circuit, the first target voltage terminal is connected to the first voltage terminal via the third resistor R3 and the twenty-fifth switch M25 in sequence; the first target voltage terminal is also grounded via the twenty-fourth switch M24; an enable terminal in the first bias protection circuit is connected to the control terminal of the twenty-fourth switch M24 via a first NOT gate I1; the control terminal of the twenty-fourth switch M24 is connected to the control terminal of the twenty-third switch M23 via a second NOT gate I2; and in the first bias protection circuit, a first bandgap reference current source is connected to the first voltage terminal via the twenty-third switch M23.

[0011] The first target voltage terminal is further connected to the second voltage terminal via the fourth resistor R4 and the twenty-eighth switch tube M28 in sequence; the first target voltage terminal is further grounded via the twenty-seventh switch tube M27; the enable terminal is further connected to the control terminal of the twenty-seventh switch tube M27 via the first NOT gate I1; in the first bias protection circuit, the second bandgap reference current source is connected to the second voltage terminal via the twenty-sixth switch tube M26.

[0012] In a possible implementation, the control end of the twenty-seventh switch tube M27 is connected to the control end of the twenty-sixth switch tube M26 via the third NOT gate I3 and the fourth NOT gate I4 in sequence.

[0013] In a possible implementation, in the bias circuit, the first voltage terminal is connected to the control terminal of the eighth switch tube M8, the control terminal of the ninth switch tube M9, and the control terminal of the tenth switch tube M10 respectively; the second voltage terminal is connected to the control terminal of the seventh switch tube M7.

[0014] In a possible implementation, the input buffer further includes a first linearity improvement circuit;

[0015] In the first linearity boosting circuit, the first constant voltage terminal is connected to the first node via the fourteenth switch tube M14; the first constant voltage terminal is also connected to the first node via the thirteenth switch tube M13; the second constant voltage terminal is connected to the second node via the twelfth switch tube M12; the second constant voltage terminal is connected to the second node via the eleventh switch tube M11; and the first node and the second node are connected via a first capacitor C1.

[0016] The first node is connected to the control terminal of the nineteenth switch tube M19 through the eighteenth switch tube M18; the first node is also connected to the control terminal of the nineteenth switch tube M19 through the seventeenth switch tube M17; the control terminal of the nineteenth switch tube M19 is connected to the input voltage terminal through the second capacitor C2;

[0017] The second node is connected to the input voltage terminal through the sixteenth switch tube M16; the second node is also connected to the input voltage terminal through the fifteenth switch tube M15;

[0018] The first target voltage terminal is connected to the output voltage terminal through the nineteenth switch tube M19 and the third switch tube M3 in sequence.

[0019] In a possible implementation, the fourteenth switch transistor M14, the eighteenth switch transistor M18, the twelfth switch transistor M12, and the sixteenth switch transistor M16 are NMOS transistors;

[0020] The thirteenth switch transistor M13, the seventeenth switch transistor M17, the eleventh switch transistor M11 and the fifteenth switch transistor M15 are PMOS transistors;

[0021] The control terminals of the twelfth switch tube M12, the fourteenth switch tube M14, the fifteenth switch tube M15 and the seventeenth switch tube M17 are connected to the first periodic signal;

[0022] The control terminals of the eleventh switch tube M11 , the thirteenth switch tube M13 , the sixteenth switch tube M16 and the eighteenth switch tube M18 are connected to the second period signal.

[0023] In a possible implementation, the input buffer further includes a second bias protection circuit;

[0024] In the second bias protection circuit, the first target voltage terminal is connected to the third node through the second resistor R2;

[0025] The third node is connected to the fourth node via the twenty-first switch tube M21; the fourth node is grounded via the first resistor R1; the control terminal of the twenty-first switch tube M21 is connected to the fourth node; the fourth node is also grounded via the twentieth switch tube M20; the control terminal of the twentieth switch tube M20 is connected to the enable terminal;

[0026] The first constant voltage terminal is connected to the control terminal of the nineteenth switch tube M19 through the twenty-second switch tube M22; the control terminal of the twenty-second switch tube M22 is connected to the third node.

[0027] In a possible implementation, the input buffer includes a digital control module;

[0028] In the digital control module, the digital enable terminal is connected to the control terminal of the twenty-ninth switch tube M29 through the fifth NOT gate I5;

[0029] The second target voltage terminal is connected to the fifth node through the thirty-first switch tube M31; the fifth node is grounded through the twenty-ninth switch tube M29; the second target voltage terminal is also connected to the enable terminal through the thirty-second switch tube M32; the enable terminal is grounded through the thirtieth switch tube M30;

[0030] The control terminal of the thirty-first switch tube M31 is connected to the enable terminal; the control terminal of the thirty-second switch tube M32 is connected to the fifth node; the control terminal of the thirtieth switch tube M30 is connected to the digital enable terminal;

[0031] The enable terminal is connected to the inverting enable terminal through a sixth NOT gate I6.

[0032] In a possible implementation, the digital control module further includes a seventh NOT gate, an eighth NOT gate, a first AND gate, a second AND gate, and a third AND gate;

[0033] The first digital code signal is connected to the first input terminal of the first AND gate through the seventh NOT gate; the second digital code signal is connected to the second input terminal of the first AND gate;

[0034] The third digital code signal is connected to the first input terminal of the second AND gate through the eighth NOT gate; the fourth digital code signal is connected to the second input terminal of the second AND gate;

[0035] The output end of the first AND gate is connected to the first input end of the third AND gate; the output end of the second AND gate is connected to the second input end of the third AND gate; and the output end of the third AND gate is connected to the digital enable end.

[0036] In a possible implementation, the input buffer further includes a second linearity improving circuit;

[0037] In the second linearity improvement circuit, the second target voltage terminal is connected to the seventh node through the sixth switch tube M6 and the fifth switch tube M5 in sequence;

[0038] The seventh node is connected to the common ground through the fourth switch tube M4; the seventh node is connected to the control end of the second switch tube M2; the control end of the fourth switch tube M4 is grounded through the first switch tube M1.

[0039] An analog-to-digital converter is provided, comprising the input buffer according to the present invention.

[0040] The technical solution provided by this application may have the following beneficial effects:

[0041] The input buffer shown in the present application includes an input buffer circuit, a bias circuit, and a first bias protection circuit; in the input buffer circuit, the first target voltage terminal is connected to the voltage output terminal through the third switch tube M3; the voltage output terminal is connected to the common ground terminal in sequence through the second switch tube M2 and the first switch tube M1; the control terminal of the third switch tube M3 is connected to the input voltage terminal; the input voltage terminal is also connected to the common ground terminal in sequence through the third capacitor C3 and the first switch tube M1; in the bias circuit, the first voltage terminal is connected to the common ground terminal in sequence through the tenth switch tube M10 and the ninth switch tube M9; the second voltage terminal is connected to the common ground terminal in sequence through the eighth switch tube M8 and the seventh switch tube M7; in the first bias protection circuit, the first target voltage terminal is connected to the first voltage terminal in sequence through the third resistor R3 and the twenty-fifth switch tube M25. The first target voltage terminal is also connected to the ground through the twenty-fourth switch M24; the enable terminal in the first bias protection circuit is connected to the control terminal of the twenty-fourth switch M24 through the first NOT gate I1; the control terminal of the twenty-fourth switch M24 is connected to the control terminal of the twenty-third switch M23 through the second NOT gate I2; in the first bias protection circuit, the first bandgap reference current source is connected to the first voltage terminal through the twenty-third switch M23; the first target voltage terminal is also connected to the second voltage terminal through the fourth resistor R4 and the twenty-eighth switch M28 in sequence; the first target voltage terminal is also connected to the ground through the twenty-seventh switch M27; the enable terminal is also connected to the control terminal of the twenty-seventh switch M27 through the first NOT gate I1; in the first bias protection circuit, the second bandgap reference current source is connected to the second voltage terminal through the twenty-sixth switch M26. When the bandgap reference has not yet been established, the bias protection circuit of the input buffer prevents the third switch M3 from being damaged due to excessive drain voltage of the third switch M3 caused by low current in the input buffer circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0043] Figure 1 The figure is a schematic structural diagram of an input buffer according to an exemplary embodiment.

[0044] Figure 2 A schematic structural diagram of an input buffer involved in an embodiment of the present application is shown.

[0045] Figure 3 A structural diagram of a second bias protection circuit involved in an embodiment of the present application is shown.

[0046] Figure 4 A structural diagram of a digital control module involved in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0047] The following will clearly and completely describe the technical solution of this application in conjunction with the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.

[0048] It should be understood that the "indication" mentioned in the embodiments of this application can be a direct indication, an indirect indication, or an indication of an association. For example, "A indicates B" can mean that A directly indicates B, for example, B can be obtained through A; it can also mean that A indirectly indicates B, for example, A indicates C, and B can be obtained through C; it can also mean that there is an association between A and B.

[0049] In the description of the embodiments of the present application, the term "corresponding" may indicate a direct or indirect correspondence between the two, or an association relationship between the two, or a relationship between indication and being indicated, configuration and being configured, etc.

[0050] Figure 1 FIG. 1 is a schematic diagram showing the structure of an input buffer according to an exemplary embodiment. Figure 1 As shown, the circuit includes an input buffer circuit, a bias circuit and a first bias protection circuit;

[0051] In the input buffer circuit, the first target voltage terminal is connected to the voltage output terminal through the third switch tube M3; the voltage output terminal is connected to the common ground terminal through the second switch tube M2 and the first switch tube M1 in turn;

[0052] The control terminal of the third switch tube M3 is connected to the input voltage terminal; the input voltage terminal is also connected to the common ground terminal through the third capacitor C3 and the first switch tube M1 in sequence;

[0053] In the bias circuit, the first voltage terminal is connected to the common ground terminal through the tenth switch tube M10 and the ninth switch tube M9 in sequence; the second voltage terminal is connected to the common ground terminal through the eighth switch tube M8 and the seventh switch tube M7 in sequence;

[0054] In the first bias protection circuit, the first target voltage terminal is connected to the first voltage terminal in sequence through the third resistor R3 and the twenty-fifth switch transistor M25; the first target voltage terminal is also grounded through the twenty-fourth switch transistor M24; the enable terminal in the first bias protection circuit is connected to the control terminal of the twenty-fourth switch transistor M24 through the first NOT gate I1; the control terminal of the twenty-fourth switch transistor M24 is connected to the control terminal of the twenty-third switch transistor M23 through the second NOT gate I2; in the first bias protection circuit, the first bandgap reference current source is connected to the first voltage terminal through the twenty-third switch transistor M23;

[0055] The first target voltage terminal is further connected to the second voltage terminal via the fourth resistor R4 and the twenty-eighth switch tube M28 in sequence; the first target voltage terminal is further grounded via the twenty-seventh switch tube M27; the enable terminal is further connected to the control terminal of the twenty-seventh switch tube M27 via the first NOT gate I1; in the first bias protection circuit, the second bandgap reference current source is connected to the second voltage terminal via the twenty-sixth switch tube M26.

[0056] In a possible implementation, in the bias circuit, the first voltage terminal is connected to the control terminal of the eighth switch tube M8, the control terminal of the ninth switch tube M9, and the control terminal of the tenth switch tube M10 respectively; the second voltage terminal is connected to the control terminal of the seventh switch tube M7.

[0057] To maintain high linearity even with large input swings, the input buffer circuit requires a relatively high 2.5V power supply voltage. Furthermore, the input buffer has extremely high speed requirements. Therefore, most of the switching transistors in the input buffer circuit use 0.9V series transistors, which have a lower withstand voltage but better high-frequency performance. This series of transistors has a withstand voltage of only 0.9V. Because the input buffer circuit's external DC power supply and LDO (low dropout regulator) require time to power up, the voltage at the terminals of some transistors may exceed their withstand voltage during the power supply ramp-up from 0V to 1.8V or 2.5V, potentially causing damage. Therefore, it is necessary to incorporate bias protection circuitry into the input buffer circuit.

[0058] Figure 1 The input buffer operation principle shown is as follows:

[0059] In the input buffer circuit, the third switch tube M3 forms a source follower, so that the output signal V OUT Follow the input signal V at the input voltage terminal INThe first switch M1 is a constant current source that can provide a constant current to the source follower (i.e., the third switch M3). The second switch M2 is a cascode structure that increases the equivalent resistance of the voltage output terminal, thereby stabilizing the tracking of the source follower (i.e., the third switch M3).

[0060] In the bias circuit, a two-stage bias circuit is used because the first switch M1 in the input buffer circuit requires a relatively low bias voltage. A single-stage bias circuit cannot directly output a low-voltage bias. The ninth and tenth switches M9 and M10 output a relatively high bias voltage to bias the second-stage bias circuit, while the eighth and seventh switches M8 and M7 output a relatively low bias voltage to bias the first switch M1 in the input buffer circuit.

[0061] In the first bias protection circuit, when power is first applied, the bias mode is switched to, and the level EN of the enable terminal is set to 1. Then, the twenty-third switch tube M23 and the twenty-fourth switch tube M24 are turned off, the twenty-sixth switch tube M26 and the twenty-seventh switch tube M27 are turned off, and the twenty-fifth switch tube M25 and the twenty-eighth switch tube M28 are turned on. The voltage at the first voltage terminal ID1 is the divided voltage of the third resistor R3, the twenty-fifth switch tube M25, and the ninth switch tube M9 and the tenth switch tube M10 in the bias circuit. The voltage at the second voltage terminal ID2 is the divided voltage of the fourth resistor R4, the twenty-eighth switch tube M28, and the seventh switch tube M7 and the eighth switch tube M8 in the bias circuit. Because the currents at the first voltage terminal ID1 and the second voltage terminal ID2 in the bias circuit are both derived from a bandgap reference, which takes time to establish, the bias for the first switch M1 in the input buffer circuit is temporarily provided by the voltage divider between the resistor and the transistor described above before the bandgap reference is established. This prevents the third switch M3 from being damaged by an excessive drain voltage due to low current in the input buffer circuit.

[0062] After the circuit stabilizes, it switches to normal mode and sets the enable terminal level EN to 0. Then, the twenty-third switch tube M23 and the twenty-fourth switch tube M24 are turned on, the twenty-sixth switch tube M26 and the twenty-seventh switch tube M27 are turned on, and the twenty-fifth switch tube M25 and the twenty-eighth switch tube M28 are turned off. The current of the first voltage terminal ID1 and the current of the second voltage terminal ID2 are provided by the current ID1_in of the first bandgap reference current source and the current ID2_in of the second bandgap reference current source from the bandgap reference, thereby providing a more accurate bias for the input buffer circuit.

[0063] It should be noted that the voltage VD25 of the first target voltage terminal is 2.5V, the voltage of the second target voltage terminal VD18 is 1.8V, and VSS is a common ground terminal.

[0064] In summary, the input buffer shown in the present application includes an input buffer circuit, a bias circuit, and a first bias protection circuit; in the input buffer circuit, the first target voltage terminal is connected to the voltage output terminal through the third switch tube M3; the voltage output terminal is connected to the common ground terminal in sequence through the second switch tube M2 and the first switch tube M1; the control terminal of the third switch tube M3 is connected to the input voltage terminal; the input voltage terminal is also connected to the common ground terminal in sequence through the third capacitor C3 and the first switch tube M1; in the bias circuit, the first voltage terminal is connected to the common ground terminal in sequence through the tenth switch tube M10 and the ninth switch tube M9; the second voltage terminal is connected to the common ground terminal in sequence through the eighth switch tube M8 and the seventh switch tube M7; in the first bias protection circuit, the first target voltage terminal is connected to the first target voltage terminal in sequence through the third resistor R3 and the twenty-fifth switch tube M25. The first bias protection circuit comprises a first voltage terminal; the first target voltage terminal is also connected to ground via the twenty-fourth switch M24; the enable terminal in the first bias protection circuit is connected to the control terminal of the twenty-fourth switch M24 via the first NOT gate I1; the control terminal of the twenty-fourth switch M24 is connected to the control terminal of the twenty-third switch M23 via the second NOT gate I2; in the first bias protection circuit, a first bandgap reference current source is connected to the first voltage terminal via the twenty-third switch M23; the first target voltage terminal is also connected to the second voltage terminal via the fourth resistor R4 and the twenty-eighth switch M28 in sequence; the first target voltage terminal is also connected to ground via the twenty-seventh switch M27; the enable terminal is also connected to the control terminal of the twenty-seventh switch M27 via the first NOT gate I1; in the first bias protection circuit, a second bandgap reference current source is connected to the second voltage terminal via the twenty-sixth switch M26. When the bandgap reference is not established, the bias protection circuit of the input buffer prevents the third switch M3 from being damaged due to excessive drain voltage of the third switch M3 caused by low current in the input buffer circuit.

[0065] Further, in Figure 1 Based on this, the input buffer can also be added as Figure 2 The first linearity improving circuit and the second linearity improving circuit shown in Figure 3 The second bias protection circuit shown and Figure 4 The digital control module shown. Figure 2 A schematic structural diagram of an input buffer involved in an embodiment of the present application is shown. Figure 3 A structural diagram of a second bias protection circuit involved in an embodiment of the present application is shown. Figure 4 A structural diagram of a digital control module involved in an embodiment of the present application is shown.

[0066] like Figure 2 As shown, in a possible implementation, the circuit further includes a first linearity improvement circuit;

[0067] In the first linearity boosting circuit, the first constant voltage terminal is connected to the first node via the fourteenth switch tube M14; the first constant voltage terminal is also connected to the first node via the thirteenth switch tube M13; the second constant voltage terminal is connected to the second node via the twelfth switch tube M12; the second constant voltage terminal is connected to the second node via the eleventh switch tube M11; the first node and the second node are connected via the first capacitor C1;

[0068] The first node is connected to the control end of the nineteenth switch tube M19 through the eighteenth switch tube M18; the first node is also connected to the control end of the nineteenth switch tube M19 through the seventeenth switch tube M17; the control end of the nineteenth switch tube M19 is connected to the input voltage end through the second capacitor C2;

[0069] The second node is connected to the input voltage terminal through the sixteenth switch tube M16; the second node is also connected to the input voltage terminal through the fifteenth switch tube M15;

[0070] The first target voltage terminal is connected to the output voltage terminal through the nineteenth switch tube M19 and the third switch tube M3 in sequence.

[0071] like Figure 2 As shown, in a possible implementation, the fourteenth switch transistor M14, the eighteenth switch transistor M18, the twelfth switch transistor M12, and the sixteenth switch transistor M16 are NMOS transistors;

[0072] The thirteenth switch transistor M13, the seventeenth switch transistor M17, the eleventh switch transistor M11 and the fifteenth switch transistor M15 are PMOS transistors;

[0073] The control terminals of the twelfth switch tube M12, the fourteenth switch tube M14, the fifteenth switch tube M15 and the seventeenth switch tube M17 are connected to the first cycle signal;

[0074] The control terminals of the eleventh switch tube M11 , the thirteenth switch tube M13 , the sixteenth switch tube M16 , and the eighteenth switch tube M18 are connected to the second cycle signal.

[0075] like Figure 2 As shown, in a possible implementation, the circuit further includes a second linearity improving circuit;

[0076] In the second linearity improvement circuit, the second target voltage terminal is connected to the seventh node through the sixth switch tube M6 and the fifth switch tube M5 in sequence;

[0077] The seventh node is connected to the common ground through the fourth switch tube M4 ; the seventh node is connected to the control end of the second switch tube M2 ; the control end of the fourth switch tube M4 is grounded through the first switch tube M1 .

[0078] like Figure 2 As shown, in a possible implementation, the control end of the twenty-seventh switch tube M27 is connected to the control end of the twenty-sixth switch tube M26 through the third NOT gate I3 and the fourth NOT gate I4 in sequence.

[0079] like Figure 3 As shown, in a possible implementation, the circuit further includes a second bias protection circuit;

[0080] In the second bias protection circuit, the first target voltage terminal is connected to the third node via the second resistor R2;

[0081] The third node is connected to the fourth node via the twenty-first switch tube M21; the fourth node is grounded via the first resistor R1; the control terminal of the twenty-first switch tube M21 is connected to the fourth node; the fourth node is also grounded via the twentieth switch tube M20; the control terminal of the twentieth switch tube M20 is connected to the enable terminal;

[0082] The first constant voltage terminal is connected to the control terminal of the nineteenth switch tube M19 through the twenty-second switch tube M22 ; the control terminal of the twenty-second switch tube M22 is connected to the third node.

[0083] like Figure 4 As shown, in a possible implementation, the circuit includes a digital control module;

[0084] In the digital control module, the digital enable terminal is connected to the control terminal of the twenty-ninth switch tube M29 through the fifth NOT gate I5;

[0085] The second target voltage terminal is connected to the fifth node through the thirty-first switch tube M31; the fifth node is grounded through the twenty-ninth switch tube M29; the second target voltage terminal is also connected to the enable terminal through the thirty-second switch tube M32; the enable terminal is grounded through the thirtieth switch tube M30;

[0086] The control terminal of the thirty-first switch tube M31 is connected to the enable terminal; the control terminal of the thirty-second switch tube M32 is connected to the fifth node; the control terminal of the thirtieth switch tube M30 is connected to the digital enable terminal;

[0087] The enable terminal is connected to the inverting enable terminal through a sixth NOT gate I6.

[0088] like Figure 4 As shown, in a possible implementation, the digital control module further includes a seventh NOT gate, an eighth NOT gate, a first AND gate, a second AND gate, and a third AND gate;

[0089] The first digital code signal is connected to the first input terminal of the first AND gate through the seventh NOT gate; the second digital code signal is connected to the second input terminal of the first AND gate;

[0090] The third digital code signal is connected to the first input terminal of the second AND gate through the eighth NOT gate; the fourth digital code signal is connected to the second input terminal of the second AND gate;

[0091] The output terminal of the first AND gate is connected to the first input terminal of the third AND gate; the output terminal of the second AND gate is connected to the second input terminal of the third AND gate; and the output terminal of the third AND gate is connected to the digital enable terminal.

[0092] Figure 2 The input buffer operation principle shown is as follows:

[0093] In the second linearity improvement circuit, the fourth switch tube M4, the fifth switch tube M5, and the sixth switch tube M6 form a common-source amplifier. The fourth switch tube M4, the fifth switch tube M5, the sixth switch tube M6 and the second switch tube M2 form a negative feedback structure, so that the gate-source voltage of the second switch tube M2 is stable, thereby making the transconductance of the second switch tube M2 constant, that is, stabilizing the equivalent impedance of the voltage output end, and improving the linearity of the input buffer circuit.

[0094] In the first linearity boosting circuit, the eleventh and twelfth switching transistors M11 and M12, the thirteenth and fourteenth switching transistors M13 and M14, the fifteenth and sixteenth switching transistors M15 and M16, and the seventeenth and eighteenth switching transistors M17 and M18 respectively form four CMOS switches, which are controlled by the first and second periodic signals THS and CLKF, which are clock signals.

[0095] When the first periodic signal THS and the second periodic signal CLKF are in phase 1, the eleventh switching transistor M11, the twelfth switching transistor M12, the thirteenth switching transistor M13, and the fourteenth switching transistor M14 are turned on, and the voltage V1 at the first constant voltage terminal and the voltage V2 at the second constant voltage terminal charge the first capacitor C1. When the first periodic signal THS and the second periodic signal CLKF are in phase 2, the fifteenth switching transistor M15, the sixteenth switching transistor M16, the seventeenth switching transistor M17, and the eighteenth switching transistor M18 are turned on, and the first capacitor C1 charges the second capacitor C2, so that the voltage across the second capacitor C2 is equal to the difference between the voltage V1 at the first constant voltage terminal and the voltage V2 at the second constant voltage terminal, thereby providing a bias voltage to the nineteenth switching transistor M19.

[0096] When the first cycle signal THS and the second cycle signal CLKF are in phase 1, the fifteenth switch tube M15, the sixteenth switch tube M16, the seventeenth switch tube M17 and the eighteenth switch tube M18 are turned off. Due to the coupling effect of the second capacitor C2, the voltage at the control end of the nineteenth switch tube M19 follows the voltage V at the input voltage end. IN , and the nineteenth switch tube M19 is a source follower, so the drain voltage of the third switch tube M3 will also follow the voltage V IN This makes the gate-drain voltage of the third switch tube M3 relatively constant, further improving the linearity of the input buffer circuit.

[0097] Because the input buffer circuit has extremely high speed requirements, the first through sixth switches M1 through M6 all use 0.9V transistors with a withstand voltage of only 0.9V. Because the nineteenth switch M19 needs to maintain the linearity of the output buffer circuit and has a slightly lower speed requirement, a 1.2V transistor with a withstand voltage of 1.2V is selected. The bias for the control terminal of the nineteenth switch M19 is provided by the second capacitor C2. Before the first cycle signal THS and the second cycle signal CLKF are applied, the second capacitor C2 has not yet charged. Therefore, the voltage at the control terminal of the nineteenth switch M19 is very low, and the drain voltage of the nineteenth switch M19 is 2.5V. This means that the maximum gate-drain voltage of the nineteenth switch M19 can reach 2.5V, while the withstand voltage of the nineteenth switch M19 is only 1.2V, which will damage the nineteenth switch M19.

[0098] The currents required for the first and second voltage terminals ID1, ID2 in the bias circuit are both derived from a bandgap reference. However, establishing the bandgap reference takes time. As a result, the bias voltage of the first switch M1 is not established for a period of time after the entire circuit is powered on. Consequently, the current in the input buffer circuit is extremely low, which makes the source and drain voltages of the nineteenth switch M19 relatively close. The source voltage of the nineteenth switch M19 can reach over 2V, while the common-mode voltage at the voltage output terminal is approximately 0.9V. This means that the source-drain voltage of the third switch M3 will exceed 1.1V, despite the fact that the withstand voltage of the third switch M3 is only 0.9V.

[0099] Therefore, bias protection circuits need to be provided to protect the nineteenth switch tube M19 and the third switch tube M3 respectively.

[0100] In the second bias protection circuit, upon power-up, the circuit switches to bias mode, setting the enable terminal's level EN to 1. This turns on the 20th switch M20, thereby lowering the voltage at the control terminal and the drain voltage of the 21st switch M21. This turns on the 21st switch M21, which in turn lowers the voltage at the control terminal of the 22nd switch M22, turning it on. At this point, the voltage BP1 at the control terminal of the 19th switch M19 is provided by the voltage V1 at the first constant voltage terminal, thereby preventing the 19th switch M19 from breaking down due to the inability to charge the second capacitor C2 due to the lack of the first periodic signal THS and the second periodic signal CLKF.

[0101] After the circuit stabilizes, it switches to normal mode, i.e., the level EN of the enable terminal is set to 0. Then, the twentieth switch tube M20 is turned off. Since the resistance of the first resistor R1 is much greater than that of the second resistor R2, the voltage at the control terminal of the twenty-second switch tube M22 is relatively high. The twenty-second switch tube M22 is turned off, and the voltage at the control terminal of the nineteenth switch tube M19 is provided by the second capacitor C2.

[0102] The principle of the first bias protection circuit has been Figure 1 The above is described in the embodiments and will not be repeated here.

[0103] For a 1-bit digital control signal, the default state after chip power-up can be either 0 or 1. Using only a 1-bit control signal to switch the bias protection circuit between bias mode and normal mode can easily cause problems. Therefore, a 4-bit control code is used in the digital control module to control the switching between bias mode and normal mode. The bias mode is switched only when the digital code BIAS_EN = 4'b1010. The 29th through 32nd switches M29 through M32 form a positive feedback circuit that raises the high level of the enable signal SPI_EN (provided by the 0.9V voltage of the digital power supply VD9 at the fifth NOT gate I5) from 0.9V to 1.8V, thereby enabling the bias protection circuit.

[0104] In addition, when the 0.9V digital power supply VD9 is not powered on, the control terminal voltage of the 29th switch tube M29 and the 30th switch tube M30 is 0V, the 29th switch tube M29 and the 30th switch tube M30 are turned off, and the level EN of the enable terminal is 1. The bias circuit operates in the state where the first bias protection circuit and the second bias protection circuit are in the bias mode.

[0105] It should be noted that EN_N is the voltage of the inverting enable terminal.

[0106] Optionally, based on the input buffer shown in the embodiment of the present application, the input buffer can also be applied to an analog-to-digital converter.

[0107] In summary, the input buffer shown in the present application includes an input buffer circuit, a bias circuit, and a first bias protection circuit; in the input buffer circuit, the first target voltage terminal is connected to the voltage output terminal through the third switch tube M3; the voltage output terminal is connected to the common ground terminal in sequence through the second switch tube M2 and the first switch tube M1; the control terminal of the third switch tube M3 is connected to the input voltage terminal; the input voltage terminal is also connected to the common ground terminal in sequence through the third capacitor C3 and the first switch tube M1; in the bias circuit, the first voltage terminal is connected to the common ground terminal in sequence through the tenth switch tube M10 and the ninth switch tube M9; the second voltage terminal is connected to the common ground terminal in sequence through the eighth switch tube M8 and the seventh switch tube M7; in the first bias protection circuit, the first target voltage terminal is connected to the first target voltage terminal in sequence through the third resistor R3 and the twenty-fifth switch tube M25. The first bias protection circuit comprises a first voltage terminal; the first target voltage terminal is also connected to ground via the twenty-fourth switch M24; the enable terminal in the first bias protection circuit is connected to the control terminal of the twenty-fourth switch M24 via the first NOT gate I1; the control terminal of the twenty-fourth switch M24 is connected to the control terminal of the twenty-third switch M23 via the second NOT gate I2; in the first bias protection circuit, a first bandgap reference current source is connected to the first voltage terminal via the twenty-third switch M23; the first target voltage terminal is also connected to the second voltage terminal via the fourth resistor R4 and the twenty-eighth switch M28 in sequence; the first target voltage terminal is also connected to ground via the twenty-seventh switch M27; the enable terminal is also connected to the control terminal of the twenty-seventh switch M27 via the first NOT gate I1; in the first bias protection circuit, a second bandgap reference current source is connected to the second voltage terminal via the twenty-sixth switch M26. When the bandgap reference is not established, the bias protection circuit of the input buffer prevents the third switch M3 from being damaged due to excessive drain voltage of the third switch M3 caused by low current in the input buffer circuit.

[0108] Furthermore, input buffers require large swing and high linearity, which typically results in a higher supply voltage. However, switching transistors with better high-frequency performance have lower withstand voltages, necessitating a compromise between swing, linearity, and speed. By incorporating a bias protection circuit, this input buffer achieves both large swing and high linearity without sacrificing circuit speed.

[0109] Furthermore, the bias protection circuit of the input buffer has a simple structure and a small transistor size, which can control power consumption within a very small range.

[0110] Furthermore, the input buffer's bias protection circuit is in a default protection bias state before the digital control module is powered on, eliminating the need for additional control circuitry and making the circuit simpler and less prone to damage. Furthermore, the digital control module prevents errors in the bias protection circuit from switching between bias mode and normal mode, which could be caused by digital circuit bit errors.

[0111] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0112] It should be understood that the present application is not limited to the exact structures described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. An input buffer, characterized in that The circuit includes an input buffer circuit, a bias circuit and a first bias protection circuit; In the input buffer circuit, the first target voltage terminal is connected to the voltage output terminal through the third switch tube M3; the voltage output terminal is connected to the common ground terminal through the second switch tube M2 and the first switch tube M1 in sequence; The control terminal of the third switch tube M3 is connected to the input voltage terminal; the input voltage terminal is also connected to the common ground terminal through the third capacitor C3 and the first switch tube M1 in sequence; In the bias circuit, the first voltage terminal is connected to the common ground terminal through the tenth switch tube M10 and the ninth switch tube M9 in sequence; The second voltage terminal is connected to the common ground terminal through the eighth switch tube M8 and the seventh switch tube M7 in sequence; In the first bias protection circuit, the first target voltage terminal is connected to the first voltage terminal via the third resistor R3 and the twenty-fifth switch M25 in sequence; the first target voltage terminal is also grounded via the twenty-fourth switch M24; an enable terminal in the first bias protection circuit is connected to the control terminal of the twenty-fourth switch M24 via a first NOT gate I1; the control terminal of the twenty-fourth switch M24 is connected to the control terminal of the twenty-third switch M23 via a second NOT gate I2; and in the first bias protection circuit, a first bandgap reference current source is connected to the first voltage terminal via the twenty-third switch M23. The first target voltage terminal is further connected to the second voltage terminal via the fourth resistor R4 and the twenty-eighth switch tube M28 in sequence; the first target voltage terminal is further grounded via the twenty-seventh switch tube M27; the enable terminal is further connected to the control terminal of the twenty-seventh switch tube M27 via the first NOT gate I1; in the first bias protection circuit, the second bandgap reference current source is connected to the second voltage terminal via the twenty-sixth switch tube M26.

2. The input buffer according to claim 1, wherein The control end of the twenty-seventh switch tube M27 is connected to the control end of the twenty-sixth switch tube M26 through the third NOT gate I3 and the fourth NOT gate I4 in sequence.

3. The input buffer according to claim 1, wherein In the bias circuit, the first voltage terminal is connected to the control terminal of the eighth switch tube M8, the control terminal of the ninth switch tube M9, and the control terminal of the tenth switch tube M10 respectively; the second voltage terminal is connected to the control terminal of the seventh switch tube M7. The input buffer according to claim 1 , wherein: The circuit further includes a first linearity improvement circuit; In the first linearity boosting circuit, the first constant voltage terminal is connected to the first node via the fourteenth switch tube M14; the first constant voltage terminal is also connected to the first node via the thirteenth switch tube M13; the second constant voltage terminal is connected to the second node via the twelfth switch tube M12; the second constant voltage terminal is connected to the second node via the eleventh switch tube M11; and the first node and the second node are connected via a first capacitor C1. The first node is connected to the control terminal of the nineteenth switch tube M19 through the eighteenth switch tube M18; the first node is also connected to the control terminal of the nineteenth switch tube M19 through the seventeenth switch tube M17; the control terminal of the nineteenth switch tube M19 is connected to the input voltage terminal through the second capacitor C2; The second node is connected to the input voltage terminal through the sixteenth switch tube M16; the second node is also connected to the input voltage terminal through the fifteenth switch tube M15; The first target voltage terminal is connected to the output voltage terminal through the nineteenth switch tube M19 and the third switch tube M3 in sequence. The input buffer according to claim 4 , wherein: The fourteenth switch transistor M14, the eighteenth switch transistor M18, the twelfth switch transistor M12 and the sixteenth switch transistor M16 are NMOS transistors; The thirteenth switch transistor M13, the seventeenth switch transistor M17, the eleventh switch transistor M11 and the fifteenth switch transistor M15 are PMOS transistors; The control terminals of the twelfth switch tube M12, the fourteenth switch tube M14, the fifteenth switch tube M15 and the seventeenth switch tube M17 are connected to the first periodic signal; The control terminals of the eleventh switch tube M11 , the thirteenth switch tube M13 , the sixteenth switch tube M16 and the eighteenth switch tube M18 are connected to the second period signal. The input buffer according to claim 4 , wherein: The circuit further includes a second bias protection circuit; In the second bias protection circuit, the first target voltage terminal is connected to the third node through the second resistor R2; The third node is connected to the fourth node via the twenty-first switch tube M21; the fourth node is grounded via the first resistor R1; the control terminal of the twenty-first switch tube M21 is connected to the fourth node; the fourth node is also grounded via the twentieth switch tube M20; the control terminal of the twentieth switch tube M20 is connected to the enable terminal; The first constant voltage terminal is connected to the control terminal of the nineteenth switch tube M19 through the twenty-second switch tube M22; the control terminal of the twenty-second switch tube M22 is connected to the third node.

7. The input buffer according to any one of claims 1 to 6, characterized in that: The circuit includes a digital control module; In the digital control module, the digital enable terminal is connected to the control terminal of the twenty-ninth switch tube M29 through the fifth NOT gate I5; The second target voltage terminal is connected to the fifth node through the thirty-first switch tube M31; the fifth node is grounded through the twenty-ninth switch tube M29; the second target voltage terminal is also connected to the enable terminal through the thirty-second switch tube M32; the enable terminal is grounded through the thirtieth switch tube M30; The control terminal of the thirty-first switch tube M31 is connected to the enable terminal; the control terminal of the thirty-second switch tube M32 is connected to the fifth node; the control terminal of the thirtieth switch tube M30 is connected to the digital enable terminal; The enable terminal is connected to the inverting enable terminal through a sixth NOT gate I6. The input buffer according to claim 7 , wherein: The digital control module further includes a seventh NOT gate, an eighth NOT gate, a first AND gate, a second AND gate and a third AND gate; The first digital code signal is connected to the first input terminal of the first AND gate through the seventh NOT gate; the second digital code signal is connected to the second input terminal of the first AND gate; The third digital code signal is connected to the first input terminal of the second AND gate through the eighth NOT gate; the fourth digital code signal is connected to the second input terminal of the second AND gate; The output end of the first AND gate is connected to the first input end of the third AND gate; the output end of the second AND gate is connected to the second input end of the third AND gate; and the output end of the third AND gate is connected to the digital enable end.

9. The input buffer according to any one of claims 1 to 6, characterized in that: The circuit further includes a second linearity improving circuit; In the second linearity improvement circuit, the second target voltage terminal is connected to the seventh node through the sixth switch tube M6 and the fifth switch tube M5 in sequence; The seventh node is connected to the common ground through the fourth switch tube M4; the seventh node is connected to the control end of the second switch tube M2; the control end of the fourth switch tube M4 is grounded through the first switch tube M1.

10. An analog-to-digital converter, characterized in that: It comprises the input buffer according to any one of claims 1 to 9.

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