Three-dimensional memory and methods of making same

Abstract

The application belongs to the technical field of storage devices, and particularly relates to a three-dimensional memory and a three-dimensional memory manufacturing method. The application aims to solve the problem of large stress on the channel structure in the related art, which easily causes damage to the channel structure. The three-dimensional memory comprises a substrate and a stacked structure; the stacked structure comprises a plurality of conductive layers and a plurality of insulating layers; the stacked structure is provided with a plurality of channel holes, and the channel holes are provided with channel structures; the stacked structure is further provided with a plurality of dummy holes, the plurality of dummy holes are located between the channel holes, and the bottom of each dummy hole is in contact with a conductive layer; a connecting line is arranged in each dummy hole, and one end of the connecting line towards the substrate is bonded to the conductive layer corresponding to the bottom of the dummy hole where the connecting line is located. In this way, each conductive layer can be connected to peripheral devices through the corresponding connecting line; no step region needs to be arranged, and the stress on the channel structure caused by filling the insulating filler in the step region is avoided, thereby preventing damage to the channel structure.

Description

[0001] Case Analysis

[0002] This application is a divisional application of Chinese Patent No. 202010187579.2, filed on March 17, 2020, entitled "Three-dimensional memory and method for manufacturing three-dimensional memory". Technical Field

[0003] This invention relates to the field of storage device technology, and in particular to a three-dimensional memory and a method for manufacturing a three-dimensional memory. Background Technology

[0004] With the gradual development of storage device technology, 3D storage devices are widely used due to their high storage capacity and fast read and write speeds.

[0005] In related technologies, three-dimensional memory includes a stacked structure formed by alternating insulating and conductive layers. The stacked structure includes a core region and a stepped region located outside the core region. The core region has channel holes extending along the stacking direction, and channel structures are disposed within these channel holes. The channel structures and conductive layers form memory cells for storing data. In the stepped region, the insulating and conductive layers are stepped, and connecting lines extending along the stacking direction are disposed within the stepped region. Each connecting line is electrically connected to a conductive layer, thereby connecting each conductive layer to peripheral devices. An insulating filler is also disposed within the stepped region, filling the stepped region and surrounding each connecting line, so that the entire stacked structure is generally plate-shaped.

[0006] However, due to the large volume of the stepped area, the corresponding volume of the insulating filler filling the stepped area is also large. After the insulating filler fills the stepped area, the stress of the insulating filler on the core area of ​​the stacked structure is large, which can easily lead to deformation of the core area and damage to the channel structure. Summary of the Invention

[0007] In view of this, embodiments of the present invention provide a three-dimensional memory and a method for manufacturing a three-dimensional memory to solve the technical problem that the channel structure is subjected to large forces and is prone to damage.

[0008] This invention provides a three-dimensional memory comprising: a substrate and a stacked structure disposed on the substrate; the stacked structure includes a plurality of conductive layers and a plurality of insulating layers alternately stacked along a first direction; the stacked structure is provided with a plurality of channel holes, the channel holes penetrating each conductive layer and each insulating layer along the first direction, and a channel structure is provided within each channel hole; the stacked structure is also provided with a plurality of dummy holes, the plurality of dummy holes being located between each channel hole, the plurality of dummy holes extending towards the substrate along the first direction, and the bottom of each dummy hole contacting a conductive layer; each dummy hole is provided with a connecting line, the end of the connecting line facing the substrate being joined to the conductive layer corresponding to the bottom of the dummy hole where the connecting line is located, and the connecting line is insulated from the conductive layer penetrated by the connecting line.

[0009] In the three-dimensional memory with the above structure, the end of the connecting line facing the substrate is bonded to the conductive layer corresponding to the bottom of the dummy via where the connecting line is located, so that each conductive layer can be connected to the peripheral device through the corresponding connecting line. Compared with setting a stepped area on the stacked structure, where the conductive layer is connected to the peripheral device through the contact line in the stepped area, the three-dimensional memory provided in the embodiment of the present invention does not need to set a stepped area, so there is no need to set an insulating material in the stepped area, avoiding the problem of large stress on the channel structure caused by filling the stepped area with insulating material, and thus preventing damage to the channel structure.

[0010] In some embodiments that may include the above-described examples, a dummy hole is provided between two adjacent channel holes. This arrangement ensures that the dummy hole has a sufficiently large cross-sectional area.

[0011] In some embodiments that may include the above-described examples, the same conductive layer is in contact with the bottom of multiple dummy vias. This arrangement can improve the voltage uniformity of the conductive layer and reduce the latency of the 3D memory; in addition, it can facilitate the wiring of the 3D memory.

[0012] In some embodiments that may include the above-described examples, the dummy holes are arranged symmetrically with respect to a plane perpendicular to the substrate. This arrangement can improve the uniformity of the dummy holes.

[0013] In some embodiments that may include the above embodiments, each dummy hole is arranged in an array, each channel hole is arranged in an array, and a row of dummy holes is provided between two adjacent rows of channel holes.

[0014] In some embodiments that may include the above-described examples, the depths of the dummy holes located in the same column are the same. With this configuration, the connecting lines within the dummy holes in the same column are connected to the same conductive layer.

[0015] In some embodiments that may include the above embodiments, the depth of each dummy hole decreases in a stepwise manner along the direction from the center to the edge of the stacked structure.

[0016] In some embodiments that may include the above embodiments, the depth of each dummy hole increases progressively along the direction from the center to the edge of the stacked structure.

[0017] In some embodiments that may include the above embodiments, the dummy hole includes a circumferential sidewall surrounding the center line of the dummy hole and a hole bottom located at the bottom of the dummy hole, and an insulating sidewall is provided between the connecting line and the circumferential sidewall of the dummy hole.

[0018] This design avoids the connection line from coming into contact with the conductive layer through which it passes, thus preventing the same connection line from connecting to different conductive layers.

[0019] In some embodiments that may include the above embodiments, the insulating sidewall is any one of silicon oxide sidewall, silicon nitride sidewall, or silicon oxynitride sidewall.

[0020] In some embodiments that may include the above embodiments, the material of the connecting wire is the same as the material of the conductive layer.

[0021] This invention also provides a method for fabricating a three-dimensional memory, comprising:

[0022] A substrate is provided; a plurality of conductive layers and a plurality of insulating layers are alternately stacked on the substrate along a first direction to form a stacked structure; a plurality of channel holes are formed on the stacked structure, and a channel structure is formed within the channel holes, the channel holes penetrating each conductive layer and each insulating layer along the first direction; a plurality of dummy holes are formed on the stacked structure, the plurality of dummy holes being located between each channel hole, the plurality of dummy holes penetrating a portion of the conductive layer and a portion of the insulating layer along the first direction, and the bottom of each dummy hole contacting a conductive layer; a connecting line is formed within each dummy hole, one end of the connecting line facing the substrate is bonded to the conductive layer corresponding to the bottom of the dummy hole where the connecting line is located, and the connecting line is insulated from the conductive layer penetrated by the connecting line.

[0023] The three-dimensional memory fabricated using the above method has the following advantages: In this three-dimensional memory, the end of the connecting line facing the substrate is bonded to the conductive layer corresponding to the bottom of the dummy hole where the connecting line is located, allowing each conductive layer to be connected to peripheral devices via the corresponding connecting line. Compared to setting a stepped region on a stacked structure, where the conductive layer is connected to peripheral devices via contact lines within the stepped region, the fabrication method of the three-dimensional memory provided in this embodiment of the invention eliminates the need for a stepped region and therefore eliminates the need to fill the stepped region with insulating filler. This avoids excessive stress on the channel structure caused by filling the stepped region with insulating filler, thus preventing damage to the channel structure.

[0024] In some embodiments that may include the above embodiments, the step of forming a plurality of conductive layers and a plurality of insulating layers alternately stacked along a first direction on a substrate to constitute a stacked structure includes:

[0025] The steps of forming a plurality of transition layers and a plurality of insulating layers alternately stacked on a substrate along a first direction; forming a plurality of channel holes on the stacked structure; and forming a channel structure within the channel holes include: forming a plurality of channel holes penetrating each transition layer and each insulating layer along the first direction; and forming a channel structure within each channel hole.

[0026] In some embodiments that may include the above embodiments, a plurality of dummy vias are formed on the stacked structure, the plurality of dummy vias are located between each channel via, and the plurality of dummy vias penetrate a portion of the conductive layer and a portion of the insulating layer along a first direction, the step of each dummy via penetrating to a different conductive layer includes:

[0027] A first sacrificial layer is formed on the side of the stacked structure away from the substrate; multiple first intermediate dummy holes of different depths are formed on the first sacrificial layer, and the projection of the first intermediate dummy holes on the stacked structure is located between the multiple channel holes; a hole segment of the same depth is formed from the bottom of each first intermediate dummy hole toward the substrate, and the hole segment extends into the stacked structure, and the part of the hole segment located in the stacked structure forms a dummy hole.

[0028] With this configuration, the first sacrificial layer can protect the insulating and transition layers outside the dummy vias when etching the insulating and transition layers that make up the stacked structure, thereby preventing the insulating and transition layers outside the dummy vias from being damaged.

[0029] In some embodiments that may include the above embodiments, the step of forming a plurality of first intermediate dummy holes of different depths on the first sacrificial layer includes:

[0030] A second sacrificial layer is formed on the first sacrificial layer; multiple through-holes are formed on the second sacrificial layer, and the projection of the through-holes on the stacked structure is located between multiple channel holes; the regions exposed in each through-hole in the first sacrificial layer form first dummy hole segments of different depths, and each first dummy hole segment forms a first intermediate dummy hole.

[0031] With this setup, through holes are first formed on the second sacrificial layer, and then first dummy hole segments of different depths are made through the through holes to form the first intermediate dummy hole. This makes the first intermediate dummy hole have high positional accuracy and improves the processing accuracy of three-dimensional storage.

[0032] In some embodiments that may include the above embodiments, the step of forming a plurality of vias on the second sacrificial layer, wherein the projection of the vias onto the stacked structure lies between the plurality of channel vias, includes:

[0033] A third sacrificial layer is formed on the second sacrificial layer; a through-hole is formed on the third sacrificial layer, and the through-hole penetrates the second sacrificial layer; the third sacrificial layer is removed.

[0034] In some embodiments that may include the above embodiments, dummy hole segments of different depths are formed in the regions exposed within each via in the first sacrificial layer, and the step of forming each first intermediate dummy hole segment includes:

[0035] A fourth sacrificial layer is formed on the second sacrificial layer; a plurality of second intermediate dummy holes are formed on the fourth sacrificial layer, each second intermediate dummy hole being directly opposite to each through hole, and each second intermediate dummy hole having a different depth; a second dummy hole segment of the same depth is formed from the bottom of each second intermediate dummy hole toward the substrate, the second dummy hole segment extending into the first sacrificial layer, and the portion of the second dummy hole segment located in the first sacrificial layer forming a first intermediate dummy hole.

[0036] In some embodiments that may include the above embodiments, the three-dimensional memory fabrication method further includes, prior to the step of forming a connecting line within the dummy hole:

[0037] Using each dummy hole as a channel, each transition layer is replaced with each conductive layer.

[0038] In some embodiments that may include the above embodiments, the step of forming a connecting line within a dummy hole includes:

[0039] An insulating sidewall is formed on the circumferential sidewall and bottom of the dummy hole, and the insulating sidewall surrounds a cavity that is open at the top and closed at the bottom; a via is formed at the bottom of the cavity, and the via extends to the conductive layer corresponding to the bottom of the dummy hole; conductive material is deposited in the cavity and the via to form a connecting line.

[0040] This configuration prevents the connecting wire from contacting the conductive layer through which it passes, thus preventing the same connecting wire from being connected to a single conductive layer. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. It is obvious that the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 A schematic diagram of the structure of a three-dimensional memory provided in an embodiment of the present invention;

[0043] Figure 2 for Figure 1 A magnified view of a section at point A in the middle;

[0044] Figure 3 A top view of a three-dimensional memory provided in an embodiment of the present invention;

[0045] Figure 4A flowchart illustrating a method for fabricating a three-dimensional memory according to an embodiment of the present invention;

[0046] Figure 5 A schematic diagram illustrating the formation of a transition layer and an insulating layer on a substrate in a three-dimensional storage fabrication method provided in an embodiment of the present invention;

[0047] Figure 6 This is a schematic diagram of the channel structure formed in the three-dimensional storage fabrication method provided in the embodiment of the present invention;

[0048] Figure 7 This is a schematic diagram illustrating the formation of a first sacrificial layer, a second sacrificial layer, and a third sacrificial layer in the three-dimensional storage fabrication method provided in an embodiment of the present invention.

[0049] Figure 8 This is a schematic diagram illustrating the formation of through-holes in the three-dimensional storage fabrication method provided in an embodiment of the present invention;

[0050] Figure 9 This is a schematic diagram illustrating the formation of a fourth sacrificial layer after removing the third sacrificial layer in the three-dimensional storage fabrication method provided in this embodiment of the invention.

[0051] Figure 10 This is a schematic diagram illustrating the formation of a second dummy hole on the fourth sacrificial layer in the three-dimensional storage fabrication method provided in an embodiment of the present invention.

[0052] Figure 11 This is a schematic diagram illustrating the formation of a first dummy hole on a first sacrificial layer in the three-dimensional storage fabrication method provided in an embodiment of the present invention.

[0053] Figure 12 This is a schematic diagram illustrating the formation of a dummy hole in the three-dimensional storage fabrication method provided in an embodiment of the present invention;

[0054] Figure 13 A schematic diagram illustrating the removal of the first and second sacrificial layers in the three-dimensional storage fabrication method provided in this embodiment of the invention;

[0055] Figure 14 This is a schematic diagram illustrating the formation of insulating sidewalls in the three-dimensional storage fabrication method provided in an embodiment of the present invention.

[0056] Figure 15 This is a schematic diagram of the formation of a conductive layer and connecting lines in the three-dimensional storage fabrication method provided in an embodiment of the present invention.

[0057] Explanation of reference numerals in the attached figures:

[0058] 10. Substrate; 20. Stacked structure; 30. Channel via;

[0059] 40. Dummy hole; 201. Insulating layer; 202. Conductive layer;

[0060] 203. Transition layer; 301. Channel structure; 401. Connecting line;

[0061] 402. Insulating sidewall; 403. Via; 501. First sacrificial layer;

[0062] 502. Second sacrificial layer; 503. Third sacrificial layer; 504. First intermediate dummy hole; 505. Through hole; 506. Fourth sacrificial layer; 507. Second intermediate dummy hole. Detailed Implementation

[0063] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0064] Three-dimensional memory enables the storage and retrieval of data in three-dimensional space, giving it high storage capacity. A three-dimensional memory includes a substrate and a stacked structure disposed on the substrate. The stacked structure is formed by alternating stacks of multiple insulating layers and multiple conductive layers. The stacked structure includes a core region and a stepped region located outside the core region. A channel hole extending perpendicular to the substrate is disposed within the core region, and a channel structure is disposed within the channel hole. The channel structure and the conductive layers form a memory cell, which is used to store data. Each channel structure and each conductive layer form a memory string.

[0065] The stepped region of the stacked structure is located outside the core region. When fabricating a 3D memory, the conductive and insulating layers in the stepped region are first distributed in a stepped manner, and at the same time, a depression is formed in the stepped region. Then, an insulating filler is formed in the depression by evaporation or deposition. Multiple dummy holes are formed on the insulating filler in a direction perpendicular to the substrate, and the depth of the dummy holes is different so that the bottom of each dummy hole contacts a corresponding conductive layer. A connecting line is formed in the dummy hole, and the connecting line contacts the conductive layer corresponding to the bottom of the dummy hole to realize the connection between the connecting line and the conductive layer. The connecting line enables the electrical connection between the conductive layer and the peripheral devices for data storage and retrieval.

[0066] However, due to the large volume of the stepped area, after the insulating filler is formed in the stepped area by means of vapor deposition or deposition, the volume of the insulating filler will change when the temperature of the insulating filler gradually returns to room temperature. This causes the insulating filler to exert a force on the stacked structure, which in turn causes the channel structure located in the core area to be stressed, which can easily lead to damage to the channel structure.

[0067] In this embodiment of the invention, there is no need to set a stepped area in the stacked structure. The connecting wire is set in the core area of ​​the stacked structure and located between the channel holes, so as to avoid the force of the insulating filler set in the stepped area on the core area, thereby preventing damage to the channel structure.

[0068] The three-dimensional memory provided in this embodiment of the invention can be a NAND flash memory or other three-dimensional memory, and this embodiment does not limit it.

[0069] like Figure 1 As shown, the three-dimensional memory includes a substrate 10 and a stacked structure 20 disposed on the substrate 10. The substrate 10 may be plate-shaped and may be mainly composed of single crystal silicon. However, this embodiment is not limited to this. The substrate 10 may also be mainly composed of silicon germanium or germanium.

[0070] The stacked structure 20 disposed on the substrate 10 is composed of a plurality of conductive layers 202 and a plurality of insulating layers 201 alternately stacked along a first direction. That is, the conductive layers 202 and insulating layers 201 are formed alternately along the first direction. For example, an insulating layer 201 is first formed on a conductive layer 202, and then a conductive layer 202 is formed on the insulating layer 201, and so on to form the stacked structure 20. It should be noted that the first direction is perpendicular to the plane on which the substrate 10 is located (e.g., ...). Figure 1 (in the y-direction) or approximately perpendicular direction.

[0071] The conductive layer 202 in the stacked structure 20 is made of a conductive material. For example, the conductive layer 202 can be made of one or more of tungsten, cobalt, copper, and aluminum. Of course, the conductive layer 202 can also be made of a non-metallic conductive material such as metal silicide. The insulating layer 201 located between two adjacent conductive layers 202 is made of an insulating material. For example, the insulating layer 201 can be made of one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0072] Continue to refer to Figure 1 The stacked structure 20 is provided with a plurality of channel holes 30, which penetrate each conductive layer 202 and insulating layer 201 along a first direction, and a channel structure 301 is provided inside the channel hole 30; wherein, the channel hole 30 can be columnar, frustum-shaped or prismatic, etc.; the channel structure 301 provided inside the channel hole 30 has the same shape as the channel hole 30.

[0073] The channel structure 301 disposed within the channel hole 30 may include a semiconductor channel layer and a dielectric layer located outside the semiconductor channel layer. The semiconductor channel layer may be composed of one or more of amorphous silicon, polycrystalline silicon, or monocrystalline silicon. The dielectric layer may include a tunnel layer, a memory cell layer, and a barrier layer. The tunnel layer may be composed of silicon oxide and / or silicon nitride. The memory cell layer may be composed of one or more of silicon nitride, silicon oxynitride, or silicon. The barrier layer may be composed of insulating materials such as silicon oxide and / or silicon nitride.

[0074] Each channel structure 301 and each conductive layer 202 can form a storage unit, and data can be stored in the storage unit; each channel structure 301 and each conductive layer 202 form a storage string to realize the storage and retrieval of data in three dimensions, so that the three-dimensional memory has a high storage capacity.

[0075] In this embodiment, multiple channel holes 30 are provided on the stacked structure 20, and the multiple channel holes 30 are arranged at intervals on the stacked structure 20. For example, the channel holes 30 can be arranged in an array on the stacked structure 20 to achieve a uniform distribution of the channel holes 30, that is, multiple channel structures 301 are arranged in multiple rows and columns in the stacked structure 20. Of course, the channel holes 30 can also be arranged randomly on the stacked structure 20, and the multiple channel structures 301 are also arranged randomly accordingly.

[0076] Continue to refer to Figures 1-3 In this embodiment, the stacked structure 20 is also provided with a plurality of dummy holes 40. The plurality of dummy holes 40 are arranged at intervals on the stacked structure 20. For example, the plurality of dummy holes 40 can be arranged in an array on the stacked structure 20. Of course, the plurality of dummy holes 40 can also be arranged randomly on the stacked structure 20.

[0077] Furthermore, each dummy via 40 is disposed between the channel vias 30. Specifically, since the distance between the channel vias 30 in the three-dimensional memory is small, a dummy via 40 can be disposed between two adjacent channel vias 30 to ensure that the dummy via 40 has a sufficiently large cross-sectional area. Of course, when there is sufficient distance between the channel vias 30, multiple dummy vias 40 can also be disposed between adjacent channel vias 30. Each dummy via 40 extends toward the substrate 10 along the first direction, and each dummy via 40 penetrates to a different conductive layer 202; that is, each conductive layer 202 is bonded to the bottom of a corresponding dummy via 40.

[0078] In this embodiment, each dummy hole 40 is provided with a connecting line 401. The end of the connecting line 401 facing the substrate 10 is joined to the conductive layer 202 corresponding to the bottom of the dummy hole 40, so that the connecting line 401 is electrically connected to the conductive layer 202 corresponding to the bottom of the dummy hole 40. The end of the connecting line 401 away from the substrate 10 can be connected to a peripheral device, so that the peripheral device and the conductive layer 202 are electrically connected through each connecting line 401. It is worth noting that the peripheral device can be a transistor disposed on the side of the stacked structure 20 away from the substrate 10.

[0079] When a dummy hole 40 is provided between two adjacent channel holes 30, a connecting line 401 is provided between two adjacent channel structures 301 accordingly; when multiple dummy holes 40 are provided between two adjacent channel holes 30, multiple connecting lines 401 are provided between adjacent adjacent channel structures 301. The material of the connecting line 401 can be the same as the material of the conductive layer 202, or the material of the connecting line 401 can be different from that of the conductive layer 202, as long as the electrical connection between the conductive layer 202 and the peripheral device can be achieved through the connecting line 401.

[0080] In the three-dimensional storage device provided in this embodiment, the stacked structure 20 is provided with a channel hole 30 that penetrates each conductive layer 202 and insulating layer 201 along a first direction. The channel hole 30 is provided with a channel structure 301, and a plurality of dummy holes 40 are provided between the channel holes 30. Each dummy hole 40 has a different depth so that the bottom of each dummy hole 40 contacts a conductive layer 202. A connecting line 401 is provided in each dummy hole 40. The end of the connecting line 401 facing the substrate 10 is joined to the conductive layer 202 corresponding to the bottom of the dummy hole 40 where the connecting line 401 is located, so that each conductive layer 202 can be connected to the peripheral device through the corresponding connecting line 401. Compared to setting a stepped area on the stacked structure, where the conductive layer is connected to the peripheral device through the connecting lines in the stepped area, in this embodiment, both the channel structure 301 and the connecting lines 401 are set in the core area of ​​the stacked structure 20. There is no need to set a stepped area outside the core area, so there is no need to set an insulating filler in the stepped area. This avoids the channel structure 301 being subjected to greater stress due to filling the stepped area with insulating filler, and thus can prevent damage to the channel structure 301.

[0081] Continue to refer to Figures 1-3 To achieve the connection between each conductive layer 202 and each channel structure 301, in the implementation where the channel structures 301 are arranged in an array, each conductive layer 202 includes multiple gate lines disposed on the same layer. These gate lines are arranged parallel to each other and spaced apart. A row of channel structures 301 passes through the same gate line, or a column of channel structures 301 passes through the same gate line. Specifically, with... Figure 1 and Figure 3 Taking the orientation shown as an example, the row direction can be parallel to the x-direction, and the column direction is the z-direction, which is perpendicular to both the x-direction and the y-direction.

[0082] In the above implementation, a row of channel structures 301 runs through the same gate line, and a dummy hole 40 is provided between adjacent channel holes 30. Correspondingly, a row of dummy holes 40 is provided between two adjacent rows of channel holes 30. A connecting line 401 is provided in each dummy hole 40, and the end of the connecting line 401 facing the substrate 10 is connected to the conductive layer 202 corresponding to the bottom of the dummy hole 40 where the connecting line 401 is located. That is to say, a row of connecting lines 401 is provided between two rows of channel structures 301.

[0083] Furthermore, the depth of each column of dummy vias 40 is the same, so that each column of connecting lines 401 is connected to the same conductive layer 202. Specifically, the number of dummy vias 40 in a column of dummy vias 40 is the same as the number of gate lines in the same conductive layer 202. Each gate line in the same conductive layer 202 is connected to a column of connecting lines 401, and each gate line is provided with a corresponding connecting line 401, so that the connection between each gate line in a conductive layer 202 and the peripheral device can be realized through the connecting lines 401 in a column of dummy vias 40.

[0084] In one optional implementation, the same conductive layer 202 contacts the bottom of multiple dummy vias 40; that is, the same conductive layer 202 corresponds to multiple connecting lines 401, and all the connecting lines 401 corresponding to the same conductive layer 202 are connected to the same peripheral device. Since the conductive layer 202 itself has a certain resistance, the above arrangement can improve the voltage uniformity of the conductive layer 202 and reduce the latency of the 3D memory. Furthermore, a wiring layer can be provided on the side of the stacked structure 20 away from the substrate 10, connecting to each connecting line 401 of the same conductive layer 202. This wiring layer connects to the corresponding peripheral device, thus enriching the connection positions between the peripheral device and the conductive layer 202 compared to using a stepped region, facilitating the wiring of the 3D memory. It is worth noting that the number of dummy vias 40 corresponding to the same conductive layer 202 can be two, three, four, etc.

[0085] Furthermore, each dummy hole 40 is symmetrically arranged with respect to a plane perpendicular to the substrate 10, which makes the dummy holes 40 more evenly distributed.

[0086] Continue to refer to Figure 1 In one feasible manner, the stacked structure 20 can be a multi-layer structure (such as a two-layer structure), although Figure 1The connection method of the conductive layer 202 in the lower structure is not shown, but it is not difficult to imagine that each conductive layer 202 can also be connected to the external device through the corresponding dummy hole 40 and the connecting line 401 set in the dummy hole 40.

[0087] Continue to refer to Figure 1 and Figure 3 In one embodiment, the depth of each dummy via 40 decreases progressively from the center to the edge of the stacked structure 20. In an array configuration where both the channel structures 301 and the connecting lines 401 are arranged, and a column of connecting lines 401 is provided between every two adjacent columns of channel structures 301, and each column of connecting lines 401 connects to different gate lines within the same conductive layer 202, the depth of each column of dummy vias 40 is the same. In this case, the column of dummy vias 40 located in the middle of the stacked structure 20 has a greater depth, and the depth of each column of dummy vias 40 gradually decreases from this column towards the two side edges. The magnitude of the decrease in depth between adjacent dummy vias 40 can be an integer multiple of the sum of the thickness of the conductive layer 202 and the thickness of the insulating layer 201. Figure 1 Taking the structure shown as an example, the depth difference between two adjacent dummy holes 40 is equal to the sum of the thickness of the conductive layer 202 and the thickness of the insulating layer 201. Of course, in other implementations, the dummy hole 40 located at the center of the stacked structure 20 has the greatest depth, and the depths of the dummy holes 40 around it are all less than the depth of the dummy hole 40, and the depth of each dummy hole 40 gradually decreases in the direction towards the edge of the stacked structure 20.

[0088] In another embodiment, the depth of each dummy via 40 increases progressively from the center to the edge of the stacked structure 20. In an implementation where both the channel structures 301 and the connecting lines 401 are arranged in an array, with a column of connecting lines 401 between every two adjacent columns of channel structures 301, and each column of connecting lines 401 connects to different gate lines within the same conductive layer 202, the depth of each column of dummy vias 40 is the same. In this case, the column of dummy vias 40 located in the middle of the stacked structure 20 has a smaller depth. From this column of dummy vias 40 towards the two side edges, the depth of each column of dummy vias 40 gradually increases. The increase in depth of adjacent dummy vias 40 can be an integer multiple of the sum of the thickness of the conductive layer 202 and the thickness of the insulating layer 201. For example, the depth difference between two adjacent dummy vias 40 is equal to the sum of the thickness of the conductive layer 202 and the thickness of the insulating layer 201. Of course, in other implementations, the dummy hole 40 located at the center of the stacked structure 20 has the smallest depth. The depths of the dummy holes 40 around the dummy hole 40 are all greater than the depth of the dummy hole 40, and the depth of each dummy hole 40 gradually increases in the direction towards the edge of the stacked structure 20.

[0089] Continue to refer to Figure 1 and Figure 2In the above implementation, the dummy hole 40 includes a bottom hole and a circumferential sidewall surrounding the center line of the dummy hole 40. To prevent the connecting line 401 from contacting the conductive layer 202 through which it passes, thus causing the same connecting line 401 to be electrically connected to different conductive layers 202 simultaneously, a gap can be formed between the connecting line 401 and the circumferential sidewall of the dummy hole 40 through which it passes. Alternatively, an insulating sidewall 402 can be provided between the connecting line 401 and the circumferential sidewall of the dummy hole 40. For example, as... Figure 1 As shown, the connecting line 401 in the dummy hole 40 near the center extends along the y direction. The connecting line 401 passes through seven conductive layers 202 from the top layer of the stacked structure 20 and contacts the eighth conductive layer 202. At this time, the insulating sidewall 402 is disposed between the seven conductive layers through which the connecting line 401 passes and the connecting line 401, so as to electrically insulate the connecting line 401 and the seven conductive layers 202 through which the connecting line 401 passes.

[0090] The insulating sidewall 402 is made of insulating material. For example, the insulating sidewall 402 can be a silicon oxide sidewall, or a silicon nitride sidewall, or a silicon oxynitride sidewall. Of course, the insulating sidewall 402 can also be made of other insulating materials. This embodiment does not limit the material of the insulating sidewall 402.

[0091] This invention also provides a method for manufacturing a three-dimensional memory. This method can be used to manufacture the three-dimensional memory provided in the foregoing embodiments. The three-dimensional memory manufactured by this method does not require the setting of a stepped area, thereby avoiding the large stress on the channel structure caused by filling the stepped area with insulating filler, and thus preventing damage to the channel structure.

[0092] like Figure 4 As shown, the method for fabricating a three-dimensional memory in this embodiment of the invention includes:

[0093] S101, Provide substrate.

[0094] The substrate can be plate-shaped, and the substrate material can be of various types, such as single crystal silicon, silicon germanium, germanium, etc.

[0095] S102. Multiple conductive layers and multiple insulating layers are alternately stacked on the substrate along a first direction to form a stacked structure. The insulating and conductive layers can be formed by methods such as chemical vapor deposition (CVD) and atomic layer deposition (ALD).

[0096] In one embodiment, a conductive layer can be formed on a substrate first, followed by an insulating layer on the conductive layer, and then another conductive layer on the insulating layer. This process can be repeated to form multiple conductive layers and multiple insulating layers that are stacked alternately.

[0097] In another embodiment, the specific steps of forming a plurality of conductive layers and a plurality of insulating layers alternately stacked along a first direction on a substrate to constitute a stacked structure include:

[0098] Multiple transition layers 203 and multiple insulating layers 201 are alternately stacked on the substrate 10 along a first direction; the structure formed after this step is as follows: Figure 5 As shown. Specifically, a separator layer made of insulating material can be formed on the substrate 10 first, then a transition layer 203 can be formed on the separator layer, followed by an insulating layer 201 on the transition layer 203, and then another transition layer 203 can be formed on the insulating layer 201, and so on, to form a plurality of alternately stacked transition layers 203 and insulating layers 201. In subsequent steps, each transition layer 203 is replaced with a conductive layer to form a stacked structure composed of conductive layers and insulating layers 201, wherein the separator layer can separate the conductive layer located near the substrate 10 from the substrate 10.

[0099] In the above implementation, the insulating layer 201 can be composed of one or more of silicon oxide, silicon nitride, and silicon oxynitride. The conductive layer 2 can be composed of one or more of tungsten, cobalt, copper, and aluminum. Of course, the conductive layer can also be composed of non-metallic conductive materials such as titanium nitride. The transition layer 203 can be composed of materials such as silicon nitride or silicon oxynitride. It is worth noting that the transition layer 203 is made of a different material than the insulating layer 201 to avoid damaging the insulating layer 201 when removing the transition layer 203 in subsequent steps.

[0100] S103. Multiple channel holes are formed on the stacked structure, and a channel structure is formed within the channel holes. The channel holes penetrate each conductive layer and each insulating layer along a first direction. The structure formed after this step is as follows: Figure 6 As shown, the channel structure 301 may include a semiconductor channel layer and a dielectric layer located outside the semiconductor channel layer. The semiconductor channel layer may be composed of amorphous silicon, polycrystalline silicon or monocrystalline silicon. The dielectric layer may include a tunnel layer, a memory cell layer and a barrier layer. The tunnel layer may be composed of materials such as silicon oxide and silicon nitride. The memory cell layer may be composed of materials such as silicon nitride, silicon oxynitride or silicon. The barrier layer may be composed of insulating materials such as silicon oxide and silicon nitride.

[0101] Each channel structure 301 and each conductive layer 202 can form a storage unit, and data can be stored in the storage unit; each channel structure and each conductive layer form a storage string to realize the storage and retrieval of data in three dimensions, so that the three-dimensional memory has a high storage capacity.

[0102] In the above steps, the steps of forming multiple channel holes 30 on the stacked structure and forming a channel structure 301 within the channel holes 30 specifically include:

[0103] First, a plurality of channel holes 30 are formed in the alternately stacked transition layer 203 and insulating layer 201, penetrating each transition layer 203 and each insulating layer 201 along a first direction; then, a channel structure 301 is formed in each channel hole 30.

[0104] The channel hole 30 is a through-hole passing through each transition layer 203 and each insulating layer 201, with its lower end extending to the surface of the substrate 10. For example, the channel hole 30 extending perpendicular to the substrate 10 can be formed on the insulating layer 201 and the transition layer 203 by methods such as photolithography or dry etching. The channel structure 301 can be formed by methods such as chemical vapor deposition (CVD) and atomic layer deposition (ALD).

[0105] Please continue to refer to this. Figure 4 In this embodiment, after forming the channel structure 301, the method further includes:

[0106] S104. Multiple dummy holes are formed on the stacked structure. The multiple dummy holes are located between each channel hole. The multiple dummy holes penetrate part of the conductive layer and part of the insulating layer along the first direction, and the bottom of each dummy hole contacts a conductive layer.

[0107] For example, multiple dummy vias are arranged in an array, i.e., multiple dummy vias are arranged in multiple rows and columns; multiple channel vias 30 are arranged in an array, i.e., multiple channel vias 30 are arranged in multiple rows and columns, and a column of dummy vias is provided between two adjacent columns of channel vias 30. Furthermore, the depth of each column of dummy vias is the same; the column of dummy vias located at the center of the insulating layer 201 has the greatest depth, and the depth of the dummy vias gradually decreases from the center to the edge, so that after the transition layer 203 is replaced with a conductive layer, the bottom of each column of dummy vias is located on the same conductive layer 202.

[0108] In one embodiment, a plurality of dummy vias are formed on the stacked structure 20, the plurality of dummy vias being located between each channel via 30, and the plurality of dummy vias penetrating a portion of the conductive layer and a portion of the insulating layer 201 along a first direction. The specific steps for each dummy via penetrating to a different conductive layer include:

[0109] First, a first sacrificial layer 501 is formed on the side of the stacked structure 20 facing away from the substrate 10.

[0110] Subsequently, a plurality of first intermediate dummy holes 504 of varying depths are formed on the first sacrificial layer 501. The projection of the first intermediate dummy holes 504 onto the stacked structure lies between the plurality of channel holes 30. Each first intermediate dummy hole 504 is a hole formed in the first sacrificial layer 501 with an opening at the top and a closed bottom. Along the direction from the center to the edge of the stacked structure 20, adjacent first intermediate dummy holes 504 have different depths. The resulting structure is as follows: Figure 11 As shown.

[0111] Next, segments of the same depth are etched from the bottom of each first intermediate dummy hole 504 toward the substrate 10. These segments extend into the stacked structure 20. Because the depths of the first intermediate dummy holes 504 differ, after etching segments of the same depth toward the stacked structure 20 starting from the bottom of each first intermediate dummy hole 504, the depths of the segments within the stacked structure 20 differ. The portion of the segment located within the stacked structure forms a dummy hole 40. The resulting structure is as follows: Figure 12 As shown.

[0112] In the above embodiments, in addition to forming the first intermediate dummy hole 504, the first sacrificial layer 501 can also protect the insulating layer 201 and transition layer 203 outside the dummy hole 40 during etching, thereby preventing damage to the insulating layer 201 and transition layer 203 outside the dummy hole 40. The material of the first sacrificial layer 501 can be various; for example, the first sacrificial layer 501 can be mainly composed of amorphous carbon, but it can also be composed of other materials.

[0113] In the above embodiments, the first intermediate dummy hole 504 can be formed by dry etching or wet etching. Similarly, the hole segment extending from the bottom of the first intermediate dummy hole 504 toward the substrate 10 to the transition layer 203 and the insulating layer 201 can also be formed by dry etching or wet etching.

[0114] Furthermore, the step of forming a plurality of first intermediate dummy holes 504 of different depths on the first sacrificial layer 501 includes:

[0115] A second sacrificial layer 502 is formed on the first sacrificial layer 501; as Figure 11 As shown, the second sacrificial layer 502 is located on the first sacrificial layer 501. The second sacrificial layer 502 can be mainly composed of materials such as silicon oxynitride and can be formed by deposition.

[0116] Next, a plurality of through holes 505 are formed on the second sacrificial layer 502, and the projection of the through holes 505 on the stacked structure is located between a plurality of channel holes 30; in the first sacrificial layer 501, the regions exposed in each through hole 505 form first dummy hole segments of different depths, and each first dummy hole segment forms a first intermediate dummy hole 504.

[0117] In the above-mentioned process of fabricating the first intermediate dummy hole 504, a through hole 505 is first formed on the second sacrificial layer 502, and then a first dummy hole segment of different depth is fabricated in the first sacrificial layer 501 located in the through hole 505 to form the first intermediate dummy hole 504. By adopting the above-mentioned fabrication method, the first intermediate dummy hole 504 has high positional accuracy and improves the processing accuracy of three-dimensional storage.

[0118] Furthermore, the step of forming a plurality of through holes 505 on the second sacrificial layer 502, wherein the projection of the through holes 505 on the stacked structure is located between the plurality of channel holes 30, specifically includes:

[0119] First, a third sacrificial layer 503 is formed on the second sacrificial layer 502, such as Figure 7 As shown, the third sacrificial layer 503 is located on the second sacrificial layer 502; as Figure 8 As shown, a through-hole 505 is then formed on the third sacrificial layer 503, the through-hole 505 penetrating the third sacrificial layer 503 and the second sacrificial layer 502; then, the third sacrificial layer 503 is removed.

[0120] In the above manufacturing method, the third sacrificial layer 503 can be photoresist, and a first exposure area is formed on the third sacrificial layer 503 by means of masking, exposure, development, etc. Then, the third sacrificial layer 503 in the first exposure area and the second sacrificial layer 502 opposite to the first exposure area are removed by etching, thereby forming a via 505, which improves the positional accuracy of the via 505.

[0121] In another embodiment, the step of forming dummy hole segments of different depths in the regions exposed within each through-hole 505 in the first sacrificial layer 501, and forming each first intermediate dummy hole 40 by each dummy hole segment, includes:

[0122] After removing the third sacrificial layer 503, a fourth sacrificial layer 506 is first formed on the second sacrificial layer 502, such as... Figure 9 As shown, the fourth sacrificial layer 506 is located on the second sacrificial layer 502.

[0123] Then, a plurality of second intermediate dummy holes 507 are formed on the fourth sacrificial layer 506, each second intermediate dummy hole 507 being directly opposite each through hole 505, and each second intermediate dummy hole 507 having a different depth.

[0124] Next, a second dummy hole segment of the same depth is formed from the bottom of each second intermediate dummy hole 507 toward the substrate 10. The second dummy hole segment extends into the first sacrificial layer 501, and the portion of the second dummy hole segment located in the first sacrificial layer 501 forms the first intermediate dummy hole 504.

[0125] For example, the fourth sacrificial layer 506 can be photoresist, so that a second exposure area can be formed on the fourth sacrificial layer 506 by means of masking, exposure, development, etc., and the second exposure area is directly opposite to the via 505. Then, the fourth sacrificial layer 506 in the second exposure area is removed by etching to form the second intermediate dummy via 507.

[0126] To ensure that the depths of the second intermediate dummy holes 507 are different, the optical proximity correction (OPC) method can be used to adjust the masks corresponding to each second exposure area before exposure, so that the light transmittance of each mask corresponding to the second exposure area is different. As a result, during the same exposure time, the depths of each second exposure area extending into the substrate 10 are different. Therefore, after removing the fourth sacrificial layer 506 in the second exposure area, second intermediate dummy holes 507 with different depths can be formed.

[0127] After the second intermediate dummy hole 507 is formed, a second dummy hole segment of the same depth can be formed from the bottom of the second intermediate dummy hole 507 toward the substrate 10 by etching. The second dummy hole segment extends into the first sacrificial layer 501, thereby forming a first dummy hole 504 of different depth.

[0128] Continue to refer to Figure 4 After forming the first dummy holes 504 of different depths, the above-mentioned method for fabricating the three-dimensional memory further includes:

[0129] S105. A connecting line is formed in each dummy hole. The end of the connecting line facing the substrate is bonded to the conductive layer corresponding to the bottom of the dummy hole where the connecting line is located, and the connecting line is insulated from the conductive layer through which the connecting line passes.

[0130] For example, interconnects can be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), and other methods. The interconnects can be mainly made of metals such as tungsten, cobalt, copper, and aluminum. Of course, the interconnects can also be made of non-metallic conductive materials such as titanium nitride. The interconnects and the conductive layer can be made of the same material to ensure that there is a small resistance at the contact between the interconnects and the conductive layer, thereby improving the performance of the three-dimensional memory.

[0131] like Figure 14 and Figure 15 As shown, prior to the step of forming the connecting line within the dummy hole 40, the three-dimensional memory fabrication method further includes:

[0132] Using each dummy hole 40 as a channel, each transition layer 203 is replaced with each conductive layer 202, thereby forming alternating stacked conductive layers 202 and insulating layers 201 to constitute a stacked structure 20.

[0133] like Figure 13 and Figure 14 As shown, in this embodiment, the step of forming the connecting line 401 within the dummy hole 40 includes:

[0134] First, an insulating sidewall 402 is formed on the inner sidewall and bottom wall of the dummy hole 40. The insulating sidewall 402 covers the circumferential sidewall and bottom wall of the dummy hole 40. The insulating sidewall 402 forms a cavity. The cavity has an opening at one end away from the substrate 10 and a closed end at the other end close to the substrate 10.

[0135] Then, a via 403 is formed at the bottom of the insulating sidewall 402, and the via 403 extends to the conductive layer 202 corresponding to the bottom of the dummy hole 40. For example, the bottom of the cavity, i.e. the bottom of the insulating sidewall, can be etched by etching to form a via 403 that communicates with the surfaces of the cavity and the conductive layer respectively.

[0136] Subsequently, conductive material is deposited in the cavity and through-hole 403 to form the connecting line 401.

[0137] In the above embodiments, the insulating sidewall 402 is made of insulating material. For example, the insulating sidewall 402 can be a silicon oxide sidewall, or a silicon nitride sidewall, or a silicon oxynitride sidewall. Of course, the insulating sidewall 402 can also be made of other insulating materials. This embodiment does not limit the material of the insulating sidewall 402.

[0138] like Figures 13-15 As shown, in the above implementation, after forming the dummy hole 40, insulating sidewalls 402 can be formed on both the circumferential sidewall and the bottom of the dummy hole 40. Then, vias 403 are formed on the insulating sidewalls 402 at the bottom of the dummy hole 40 by etching or other means. Then, the transition layer 203 corresponding to the bottom of the dummy hole 40 is removed using the dummy hole 40 to form a blank layer. Then, conductive material is formed in each blank layer and in each dummy hole 40 to form each conductive layer 202 and each connecting line 401.

[0139] For ease of understanding, the method for manufacturing the three-dimensional storage device described in the above embodiments can be summarized as including the following steps:

[0140] A substrate 10 is provided, and a plurality of alternating transition layers 203 and a plurality of insulating layers 201 are formed on the substrate 10. The structure formed in this step is as follows: Figure 5 As shown.

[0141] Subsequently, channel holes 30 are formed penetrating each transition layer 203 and insulating layer 201, and channel structures 301 are formed within the channel holes 30. The structure formed in this step is as follows: Figure 6 As shown.

[0142] Next, the first sacrificial layer 501, the second sacrificial layer 502, and the third sacrificial layer 503 are formed sequentially. The structure formed in this step is as follows: Figure 7 As shown.

[0143] Subsequently, vias 505 are formed on the third sacrificial layer 503 by etching. The vias 505 penetrate the second sacrificial layer 502. The structure formed in this step is as follows: Figure 8 As shown.

[0144] The third sacrificial layer 503 is then removed, and a fourth sacrificial layer 506 is formed on top of the third sacrificial layer 503. The structure formed in this step is as follows: Figure 9 As shown.

[0145] Subsequently, using an optical proximity effect correction method, second exposure regions of varying depths are formed on the fourth sacrificial layer 506. Each second exposure region corresponds one-to-one with a via 505 on the second sacrificial layer 502. The second exposure region projected to the center of the substrate 10 has a greater depth, and the depth of each second exposure region gradually decreases towards the edge. The fourth sacrificial layer 506 corresponding to each second exposure region is removed to form each second intermediate dummy via 507. Furthermore, the second intermediate dummy via 507 projected to the center of the substrate 10 has a greater depth, and the depth of each second intermediate dummy via 507 gradually decreases towards the edge. The structure formed in this step is as follows: Figure 10 As shown.

[0146] Next, a second dummy hole segment of the same depth is formed at the bottom of the second intermediate dummy hole 40 towards the substrate 10. The second dummy hole segment extends into the first sacrificial layer 501 to form a first intermediate dummy hole 504. The first intermediate dummy hole 504 projected to the center of the substrate 10 has a larger depth, and the depth of each first intermediate dummy hole 504 decreases in the direction from the first intermediate dummy hole 504 towards the edge. The structure formed by this step is as follows: Figure 11 As shown.

[0147] Subsequently, a hole segment of the same depth is formed from the bottom of the first intermediate dummy hole 504 towards the substrate 10, thereby forming a dummy hole 40 on the transition layer 203 and the insulating layer 201. The structure formed by this step is as follows: Figure 12 As shown.

[0148] Remove the first sacrificial layer 501 and the second sacrificial layer 502; the structure formed by this step is as follows Figure 13 As shown. Then, an insulating sidewall 402 is formed on the circumferential sidewall and bottom of the dummy hole 40; subsequently, a via 403 is formed on the insulating sidewall 402 at the bottom of the dummy hole 40. The structure formed in this step is as follows. Figure 14 As shown.

[0149] Next, the transition layer 203 corresponding to the bottom of the dummy hole 40 is removed using the dummy hole 40 to form a blank layer. A conductive layer 202 is then formed within the blank layer and the dummy hole 40, thereby forming a connecting line 401 connecting the conductive layer 202. The structure formed in this step is as follows: Figure 15 As shown.

[0150] The three-dimensional memory fabricated by the method provided in this embodiment has a stacked structure 20 with a channel hole 30 that penetrates each conductive layer 202 and insulating layer 201 along a first direction. The channel hole 30 has a channel structure 301, and multiple dummy holes 40 are also provided between the channel holes 30. Each dummy hole 40 has a different depth so that each dummy hole 40 penetrates to a different conductive layer 202. A connecting line 401 is provided in each dummy hole 40. The end of the connecting line 401 facing the substrate 10 is joined to the conductive layer 202 corresponding to the bottom of the dummy hole 40 where the connecting line 401 is located, so that each conductive layer 202 can be connected to peripheral devices through the corresponding connecting line 401. Compared to setting a stepped area on the stacked structure, where the conductive layer is connected to the peripheral device through the connecting lines in the stepped area, in this embodiment, both the channel structure 301 and the connecting lines 401 are set in the core area of ​​the stacked structure 20. There is no need to set a stepped area outside the core area, so there is no need to set an insulating filler in the stepped area. This avoids the channel structure 301 being subjected to greater stress due to filling the stepped area with insulating filler, and thus can prevent damage to the channel structure 301.

[0151] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A three-dimensional memory, characterized in that, include: A stacked structure comprising a plurality of conductive layers and a plurality of insulating layers alternately stacked along a first direction; A channel structure that penetrates the stacked structure along a first direction; A connecting line, the connecting line being located between the plurality of the channel structures, passing through the stacked structure along a first direction to different lengths in the stacked structure, and connected to at least one of the conductive layers; An insulating sidewall that surrounds the connecting line; Along the X direction from the center to the edge of the stacked structure, the length of the connecting line in the first direction increases or decreases sequentially.

2. The three-dimensional memory of claim 1, wherein, A connecting line is provided between two adjacent channel structures.

3. The three-dimensional memory of claim 1, wherein, The connecting lines are arranged in an array; The channel structure is arranged in an array; A connecting line is provided between two adjacent columns of the channel structure; Each column of connecting lines is positioned in the Z direction, which is perpendicular to the X direction.

4. The three-dimensional memory of claim 3, wherein, The connecting lines located in the same column are connected to the same conductive layer.

5. The three-dimensional memory of claim 3, wherein, The connecting lines located in the same column have the same length in the first direction.

6. The three-dimensional memory of claim 1, wherein, The length difference between adjacent connecting lines in a first direction is an integer multiple of the sum of the thicknesses of the conductive layer and the insulating layer.

7. The three-dimensional memory of claim 1, wherein, The connecting line is insulated from the conductive layer through which it passes.

8. The three-dimensional memory of claim 1, wherein, The insulating sidewall is any one of silicon oxide sidewall, silicon nitride sidewall, or silicon oxynitride sidewall.

9. The three-dimensional memory of claim 1, wherein, The connecting wire is made of the same material as the conductive layer.

10. The three-dimensional memory of claim 1, wherein, The bottom of each of the connecting lines is in contact with one of the conductive layers.

11. A three-dimensional memory, comprising: include: A stacked structure comprising a plurality of conductive layers and a plurality of insulating layers alternately stacked along a first direction; A channel structure that penetrates the stacked structure along a first direction; A connecting line, the connecting line being located between the plurality of the channel structures, passing through the stacked structure along a first direction to different lengths in the stacked structure, and connected to at least one of the conductive layers; An insulating sidewall that surrounds the connecting line; The conductive layer on the same layer is in contact with the multiple connecting lines; The connecting lines are arranged symmetrically with respect to a plane perpendicular to the stacked structure.

12. The three-dimensional memory as recited in claim 11, further comprising: A connecting line is provided between two adjacent channel structures.

13. The three-dimensional memory as recited in claim 11, further comprising: The connecting lines are arranged in an array; The channel structure is arranged in an array; A connecting line is provided between two adjacent columns of the channel structure; The connecting lines in each column are arranged in the Z direction.

14. The three-dimensional memory as recited in claim 13, further comprising: The connecting lines located in the same column are connected to the same conductive layer.

15. The three-dimensional memory as recited in claim 13, further comprising: The connecting lines located in the same column have the same length in the first direction.

16. The three-dimensional memory as recited in claim 11, further comprising: The length difference between adjacent connecting lines in a first direction is an integer multiple of the sum of the thicknesses of the conductive layer and the insulating layer.

17. The three-dimensional memory as recited in claim 11, further comprising: The connecting line is insulated from the conductive layer through which it passes.

18. The three-dimensional memory as recited in claim 11, further comprising: The insulating sidewall is any one of silicon oxide sidewall, silicon nitride sidewall, or silicon oxynitride sidewall.

19. The three-dimensional memory as recited in claim 11, further comprising: The connecting wire is made of the same material as the conductive layer.

20. The three-dimensional memory as recited in claim 11, further comprising: The bottom of each of the connecting lines is in contact with one of the conductive layers.

21. The three-dimensional memory as recited in claim 11, further comprising: Along the X direction from the center to the edge of the stacked structure, the length of the connecting line in the first direction increases or decreases sequentially.

22. A three-dimensional memory fabrication method comprising: include: A transition layer and an insulating layer are formed, which are alternately stacked along the first direction; A channel hole is formed through the transition layer and the insulating layer, and a channel structure is formed within the channel hole; A stacked structure of alternating conductive layers and insulating layers is formed by replacing the transition layer with a conductive layer; Connecting lines are formed through the stacked structure and extend to different lengths, the connecting lines being connected to at least one of the conductive layers; the connecting lines are located between the plurality of the channel structures; Wherein, along the X direction from the center to the edge of the stacked structure, the length of the connecting line in the first direction increases or decreases sequentially.

23. The method for fabricating a three-dimensional memory according to claim 22, characterized in that, The step of forming connecting lines extending through the stacked structure to different lengths includes: A dummy hole is formed that extends through the transition layer and the insulating layer to different depths, and the bottom of the dummy hole contacts at least one layer of the transition layer; A connecting line is formed within the dummy hole.

24. The method for fabricating a three-dimensional memory according to claim 23, characterized in that, The formation of the dummy holes at different depths includes: A first sacrificial layer is formed on the alternatingly stacked transition layer and the insulating layer; Multiple first intermediate dummy holes of different depths are formed on the first sacrificial layer; In the X direction, from the center to the edge of the alternately stacked transition layer and insulating layer, the depth of the first intermediate dummy hole increases or decreases sequentially.

25. The three-dimensional memory fabrication method of claim 24, wherein, The step of forming a plurality of first intermediate dummy holes of different depths on the first sacrificial layer includes: A second sacrificial layer is formed on the first sacrificial layer; Multiple vias are formed on the second sacrificial layer, and the projections of the vias onto the alternately stacked transition layers and insulating layers are located between the multiple channel vias; In the first sacrificial layer, the regions exposed within each of the vias form first dummy hole segments of different depths, and each first dummy hole segment forms a first intermediate dummy hole.

26. The three-dimensional memory fabrication method of claim 25, wherein, The step of forming a plurality of vias on the second sacrificial layer, wherein the projections of the vias onto the stacked structure lie between the plurality of channel vias, includes: A third sacrificial layer is formed on the second sacrificial layer; A through-hole is formed in the third sacrificial layer, and the through-hole penetrates the second sacrificial layer; Remove the third sacrificial layer.

27. The three-dimensional memory fabrication method of claim 25 or 26, wherein, The step of forming dummy hole segments of different depths in the regions exposed within each of the vias in the first sacrificial layer, wherein each of the dummy hole segments forms each of the first intermediate dummy holes, includes: A fourth sacrificial layer is formed on the second sacrificial layer; Multiple second intermediate dummy holes are formed on the fourth sacrificial layer, each second intermediate dummy hole corresponding to each of the through holes, and each second intermediate dummy hole has a different depth. From the bottom of each of the second intermediate dummy holes, a second dummy hole segment of the same depth is formed in the first direction. The second dummy hole segment extends into the first sacrificial layer, and the portion of the second dummy hole segment located in the first sacrificial layer forms the first intermediate dummy hole.

28. The three-dimensional memory fabrication method of claim 23, wherein, The step of forming a connecting line within the dummy hole includes: An insulating sidewall is formed on the circumferential sidewall and bottom of the dummy hole, and the insulating sidewall surrounds a cavity that is open at the top and closed at the bottom. A via is formed at the bottom of the cavity, and the via extends to the conductive layer corresponding to the bottom of the dummy hole; Conductive material is deposited in the cavity and the via to form the connecting line.

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