A neuromorphic transistor memory and its fabrication method

Abstract

This application discloses a neuromorphic transistor memory and its fabrication method. The transistor is an organic field-effect transistor, comprising a gate, a dielectric layer, a semiconductor layer, and electrodes. The dielectric layer contains a multi-stimulus responsive material donor-acceptor Stenhouse adduct DASA and a polymer, and the semiconductor layer contains an organic semiconductor material. The neuromorphic transistor memory of this application can achieve tunable multiple storage characteristics, providing a general design guideline for the development of intelligent storage devices. It has great potential in artificial intelligence (AI), data encryption, and anti-counterfeiting. Furthermore, it features low electrolysis risk and low leakage current. The fabrication method of this application is simple and controllable, with mild reaction conditions and strong industrial applicability.

Description

Technical Field

[0001] This application relates to a neuromorphic transistor memory and its fabrication method, belonging to the field of organic field-effect transistors. Background Technology

[0002] The human brain possesses sensory storage, short-term storage, and long-term storage capabilities. Sensory storage detects information from the external world in the form of chemical and physical stimuli and uses it for different purposes. Short-term storage allows humans to recall specific information about anything within a short period. Long-term storage enables humans to store information for extended periods, either consciously (directly) or unconsciously (indirectly). These storage behaviors allow humans to store, recall, and process information on demand, ensuring that humans can not only solve the most complex tasks but also react quickly to changes in the external environment. Developing intelligent "brain-like" storage devices with multiple data storage modes plays an increasingly important role in modern information technologies such as machine learning and artificial neural networks. This allows external information to be acquired through chemical and physical stimuli and enables efficient information storage, exchange, and processing. As mentioned earlier, this intelligent memory behavior ensures that humans can not only solve the most complex tasks but also react quickly to changes in the external environment. Therefore, developing "brain-like" memory devices with multiple data storage methods will undoubtedly play a crucial role in the development of modern information technology. However, to date, most traditional storage devices, such as WORM (write-once-read-many), RAM (randomaccess memory), ROM (read-only memory), and flash memory, cannot switch their storage characteristics once they are manufactured, resulting in poor adjustability. This significantly limits the application of these storage devices in intelligent systems. Summary of the Invention

[0003] To address the aforementioned shortcomings in existing technologies, this application proposes a solution based on the multi-stimulus-responsive properties of stimuli-responsive material donor-acceptor Stenhouse adducts (DASA). For example, under white light irradiation or increased humidity, DASA transforms from a colored "linear" form to a colorless "closed-loop" form; conversely, heating or reducing humidity allows DASA to revert to its "linear" form. Furthermore, DASA itself can serve as an excellent dielectric charge trapping device, resulting in DASA-based transistors exhibiting good storage characteristics. Combining this with the multi-stimulus-responsive properties of DASA will contribute to the diversification of transistor storage behavior. Additionally, most polymers are insulators, possessing excellent electrical insulation properties, low dielectric loss, and low conductivity, ensuring that transistor memory is protected from breakdown under high-voltage operation. Therefore, blending DASA and polymers in the dielectric layer is expected to improve the dielectric performance of transistors.

[0004] According to one aspect of this application, a neuromorphic transistor memory is provided, wherein the transistor is an organic field-effect transistor, comprising: a gate, a dielectric layer, a semiconductor layer, and electrodes.

[0005] The dielectric layer comprises a multi-stimulus responsive material donor-receptor Stenhouse adduct DASA and a polymer, and the semiconductor layer comprises an organic semiconductor material.

[0006] Optionally, the organic field-effect transistor includes, from bottom to top, the gate, the dielectric layer, the semiconductor layer, and the electrode.

[0007] Optionally, the electrode includes a source electrode and a drain electrode.

[0008] Optionally, the DASA is selected from at least one of the following compounds:

[0009]

[0010] Not limited to theory, the DASA (including the above 9 specific compounds) have the following common structure, which causes the DASA molecule to undergo corresponding "isomerization" when subjected to different types of stimuli (such as electric field, light, heat, humidity, etc.), resulting in changes in molecular configuration and / or conformation, thereby affecting its properties such as conductivity to varying degrees.

[0011]

[0012] Optionally, the DASA and the polymer exist in a blended form in the dielectric layer.

[0013] Optionally, the polymer is selected from at least one of polymethyl methacrylate, polystyrene, polyvinyl alcohol, and polypentafluorophenol. This application does not impose any particular limitation on the molecular weight or degree of polymerization of the polymer.

[0014] Optionally, the DASA has a mass percentage content of 1-50 wt%, based on the total weight of the DASA and the polymer.

[0015] Optionally, the mass percentage of the DASA is independently selected from any value or a range between any two of 1wt%, 2wt%, 5wt%, 10wt%, 12wt%, 15wt%, 17wt%, 20wt%, 23wt%, 25wt%, 28wt%, 30wt%, 32wt%, 35wt%, 37wt%, 40wt%, 43wt%, 45wt%, 48wt%, and 50wt%, based on the total weight of the DASA and the polymer.

[0016] Preferably, the DASA has a mass percentage content of 25-30 wt%, based on the total weight of the DASA and the polymer.

[0017] Optionally, the gate comprises a silicon wafer.

[0018] Optionally, the organic semiconductor material is selected from pentane, 2,7-decyl[1]benzothiophene[3,2-B][1]benzothiophene, 2,7-dioctylbenzo[LMN][3,8]phenanthroline-1,3,6,8-(2H,7H)-tetraone, 6,13-bis(triisopropylsilylethynyl)pentane, poly(3-hexylthiophene-2,5-diyl), N,N'-di(4-heptyl)-3, At least one of 4,9,10-perylenedicarboximide, poly(2,5-bis(3-tetradecylthiophene-2-yl)thieno[3,2-B]thiophene), and poly[[1,2,3,6,7,8-hexahydro-2,7-bis(2-octyldodecyl)-1,3,6,8-dioxobenzo[LMN][3,8]phenanthroline-4,9-diyl][2,2'-bithiophene]-5,5'-diyl].

[0019] Optionally, the thickness of the dielectric layer is 100-250 nm.

[0020] Optionally, the thickness of the dielectric layer is independently selected from any value or a range between 100nm, 110nm, 120nm, 130nm, 140nm, 150nm, 160nm, 170nm, 180nm, 190nm, 200nm, 210nm, 220nm, 230nm, 240nm, and 250nm.

[0021] Optionally, the thickness of the semiconductor layer is 20-200 nm.

[0022] Optionally, the thickness of the semiconductor layer is independently selected from any value or a range between 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 110nm, 120nm, 130nm, 140nm, 150nm, 160nm, 170nm, 180nm, 190nm, and 200nm.

[0023] Optionally, the neuromorphic transistor memory has multiple storage modes, such as three.

[0024] The inventors of this application have discovered that, due to the donor-acceptor molecular configuration and extended π-conjugation, DASA acts as a trap to capture charges in the dielectric layer, giving the transistor excellent data storage capabilities. Furthermore, the light, heat, and humidity responsiveness of DASA enriches the transistor's storage behavior and data "write-erase" modes. When data is written via humidity, the transistor behaves similarly to "sensory storage," as the data disappears immediately upon removal of humidity. When data is written via light, the transistor exhibits volatile storage characteristics and can be erased by heating, similar to the human brain's "short-term memory." When data is written via heating, the transistor exhibits non-volatile characteristics, although its data may be erased by light irradiation, similar to the human brain's "long-term memory." Finally, when the transistor is programmed with an electric field, permanent long-term memory is generated. Additionally, the polymer according to this application has advantages such as low dielectric loss, high breakdown strength, light weight, and high power density. Therefore, neuromorphic transistor memories with multiple (e.g., triple) memory characteristics can be realized through the blending of DASA and polymers.

[0025] According to another aspect of this application, a method for fabricating the neuromorphic transistor memory as described above is provided, comprising:

[0026] a) Dissolve the DASA and the polymer in an organic solvent to prepare a blend solution of DASA and the polymer;

[0027] b) The blended solution is coated onto the gate and cured to form the dielectric layer;

[0028] c) The organic semiconductor material is vapor-deposited onto the dielectric layer to form the semiconductor layer;

[0029] d) Connect the electrode to the surface of the semiconductor layer.

[0030] Optionally, in step a), the organic solvent is selected from at least one of chloroform, o-dichlorobenzene, chlorobenzene, tetrahydrofuran, toluene, and 1,4-dioxane.

[0031] Optionally, step a) includes: dissolving the DASA and the polymer in the organic solvent to prepare a blend solution, wherein the polymer is selected from at least one of polymethyl methacrylate, polystyrene, polyvinyl alcohol, and polypentafluorophenol.

[0032] Optionally, in step b), the coating method is spin coating.

[0033] Optionally, the spin coating is performed using a spin coater.

[0034] Optionally, the spin coating rotation speed is 1,000-5,000 rpm and the time is 10-100 s.

[0035] Optionally, the spin coating speed is independently selected from any value or a range between any two of 1,000 rpm, 1,200 rpm, 1,500 rpm, 1,700 rpm, 2,000 rpm, 2,300 rpm, 2,500 rpm, 2,800 rpm, 3,000 rpm, 3,200 rpm, 3,500 rpm, 3,700 rpm, 4,000 rpm, 4,300 rpm, 4,500 rpm, 4,800 rpm, and 5,000 rpm.

[0036] Preferably, the spin coating speed is 2,000-3,000 rpm.

[0037] Optionally, the spin coating time is independently selected from any value or a range between 10s, 15s, 20s, 25s, 30s, 35s, 40s, 45s, 50s, 55s, 60s, 65s, 70s, 75s, 80s, 85s, 90s, 95s, and 100s.

[0038] Preferably, the spin coating time is 25-35 seconds.

[0039] Optionally, the curing method is annealing or ultraviolet curing.

[0040] Preferably, the curing method is annealing curing.

[0041] Optionally, the annealing temperature is 50-200℃ and the time is 1-120min.

[0042] Optionally, the annealing temperature is independently selected from any value or a range between any two of 50°C, 60°C, 70°C, 80°C, 90°C, 100°C, 110°C, 120°C, 130°C, 140°C, 150°C, 160°C, 170°C, 180°C, 190°C, and 200°C.

[0043] Preferably, the annealing temperature is 50-55°C.

[0044] Optionally, the annealing time is independently selected from any value or a range between 1 min, 3 min, 5 min, 7 min, 9 min, 10 min, 15 min, 20 min, 25 min, 30 min, 35 min, 40 min, 45 min, 50 min, 55 min, 60 min, 70 min, 80 min, 90 min, 100 min, 110 min, and 120 min.

[0045] Preferably, the annealing time is 10-15 minutes.

[0046] Optionally, the annealing is performed in an inert gas atmosphere.

[0047] According to this application, depending on the type of organic semiconductor material, the annealing can be performed in an air atmosphere or an inactive gas atmosphere.

[0048] Optionally, the inactive gas is selected from at least one of nitrogen, argon, and helium.

[0049] Optionally, the UV curing power is 6-100W and the time is 1-120min.

[0050] Optionally, the power of the UV curing is independently selected from any value or a range between 6W, 8W, 10W, 15W, 20W, 25W, 30W, 35W, 40W, 45W, 50W, 55W, 60W, 65W, 70W, 75W, 80W, 85W, 90W, 95W, and 100W.

[0051] Optionally, the UV curing time is independently selected from any value or a range between any two of 1 min, 3 min, 5 min, 7 min, 9 min, 10 min, 15 min, 20 min, 25 min, 30 min, 35 min, 40 min, 45 min, 50 min, 55 min, 60 min, 70 min, 80 min, 90 min, 100 min, 110 min, and 120 min.

[0052] Optionally, in step c), the organic semiconductor material is used by vapor deposition of a solid organic semiconductor material or spin-coating of a solution of an organic semiconductor material with a solvent added. That is, the organic semiconductor material can be used in the form of a pure substance or a solution.

[0053] In the case of using a solution, the solvent for the organic semiconductor material may optionally be selected from at least one of chloroform, o-dichlorobenzene, chlorobenzene, tetrahydrofuran, toluene, and 1,4-dioxane.

[0054] In one embodiment, the solution of the organic semiconductor material may be selected from at least one of the following: a chloroform solution of poly[[1,2,3,6,7,8-hexahydro-2,7-bis(2-octyldodecyl)-1,3,6,8-dioxobenzo[LMN][3,8]phenanthroline-4,9-diyl][2,2'-bithiophene]-5,5'-diyl], a chloroform solution of poly(2,5-bis(3-tetradecylthiophene-2-yl)thieno[3,2-B]thiophene), and a toluene solution of poly(3-hexylthiophene-2,5-diyl).

[0055] Optionally, in step c), the concentration of the organic semiconductor material solution is independently selected from any value or a range between 3 mg / ml, 4 mg / ml, 5 mg / ml, 6 mg / ml, 7 mg / ml, 8 mg / ml, 9 mg / ml, and 10 mg / ml.

[0056] Optionally, in step c), the evaporation rate is

[0057] Optionally, the evaporation rate is independently selected from... Any value in the range or any value between the two.

[0058] Optionally, the thickness of the vapor deposition is 20-200 nm.

[0059] Optionally, the thickness of the vapor deposition is independently selected from any value or a range between 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 110nm, 120nm, 130nm, 140nm, 150nm, 160nm, 170nm, 180nm, 190nm, and 200nm.

[0060] Optionally, in step d), the connection method is vapor deposition.

[0061] Optionally, the evaporation rate is

[0062] Optionally, the evaporation rate is independently selected from... Any value in the range or any value between the two.

[0063] Optionally, the thickness of the vapor deposition is 20-100 nm.

[0064] Optionally, the thickness of the vapor deposition is independently selected from any value or a range between any two of 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm, 55nm, 60nm, 65nm, 70nm, 75nm, 80nm, 85nm, 90nm, 95nm, and 100nm.

[0065] Optionally, the method includes the following steps:

[0066] 1) Wash the silicon wafer that serves as the gate;

[0067] 2) Prepare a blend solution of the DASA and the polymer in the organic solvent;

[0068] 3) Spin-coating the blended solution onto the silicon wafer, annealing and curing to obtain a silicon wafer coated with a dielectric layer;

[0069] 4) The organic semiconductor material is vapor-deposited onto the silicon wafer coated with the dielectric layer to obtain a silicon-DASA / polymer-organic semiconductor device;

[0070] 5) Connect the source electrode and drain electrode to the surface of the organic semiconductor side of the device, respectively.

[0071] Optionally, in step 1), the washing process involves sequentially using deionized water, acetone, and ethanol for at least 15 minutes.

[0072] According to another aspect of this application, the use of multi-stimulus responsive materials such as DASA for fabricating neuromorphic transistor memories is provided. The features and technical solutions, and combinations thereof, of the neuromorphic transistor memory and its fabrication method are the same as those described above.

[0073] The beneficial effects that this application can produce include:

[0074] 1) The neuromorphic transistor memory of this application can realize tunable multiple storage feature behaviors, providing a general design guideline for the development of intelligent storage devices, and has great prospects in artificial intelligence (AI), data encryption, anti-counterfeiting and other fields.

[0075] 2) The dielectric layer of the neuromorphic transistor memory of this application contains DASA-polymer blend material, which has the effects of low electrolysis risk and low leakage current.

[0076] 3) The preparation method of this application is simple and controllable, the reaction conditions are mild, and it has strong industrial applicability. Attached Figure Description

[0077] Figure 1 This is a schematic diagram of the structure of the capacitor device prepared in Embodiment 1 of this application.

[0078] Figure 2 This is a schematic diagram of the structure of the transistor prepared in Embodiment 2 of this application.

[0079] Figure 3 The results are the test results of the capacitor device prepared in Example 1 of this application, where (a) is the current density of the capacitor device, and (b) is the capacitance of the capacitor device and the dielectric constant of the DASA / PMMA film.

[0080] Figure 4 The test results are for the capacitor device prepared in Example 1 and the transistor prepared in Example 2 of this application, where (a) is the curve of capacitance change caused by temperature in the capacitor device and (b) is the curve of current change caused by temperature in the transistor.

[0081] Figure 5 The results are the test results of the capacitor device prepared in Example 1 and the transistor prepared in Example 2 of this application, where (a) is the curve of capacitance change caused by humidity in the capacitor device and (b) is the curve of current change caused by humidity in the transistor.

[0082] Figure 6 The test results are for the transistors prepared in Example 2 of this application, where (a) is the hysteresis curve, (b) is the curve of optical programming and thermal erasure, (c) is the curve of thermal programming and optical erasure, and (d) is the curve of high humidity programming and low humidity erasure.

[0083] Figure 7 The test results are for the transistors prepared in Embodiment 2 of this application, where (a) is the curve of negative voltage programming and positive voltage erasure, (b) is the curve of negative voltage programming and optical erasure, (c) is the curve of negative voltage programming and thermal erasure, and (d) is the curve of negative voltage programming and humidity erasure. Detailed Implementation

[0084] As previously stated, this application relates to a neuromorphic transistor memory with three data storage modes achieved using a single smart molecule-doped dielectric layer. The organic field-effect transistor according to this application can be fabricated according to the following steps: first, a blend of DASA and polymethyl methacrylate (PMMA) is spin-coated onto a silicon wafer as a dielectric layer; then, an organic semiconductor layer is deposited on the resulting dielectric layer; and finally, source (S) and drain (D) electrodes are fabricated on the semiconductor layer. Compared to conventional storage devices that typically exhibit only a single storage mode, this application introduces DASA into the PMMA dielectric layer and successfully achieves a multifunctional transistor memory with three storage modes (i.e., sensing, short-term, and long-term storage). When programmed by humidity, the transistor behaves similarly to "sensing storage" because the data disappears immediately after the humidity is removed. When programmed by light, the transistor exhibits volatile storage and can be erased by heating, similar to "short-term storage." Finally, when the transistor is programmed by heat or an electric field, "long-term storage" is achieved. The neuromorphic transistor memory according to this application is particularly suitable for fields such as artificial intelligence (AI), data encryption, and anti-counterfeiting.

[0085] In the context of this application, programming in a transistor memory refers to writing information, and erasing refers to deleting information.

[0086] The technical solutions of this application will be further described in detail below with reference to specific embodiments. It should be understood that the following embodiments are only used to illustrate and explain this application, and should not be construed as limiting the scope of protection of this application. All technical solutions implemented based on the above content of this application are covered within the scope of protection claimed by this application.

[0087] Experimental methods not specified in the following examples are generally performed under standard conditions or as recommended by the manufacturer.

[0088] Unless otherwise stated, all raw materials and reagents used in the embodiments of this application were purchased commercially from Shanghai Aladdin Biochemical Technology Co., Ltd., and the DASA specifically used in the embodiments are the following compounds:

[0089]

[0090] The analytical instruments used in the embodiments of this application are as follows:

[0091] The capacitance and current density of capacitors were tested and analyzed using a precision LCR digital bridge tester (model TH2827). The hysteresis return curves of transistors and the write / erase programming of devices were tested and analyzed using a semiconductor parameter analyzer (model Keithley SC-4200).

[0092] Example 1

[0093] The highly doped silicon wafer was sequentially ultrasonically cleaned in soapy water, deionized water, acetone, and ethanol for 20 min each, and then dried with N2. First, a 20 mg / ml polymethyl methacrylate solution was prepared using chloroform as the solvent; then, a 20 mg / ml DASA solution was prepared using chloroform as the solvent. The obtained DASA and methyl methacrylate solutions were blended at a DASA to PMMA mass ratio of 3:7. The blended solution was then spin-coated onto the cleaned silicon substrate (2,000 rpm for 30 s), followed by annealing at 50°C for 10 min under N2 to obtain a dielectric layer (190 nm thick). The dielectric layer was then deposited using an evaporator. A 50 nm thick Au electrode (5,600 × 200 μm) was fabricated on the dielectric layer using a mask at a certain rate, thereby obtaining a capacitor device, the structure of which is simplified as follows: Figure 1 As shown. The capacitance and current density of the obtained capacitor were measured using a precision LCR digital bridge tester (TH2827), and the results are as follows. Figure 3 As shown.

[0094] The capacitance changes of the 30% DASA / PMMA capacitors prepared above were verified after exposure to light and heating. Figure 4 As shown in (a), the first point represents the initial state, the second point represents the capacitance value after 20 minutes of light exposure (the capacitance of the device increased by 35% compared to the initial state), and the third point represents the capacitance value returning to the initial value after heat treatment. Multiple light and heating cycles demonstrate the stable switching of the capacitor. Furthermore, the switching behavior of the capacitor under humidity conditions was verified, as shown below. Figure 5 As shown in (a), the capacitance of the 30% DASA / PMMA device increases by nearly 70% when the relative humidity increases from 40% to 80%. Similarly, the stability of the device under multiple humidity changes was demonstrated by testing multiple cycles.

[0095] Example 2

[0096] The highly doped silicon wafer was sequentially ultrasonically cleaned in soapy water, deionized water, acetone, and ethanol for 20 min each, and then dried with N2. First, a 20 mg / ml polymethyl methacrylate solution was prepared using chloroform as the solvent; then, a 20 mg / ml DASA solution was prepared using chloroform as the solvent. The obtained DASA and methyl methacrylate solutions were blended at a DASA to PMMA mass ratio of 3:7. The blended solution was then spin-coated onto the cleaned silicon substrate (2,000 rpm for 30 s), followed by annealing at 50°C for 10 min under N2 to obtain a dielectric layer (190 nm thick). The dielectric layer was then deposited using an evaporator. A 50 nm thick 2,7-didecyl[1]benzothiophene[3,2-B][1]benzothiophene semiconductor layer was deposited on the dielectric layer at a rate of [missing information]. A vapor deposition apparatus was used to [missing information]. At a rate of [missing information], an Au electrode with a thickness of 50 nm (5,600 × 200 μm) was deposited on the semiconductor layer using a mask, thereby fabricating a transistor device, the structure of which is simplified as follows: Figure 2 As shown. The light switching, humidity switching, hysteresis round-trip curves, and write / erase programming of the transistor device were measured using a semiconductor parameter analyzer (Keithley SC-4200). The results are as follows. Figures 4 to 7 As shown.

[0097] like Figure 4 As shown in (b), compared to the first point in the initial state, the 30% DASA / PMMA transistor device showed a 250% increase in current after illumination. The third point indicates that the current returned to its initial value after 10 minutes of reheating. Furthermore, the current switching could be repeated multiple times under alternating heating and white light illumination. In addition, it was verified that changes in relative humidity could effectively regulate the current magnitude of the transistor, such as... Figure 5 As shown in (b), when the humidity changes from 40% to 80%, the current of the transistor based on the 30% DASA / PMMA dielectric layer increases by nearly 80%.

[0098] like Figure 6 As shown in (a), a hysteresis loop was obtained through a dual-scan test (drain voltage = -30V, gate voltage scanned from 1V to -30V, and then scanned back to 1V), which verifies that the DASA / PMMA device has storage capability. Next, the data storage modes of this transistor memory under different "write" and "erase" conditions were investigated. First, see... Figure 6 (b) When data is written to the memory through 20 minutes of light illumination, the current increases by an order of magnitude and then slowly decays after the white light is removed, indicating that the device has short-term memory capabilities. See also Figure 6 (c) When data was written by heating to 50°C (10 min), the current dropped by about an order of magnitude, and the current value was well maintained even after the heat source was removed, indicating the long-term memory behavior of the device; furthermore, the current could be effectively recovered by illumination, which is equivalent to data deletion. See also Figure 6 (d) When the transistor is programmed by increasing the humidity from 40% to 80%, the current immediately increases by an order of magnitude, and the current remains at a high level only when the humidity is kept at 80%; once the humidity drops to 40%, the current also immediately decreases. This result can be regarded as a sensory memory.

[0099] In addition, other stimulation methods are used to erase information electrically written to transistors via negative voltage. For example... Figure 7 As shown in (a) to (d), none of the four methods—positive voltage, 20 minutes of light exposure, 10 minutes of heating at 50°C, and increasing humidity to 80%—could fully restore the current, thus preventing data erasure. Therefore, when data is programmed with voltage, it can be considered as permanent memory.

[0100] The above descriptions are merely several embodiments of this application and are not intended to limit this application in any way. Although this application discloses preferred embodiments as described above, these embodiments are not intended to limit this application. Any modifications or alterations made by those skilled in the art using the disclosed technical content without departing from the scope of the technical solution of this application are equivalent to equivalent implementations and fall within the scope of the technical solution of this application.

Claims

1. A neuromorphic transistor memory, characterized in that, The transistor exhibits an organic field effect. A transistor includes: a gate, a dielectric layer, a semiconductor layer, and electrodes. The dielectric layer comprises a multi-stimulus responsive material donor-receptor Stenhouse adduct. The semiconductor layer comprises DASA and polymers, and the semiconductor layer contains organic semiconductor materials. The electrode includes a source electrode and a drain electrode; The DASA is selected from at least one of the following compounds: ， In the dielectric layer, the polymer and the DASA are co-existing; The polymer is selected from at least one of polymethyl methacrylate, polystyrene, polyvinyl alcohol, and polypentafluorophenol; The DASA content is 1-50 wt%, based on the total mass of the DASA and the polymer.

2. The neuromorphic transistor memory according to claim 1, characterized in that, The DASA has a mass percentage content of 25-30 wt%, based on the total mass of the DASA and the polymer.

3. The neuromorphic transistor memory according to claim 1, characterized in that, The gate comprises a silicon wafer; The organic semiconductor material is selected from pentane, 2,7-didecyl[1]benzothiophene[3,2-B][1]benzothiophene, 2,7-dioctylbenzo[LMN][3,8]phenanthroline-1,3,6,8-(2H,7H)-tetraone, 6,13-bis(triisopropylsilylethynyl)pentane, poly(3-hexylthiophene-2,5-diyl), N,N'-bis(4-heptyl)-3,4, At least one of 9,10-perylenedicarboximide, poly(2,5-bis(3-tetradecylthiophene-2-yl)thieno[3,2-B]thiophene), and poly[[1,2,3,6,7,8-hexahydro-2,7-bis(2-octyldodecyl)-1,3,6,8-dioxobenzo[LMN][3,8]phenanthroline-4,9-diyl][2,2'-bithiophene]-5,5'-diyl]; The thickness of the dielectric layer is 100-250 nm; The thickness of the semiconductor layer is 20-200 nm.

4. A method for fabricating a neuromorphic transistor memory according to any one of claims 1 to 3, characterized in that, include: a) Dissolve the DASA and the polymer in an organic solvent to prepare a blend solution of DASA and the polymer; b) The blended solution is coated onto the gate and cured to form the dielectric layer; c) The organic semiconductor material is vapor-deposited onto the dielectric layer to form the semiconductor layer; d) Connect the electrode to the surface of the semiconductor layer.

5. The method according to claim 4, characterized in that, In step a), the organic solvent is selected from at least one of chloroform, o-dichlorobenzene, chlorobenzene, tetrahydrofuran, toluene, and 1,4-dioxane.

6. The method according to claim 4, characterized in that, In step b), the coating method is spin coating; The spin coating speed is 1,000-5,000 rpm, and the time is 10-100 s; The curing method is annealing or ultraviolet curing; The annealing temperature is 50-200℃, and the time is 1-120 min; The annealing is performed in an inert gas atmosphere; The inactive gas is selected from at least one of nitrogen, argon, and helium; The UV curing power is 6-100W, and the time is 1-120min.

7. The method according to claim 4, characterized in that, In step c), the evaporation rate is 0.1-1.0 Å / s; The thickness of the vapor deposition is 20-200 nm; In step d), the connection method is vapor deposition; The evaporation rate is 0.1-1.0 Å / s; The thickness of the vapor deposition is 20-100 nm.

8. The method according to claim 4, characterized in that, Includes the following steps: 1) Wash the silicon wafer that serves as the gate; 2) Prepare a blend solution of the DASA and the polymer in the organic solvent; 3) Spin-coating the blended solution onto the silicon wafer, annealing and curing to obtain a silicon wafer coated with a dielectric layer; 4) The organic semiconductor material is vapor-deposited onto the silicon wafer coated with the dielectric layer to obtain a silicon DASA / polymer-organic semiconductor device; 5) Connect the source electrode and drain electrode to the surface of the organic semiconductor side of the device, respectively.

9. Use of the multi-stimulus responsive material DASA in the fabrication of neuromorphic transistor memories, the neuromorphic transistor memories comprising neuromorphic transistor memories according to any one of claims 1-3 or neuromorphic transistor memories fabricated by any one of claims 4-8.

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