Semiconductor structure and method of manufacturing the same

Abstract

The application provides a semiconductor structure and a preparation method thereof. The semiconductor structure comprises a substrate, an epitaxial layer and an epitaxial structure which are sequentially arranged on the substrate; the epitaxial layer is doped with a doping element, and in the forming process, a sacrificial layer is formed on the epitaxial layer and repeatedly etched to make the concentration of the doping element in the epitaxial layer lower than a preset value. The preparation method is used for preparing the semiconductor structure. The application forms a sacrificial layer on the epitaxial layer and repeatedly etches the sacrificial layer to make the concentration of the doping element in the epitaxial layer lower than a preset value, thereby preventing the doping element in the epitaxial layer from being separated upward into the upper structure, ensuring the mobility of the channel layer electron, and improving the performance of the device.

Description

Technical Field

[0001] This application relates to the field of semiconductors, and more particularly to a semiconductor structure and its fabrication method. Background Technology

[0002] In semiconductor device fabrication, when using GaN power electronics and radio frequency materials, it is common practice to introduce dopants such as iron and magnesium to increase the resistivity of the epitaxial layer and reduce leakage current. However, iron and magnesium exhibit a so-called memory effect, meaning that iron and magnesium dopants in the epitaxial layer can precipitate upwards into the upper epitaxial structure. This results in a large amount of iron and magnesium dopants in the upper structure, which does not require doping. This reduces the electron mobility of the upper epitaxial structure, thereby degrading device performance.

[0003] Therefore, how to prevent dopants in the epitaxial layer from precipitating upwards and entering the upper structure is a problem that urgently needs to be solved. Summary of the Invention

[0004] This application provides a semiconductor structure and its fabrication method, which can prevent doping elements in the first epitaxial structure from depositing upwards into the upper epitaxial structure, ensuring the electron mobility of the upper epitaxial structure, and improving the performance of the device.

[0005] To achieve the above objectives, an embodiment of this application provides a method for fabricating a semiconductor structure, the method comprising the following steps:

[0006] S1: A first epitaxial structure is formed on a substrate, wherein the first epitaxial structure is doped with a doping element;

[0007] S2: A sacrificial layer is formed on the first epitaxial structure;

[0008] S3: Etch the sacrificial layer;

[0009] S4: Continue to grow a second epitaxial structure on the first epitaxial structure after etching the sacrificial layer;

[0010] Before proceeding to step S4, steps S2 and S3 are repeated N times until the concentration of doped elements in the first epitaxial structure is lower than a preset value.

[0011] Optionally, the first epitaxial structure is a buffer layer, and the doping element is located in the buffer layer; the second epitaxial structure includes at least a channel layer and a barrier layer stacked sequentially.

[0012] Optionally, the first epitaxial structure includes a buffer layer, a first N-type semiconductor layer, a second N-type semiconductor layer, and a P-type semiconductor layer stacked sequentially, wherein the doping element is located in the P-type semiconductor layer; the second epitaxial structure includes at least a third N-type semiconductor layer.

[0013] Optionally, the first epitaxial structure includes at least a buffer layer and a first P-type semiconductor layer stacked sequentially, wherein the doping element is located in the P-type semiconductor layer; the second epitaxial structure includes at least an N-type semiconductor layer and a second P-type semiconductor layer stacked sequentially.

[0014] Optionally, the first N-type semiconductor layer is an N-type heavily doped GaN layer; the second N-type semiconductor layer is an N-type lightly doped GaN layer; and the third N-type semiconductor layer is an N-type heavily doped GaN layer.

[0015] Optionally, the first P-type semiconductor layer is a P-type GaN layer; the N-type semiconductor layer is an N-type GaN layer; and the second P-type semiconductor layer is a P-type GaN layer.

[0016] Optionally, the material of the sacrificial layer includes one or more combinations of InN, InGaN, InAlN, InAlGaN, and GaN.

[0017] Optionally, the thickness of the sacrificial layer can be 1 nm–1 μm.

[0018] Optionally, a protective layer is formed between the first epitaxial structure and the sacrificial layer.

[0019] Optionally, the material of the protective layer includes one or more combinations of AlN, AlInGaN, and AlGaN.

[0020] Optionally, the doping element in the first epitaxial structure is iron or magnesium.

[0021] Optionally, the preset value is 2×10 18 atoms / cm 3 Below the order of magnitude.

[0022] Optionally, steps S1, S2, S3, and S4 can be performed sequentially within the same reaction chamber.

[0023] Optionally, in step S3, the temperature inside the reaction chamber is higher than 400 degrees Celsius, and the sacrificial layer is etched using gas.

[0024] Optionally, the gas is one or a combination of hydrogen, ammonia, hydrogen chloride, and chlorine.

[0025] Optionally, in step S3, the sacrificial layer is completely or partially etched.

[0026] Optionally, the substrate is Si, SiC, GaN, AlN, or sapphire.

[0027] In the semiconductor structure and its fabrication method described in the above embodiments, a sacrificial layer is formed on the first epitaxial structure and then etched to reduce the concentration of doped elements in the first epitaxial structure to a preset value. This prevents doped elements in the first epitaxial structure from precipitating upwards into the upper epitaxial structure, ensuring the electron mobility of the upper epitaxial structure and improving the device performance.

[0028] Specifically, by forming a sacrificial layer on the first epitaxial structure, iron and magnesium dopants in the first epitaxial structure can precipitate and accumulate on the surface of the sacrificial layer in contact with the first epitaxial structure and within the sacrificial layer. Then, by etching the sacrificial layer, the upward precipitation of iron and magnesium dopants into the upper epitaxial structure is reduced or removed. Although dopants will also accumulate on the surface of the first epitaxial structure due to surface energy, directly etching the first epitaxial structure will introduce defects. Furthermore, the material of the first epitaxial structure is relatively difficult to etch. Further, to reduce the damage to the first epitaxial structure during the etching process, this invention proposes to first grow a protective layer on the first epitaxial structure before growing the sacrificial layer. The protective layer material is one or more combinations of AlN, AlInGaN, and AlGaN. Attached Figure Description

[0029] Figure 1 This is a method for preparing a semiconductor structure provided in one embodiment of this application.

[0030] Figures 2(a)-2(f) This is a method for preparing a semiconductor structure according to Embodiment 1 of this application, and a process flow diagram of the method for preparing a semiconductor structure.

[0031] Figures 3(a)-3(f) This is a method for preparing a semiconductor structure according to Embodiment 2 of this application, and a process flow diagram of the method for preparing a semiconductor structure.

[0032] Figures 4(a)-4(f) This is a method for preparing a semiconductor structure according to Embodiment 3 of this application, and a process flow diagram of the method for preparing a semiconductor structure.

[0033] Explanation of reference numerals in the attached figures

[0034] Substrate 10

[0035] Buffer layer 20

[0036] Sacrifice layer 30

[0037] Channel layer 40

[0038] Barrier layer 50

[0039] First N-type semiconductor layer 61

[0040] Second N-type semiconductor layer 62

[0041] Third N-type semiconductor layer 63

[0042] P-type semiconductor layer 70

[0043] First P-type semiconductor layer 81

[0044] Second P-type semiconductor layer 82

[0045] N-type semiconductor layer 90 Detailed Implementation

[0046] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses consistent with some aspects of this application as detailed in the appended claims.

[0047] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. Unless otherwise defined, the technical or scientific terms used in this application should be understood in their ordinary sense by one of ordinary skill in the art to which this application pertains. The words “a” or “one” and similar terms used in this application specification and claims do not indicate a limitation of quantity, but rather indicate the presence of at least one. The words “comprising” or “including” and similar terms mean that the element or object preceding “comprising” or “including” covers the element or object listed following “comprising” or “including” and its equivalents, and do not exclude other elements or objects. The words “connected” or “linked” and similar terms are not limited to physical or mechanical connections and can include electrical connections, whether direct or indirect. “A plurality” includes two, equivalent to at least two. The singular forms “a,” “the,” and “the” used in this application specification and appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0048] Example 1

[0049] This embodiment provides a method for fabricating a semiconductor structure, such as... Figure 1 As shown, the method for fabricating the semiconductor structure includes the following steps:

[0050] Step S1: Form a first epitaxial structure on a substrate, wherein the first epitaxial structure is doped with a doping element;

[0051] Step S2: Form a sacrificial layer on the first epitaxial structure;

[0052] Step S3: Etch the sacrificial layer;

[0053] Step S4: Continue growing a second epitaxial structure on the first epitaxial structure after etching the sacrificial layer;

[0054] Before proceeding to step S4, steps S2 and S3 are repeated N times until the concentration of doped elements in the first epitaxial structure is lower than the preset value.

[0055] In this way, by forming and etching a sacrificial layer on the first epitaxial structure, the concentration of doped elements in the first epitaxial structure is reduced to below a preset value. This prevents doped elements from precipitating upwards into the upper epitaxial structure, ensuring the electron mobility of the upper epitaxial structure and improving device performance. In other words, by forming a sacrificial layer on the first epitaxial structure, iron and magnesium dopants can be concentrated on the surface where the sacrificial layer contacts the first epitaxial structure and within the sacrificial layer itself. Etching the sacrificial layer then reduces or eliminates the upward precipitation of iron and magnesium dopants into the upper epitaxial structure.

[0056] In the semiconductor structure fabrication method of this embodiment, specifically, the first epitaxial structure is a buffer layer, and the second epitaxial structure includes at least a channel layer and a barrier layer. Each step specifically includes:

[0057] Step S1: As shown in Figure 2(a), a buffer layer 20 is formed on the substrate 10. The buffer layer 20 is doped with a dopant element, wherein the dopant element in the buffer layer 20 is iron or magnesium, and the buffer layer 20 is a group III nitride epitaxial layer. The materials of the substrate 10 include Si, SiC, GaN, AlN, and sapphire.

[0058] Step S2: As shown in Figure 2(b), a sacrificial layer 30 is formed on the buffer layer 20 so that iron and magnesium dopants in the buffer layer 20 are precipitated and aggregated on the surface of the sacrificial layer 30 in contact with the buffer layer 20 and within the sacrificial layer 30. The material of the sacrificial layer 30 includes one or more combinations of InN, InGaN, InAlN, InAlGaN, and GaN, and the thickness is 1nm–1μm.

[0059] Step S3: As shown in Figure 2(c), the sacrificial layer 30 is etched to remove the iron and magnesium dopant atoms deposited in the sacrificial layer 30, thereby reducing the content of dopants enriched on the surface of the buffer layer 20. Preferably, the temperature inside the reaction chamber is higher than 400 degrees Celsius to achieve direct etching of the sacrificial layer in the reaction chamber without the aid of other tools or etching methods. The sacrificial layer 30 is etched using a gas, preferably one or a combination of hydrogen, ammonia, hydrogen chloride, and chlorine.

[0060] Step S4: Form a channel layer 40 and a barrier layer 50 on the buffer layer 20 after the etched sacrificial layer 30 is completed.

[0061] In step S1, a protective layer may also be included between the substrate 10 and the buffer layer 20, and the material of the protective layer is one or more combinations of AlN, AlInGaN, and AlGaN.

[0062] In step S3, there are two situations after the sacrificial layer 30 is etched. The first situation is shown in Figure 2(c), where part of the sacrificial layer 30 remains on the buffer layer. The second situation is shown in Figure 2(e), where the sacrificial layer 30 is completely etched away.

[0063] Correspondingly, in the first case, as shown in FIG2(d), in step S4, a channel layer 40 and a barrier layer 50 are formed on the remaining sacrificial layer 30; in the second case, as shown in FIG2(f), a channel layer 40 and a barrier layer 50 are formed directly on the buffer layer 20.

[0064] Before proceeding to step S4, the dopant element undergoes steps S2 and S3 N times until the concentration of the dopant element in the buffer layer 20 falls below the preset value. This preset value is determined based on the requirements of different device parameters, and the number of times steps S2 and S3 need to be repeated is then determined according to this preset value. Preferably, the number of times N is repeated for steps S2 and S3 is less than or equal to 100,000.

[0065] Steps S1, S2, S3, and S4 are completed sequentially within the same reaction chamber without removing the epitaxial material from the chamber. This improves preparation efficiency and product yield, and avoids the risk of surface contamination from external impurities caused by removing the epitaxial material from the reaction chamber.

[0066] In this way, by forming and etching a sacrificial layer on the buffer layer, the concentration of doped elements in the buffer layer is reduced to a preset value, thereby preventing doped elements in the buffer layer from precipitating upwards into the upper structure, ensuring the mobility of electrons in the channel layer, and improving the performance of the device.

[0067] Specifically, by forming a sacrificial layer on the buffer layer, iron and magnesium dopants can be gathered on the surface where the sacrificial layer and the buffer layer are in contact, and within the sacrificial layer. Then, by etching the sacrificial layer, the effect of reducing or removing iron and magnesium dopants from precipitating upwards into the upper structure can be achieved.

[0068] Example 2

[0069] The preparation steps of the semiconductor structure preparation method in this embodiment are basically the same as those in Embodiment 1. The difference is that the first epitaxial structure includes a buffer layer, a first N-type semiconductor layer, a second N-type semiconductor layer and a P-type semiconductor layer stacked sequentially, and the doping element is located in the P-type semiconductor layer; the second epitaxial structure includes at least a third N-type semiconductor layer.

[0070] Step S1: As shown in Figure 3(a), a first epitaxial structure is sequentially formed on the substrate. The first epitaxial structure includes a buffer layer 20, a first N-type semiconductor layer 61, a second N-type semiconductor layer 62, and a P-type semiconductor layer 70. The P-type semiconductor layer 70 is doped with a doping element, wherein the doping element in the P-type semiconductor layer 70 is iron or magnesium. The buffer layer 20 is a group III nitride epitaxial layer.

[0071] Step S2: As shown in Figure 3(b), a sacrificial layer 30 is formed on the P-type semiconductor layer 70 so that iron and magnesium dopants in the P-type semiconductor layer 70 are precipitated and aggregated on the surface of the sacrificial layer 30 in contact with the P-type semiconductor layer 70. The material of the sacrificial layer 30 includes one or more combinations of InN, InGaN, InAlN, InAlGaN, and GaN, and the thickness is 1nm–1μm.

[0072] Step S3: As shown in Figure 3(c), the sacrificial layer 30 is etched to remove the iron and magnesium dopant atoms deposited in the sacrificial layer 30, thereby reducing the content of dopants enriched on the surface of the P-type semiconductor layer 70. Preferably, the temperature inside the reaction chamber is higher than 400 degrees Celsius to achieve direct etching of the sacrificial layer in the reaction chamber without the aid of other tools or etching methods. The sacrificial layer 30 is etched using a gas, preferably one or a combination of hydrogen, ammonia, hydrogen chloride, and chlorine.

[0073] Step S4: As shown in Figure 3(d), a third N-type semiconductor layer 63 is formed on the P-type semiconductor layer 70 after the etched sacrificial layer 30 is completed.

[0074] The first N-type semiconductor layer 61 is a heavily doped N-type GaN layer; the second N-type semiconductor layer 62 is a lightly doped N-type GaN layer; the P-type semiconductor layer 70 is a P-type GaN layer; and the third N-type semiconductor layer 63 is a heavily doped N-type GaN layer.

[0075] Similar to Example 1, in step S3, there are two situations after the sacrificial layer 30 is etched. The first situation is shown in Figure 3(c), where part of the sacrificial layer 30 remains on the P-type semiconductor layer 70. The second situation is shown in Figure 3(e), where the sacrificial layer 30 is completely etched away.

[0076] Correspondingly, in the first case, as shown in FIG3(d), in step S4, a third N-type semiconductor layer 63 is formed on the remaining sacrificial layer 30; in the second case, as shown in FIG3(f), a third N-type semiconductor layer 63 is formed directly on the P-type semiconductor layer 70.

[0077] Before proceeding to step S4, steps S2 and S3 are repeated N times until the concentration of doped elements in the P-type semiconductor layer 70 is lower than the preset value. The preset value is determined based on the requirements of different device parameters, and the number of times steps S2 and S3 need to be repeated is then determined based on this preset value. Preferably, the number of times N is repeated for steps S2 and S3 is less than or equal to 100,000.

[0078] Steps S1, S2, S3, and S4 are completed sequentially within the same reaction chamber without removing the epitaxial material from the chamber. This improves preparation efficiency and product yield, and avoids the risk of surface contamination from external impurities caused by removing the epitaxial material from the reaction chamber.

[0079] In this way, by forming and etching a sacrificial layer on the P-type semiconductor layer 70, the concentration of doped elements in the P-type semiconductor layer 70 is reduced to a preset value, thereby preventing doped elements in the P-type semiconductor layer 70 from depositing upwards into the upper structure, ensuring the mobility of electrons in the channel layer, and improving the performance of the device.

[0080] Specifically, by forming a sacrificial layer on the P-type semiconductor layer 70, iron and magnesium dopants can be gathered on the surface where the sacrificial layer 30 contacts the P-type semiconductor layer 70. Then, by etching the sacrificial layer, the effect of reducing or removing iron and magnesium dopants from precipitating upwards into the upper structure can be achieved.

[0081] Example 3

[0082] The preparation steps of the semiconductor structure preparation method in this embodiment are basically the same as those in Example 1, except that...

[0083] The first epitaxial structure includes at least a buffer layer and a first P-type semiconductor layer stacked sequentially, wherein the doping element is located in the P-type semiconductor layer; the second epitaxial structure includes at least an N-type semiconductor layer and a second P-type semiconductor layer stacked sequentially.

[0084] The specifics are as follows:

[0085] Step S1: As shown in Figure 4(a), a first epitaxial structure is formed on the substrate 10. The first epitaxial structure includes a buffer layer 20 and a first P-type semiconductor layer 81. The buffer layer 20 is a group III nitride epitaxial layer. The first P-type semiconductor layer 81 is doped with a doping element, which is iron or magnesium.

[0086] Step S2: As shown in Figure 4(b), a sacrificial layer 30 is formed on the first P-type semiconductor layer 81 so that iron and magnesium dopants in the first P-type semiconductor layer 81 are precipitated and aggregated on the surface of the sacrificial layer 30 in contact with the first P-type semiconductor layer 81 and within the sacrificial layer 30. The material of the sacrificial layer 30 includes one or more combinations of InN, InGaN, InAlN, InAlGaN, and GaN, and the thickness is 1nm–1μm.

[0087] Step S3: As shown in Figure 4(c), the sacrificial layer 30 is etched to remove the iron and magnesium dopant atoms deposited in the sacrificial layer 30, thereby reducing the content of dopants enriched on the surface of the first P-type semiconductor layer 81. Preferably, the temperature inside the reaction chamber is higher than 400 degrees Celsius to achieve direct etching of the sacrificial layer in the reaction chamber without the aid of other tools or etching methods. The sacrificial layer 30 is etched using a gas, preferably one or a combination of hydrogen, ammonia, hydrogen chloride, and chlorine.

[0088] Step S4: As shown in Figure 4(d), an N-type semiconductor layer 90 and a second P-type semiconductor layer 82 are sequentially formed on the first P-type semiconductor layer 81 after the etching of the sacrificial layer 30.

[0089] The first P-type semiconductor layer 81 is a P-type GaN layer; the N-type semiconductor layer 90 is an N-type GaN layer; and the second P-type semiconductor layer 82 is a P-type GaN layer.

[0090] Similar to Example 1, in step S3, there are two situations after the sacrificial layer 30 is etched. The first situation is shown in Figure 4(c), where part of the sacrificial layer 30 remains on the first P-type semiconductor layer 81. The second situation is shown in Figure 4(e), where the sacrificial layer 30 is completely etched away.

[0091] Correspondingly, in the first case, as shown in FIG4(d), an N-type semiconductor layer 90 is formed on the remaining sacrificial layer 30 in step S4; in the second case, as shown in FIG4(f), an N-type semiconductor layer 90 is formed directly on the first P-type semiconductor layer 81.

[0092] Before proceeding to step S4, steps S2 and S3 are repeated N times until the concentration of doped elements in the first P-type semiconductor layer 81 is lower than the preset value. The preset value is determined based on the requirements of different device parameters, and the number of times steps S2 and S3 need to be repeated is then determined based on this preset value. Preferably, the number of times N is repeated for steps S2 and S3 is less than or equal to 100,000.

[0093] Steps S1, S2, S3, and S4 are completed sequentially within the same reaction chamber without removing the epitaxial material from the chamber. This improves preparation efficiency and product yield, and avoids the risk of surface contamination from external impurities caused by removing the epitaxial material from the reaction chamber.

[0094] In this way, by forming and etching a sacrificial layer on the first P-type semiconductor layer 81, the concentration of doped elements in the first P-type semiconductor layer 81 is lower than a preset value, thereby preventing doped elements in the first P-type semiconductor layer 81 from depositing upwards into the upper structure, ensuring the mobility of channel layer electrons, and improving the performance of the device.

[0095] Specifically, by forming a sacrificial layer on the first P-type semiconductor layer 81, iron and magnesium dopant atoms can be gathered on the surface where the sacrificial layer 30 contacts the first P-type semiconductor layer 81. Then, by etching the sacrificial layer, the upward precipitation of iron and magnesium dopant atoms into the upper structure is reduced or removed. The above description is merely a preferred embodiment of this application and is not intended to limit the application. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A method of fabricating a semiconductor structure, characterized by, The method comprises: S1: forming a first epitaxial structure on a substrate, the first epitaxial structure being doped with a doping element; S2: forming a sacrificial layer on the first epitaxial structure, wherein the material of the sacrificial layer comprises one or more combinations of InN, InGaN, InAlN, InAlGaN, and GaN; S3: etching the sacrificial layer; S4: continuing to grow a second epitaxial structure on the first epitaxial structure after the etching of the sacrificial layer is completed; wherein, before entering step S4, steps S2 and S3 are repeated N times until the concentration of the doping element in the first epitaxial structure is lower than a preset value.

2. The method of producing a semiconductor structure according to claim 1, wherein The first epitaxial structure is a buffer layer, and the doping element is located in the buffer layer; the second epitaxial structure at least comprises a channel layer and a barrier layer which are sequentially stacked.

3. The method of producing a semiconductor structure according to claim 1, wherein The first epitaxial structure comprises a buffer layer, a first N-type semiconductor layer, a second N-type semiconductor layer, and a P-type semiconductor layer which are sequentially stacked, and the doping element is located in the P-type semiconductor layer; the second epitaxial structure at least comprises a third N-type semiconductor layer.

4. The method of producing a semiconductor structure according to claim 3, wherein The first N-type semiconductor layer is an N-type heavily doped GaN layer; the second N-type semiconductor layer is an N-type lightly doped GaN layer; and the third N-type semiconductor layer is an N-type heavily doped GaN layer.

5. The method of producing a semiconductor structure according to claim 1, wherein The first epitaxial structure at least comprises a buffer layer and a first P-type semiconductor layer which are sequentially stacked, and the doping element is located in the P-type semiconductor layer; the second epitaxial structure at least comprises an N-type semiconductor layer and a second P-type semiconductor layer which are sequentially stacked.

6. The method of producing a semiconductor structure according to claim 5, wherein The first P-type semiconductor layer is a P-type GaN layer; the N-type semiconductor layer is an N-type GaN layer; and the second P-type semiconductor layer is a P-type GaN layer.

7. The method of producing a semiconductor structure according to claim 1, wherein The thickness of the sacrificial layer is 1 nm-1 μm.

8. The method of producing a semiconductor structure according to claim 1, wherein The method further comprises: forming a protective layer between the first epitaxial structure and the sacrificial layer.

9. The method of producing a semiconductor structure according to claim 8, wherein The material of the protective layer comprises one or more combinations of AlN, AlInGaN, and AlGaN.

10. The method of producing a semiconductor structure according to claim 1, wherein The doping element in the first epitaxial structure is iron or magnesium; and the concentration of the doping element is constant or changes with the thickness.

11. The method of producing a semiconductor structure according to claim 1, wherein The preset value is 2 x 1018 atoms / cm 3 orders of magnitude below.

12. The method of producing a semiconductor structure according to claim 1, wherein Steps S1, S2, S3, and S4 are sequentially completed in the same reaction chamber.

13. The method of producing a semiconductor structure according to claim 1, wherein In step S3, the temperature in the reaction chamber is higher than 400 degrees Celsius, and a gas is used to etch the sacrificial layer.

14. The method of producing a semiconductor structure according to claim 13, wherein The gas is one or more combinations of hydrogen, ammonia, hydrogen chloride, and chlorine.

15. The method of producing a semiconductor structure according to claim 1, wherein In step S3, the sacrificial layer is completely etched or partially etched.

16. The method of producing a semiconductor structure according to claim 1, wherein The substrate is Si, SiC, GaN, AlN, or sapphire.

17. A semiconductor structure, characterized by The method comprises: a substrate; an epitaxial layer and an epitaxial structure which are sequentially stacked on the substrate; wherein the epitaxial layer is doped with a doping element, and in the forming process, the concentration of the doping element in the epitaxial layer is lowered than a preset value by forming a sacrificial layer on the epitaxial layer and repeatedly etching the sacrificial layer, wherein the material of the sacrificial layer comprises one or more combinations of InN, InGaN, InAlN, InAlGaN, and GaN.

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