Method for manufacturing an image display device and the image display device

Abstract

The method for manufacturing an image display device according to the embodiment includes the following steps: forming a conductive layer comprising a first portion of a single-crystal metal on a first substrate; forming a semiconductor layer comprising a light-emitting layer on the first portion; processing the semiconductor layer to form a light-emitting element having a bottom surface on the first portion and including a light-emitting surface as the opposite side of the bottom surface; forming a first insulating film covering the first substrate, the conductive layer, and the light-emitting element; forming a circuit element on the first insulating film; forming a second insulating film covering the first insulating film and the circuit element; removing a portion of the first insulating film and a portion of the second insulating film to expose the surface containing the light-emitting surface; and forming a wiring layer on the second insulating film.

Description

Technical Field

[0001] The embodiments of the present invention relate to a method for manufacturing an image display device and an image display device. Background Technology

[0002] There is a desire to achieve thin image display devices with high brightness, wide viewing angles, high contrast, and low power consumption. To meet this market demand, the development of display devices utilizing self-emissive elements is underway.

[0003] As self-emissive elements, display devices utilizing micro-LEDs, which are tiny light-emitting elements, are anticipated. A method for manufacturing such a display device using micro-LEDs has been described, which involves sequentially transferring separately formed micro-LEDs onto a driving circuit. However, with the increasing demand for high image quality such as Full HD, 4K, and 8K, the number of micro-LEDs increases. Therefore, when multiple micro-LEDs are formed separately and sequentially transferred onto a substrate containing the driving circuit, the transfer process requires a significant amount of time. Furthermore, there is a risk of poor connection between the micro-LEDs and the driving circuit, leading to a decrease in yield.

[0004] The following techniques are known: growing a semiconductor layer containing a light-emitting layer on a Si substrate, forming electrodes on the semiconductor layer, and then attaching it to a circuit board on which a driving circuit is formed (see, for example, Patent Document 1).

[0005] Existing technical documents

[0006] Patent documents

[0007] Patent Document 1: Japanese Patent Application Publication No. 2002-141492

[0008] Non-patent literature

[0009] Non-patent literature 1: H. Kim, J. Ohta, K. Ueno, A. Kobayashi, M. Morita, Y. Tokumoto & H. Fujioka, "Fabrication of full-color GaN-based light-emitting diodes onnearly lattice-matched flexible metal foil", SCIENTIFIC REPORTS, 7: 2112, 18May2017

[0010] Non-patent literature 2: JWShon, J. Ohta, K. Ueno, A. Kobayashi & H. Fujioka, "Fabrication of full-color InGaN-based light-emitting diodes on amorphous substrates bypulsed sputtering", SCIENTIFIC REPORTS, 4: 5325, 23June 2014 Summary of the Invention

[0011] The problem that the invention will solve

[0012] One embodiment of the present invention provides a method for manufacturing an image display device and an image display device that shortens the transfer process of the light-emitting element and improves the yield rate.

[0013] Methods for solving problems

[0014] A method for manufacturing an image display device according to an embodiment of the present invention includes the following steps: forming a conductive layer comprising a first portion of a single-crystal metal on a first substrate; forming a semiconductor layer comprising a light-emitting layer on the first portion; processing the semiconductor layer to form a light-emitting element having a bottom surface on the first portion and including a light-emitting surface as the opposite side of the bottom surface; forming a first insulating film covering the first substrate, the conductive layer, and the light-emitting element; forming a circuit element on the first insulating film; forming a second insulating film covering the first insulating film and the circuit element; removing a portion of the first insulating film and a portion of the second insulating film to expose the surface including the light-emitting surface; and forming a wiring layer on the second insulating film.

[0015] An image display device according to one embodiment of the present invention includes: a substrate having a first surface; a conductive layer disposed on the first surface, comprising a first portion of a single-crystal metal; a light-emitting element disposed on the first portion, having a bottom surface electrically connected to the first portion and including a light-emitting surface that is a surface opposite to the bottom surface; a first insulating film covering the side surface of the light-emitting element, the first surface, and the conductive layer; a circuit element disposed on the first insulating film; a second insulating film covering the first insulating film and the circuit element; and a wiring layer disposed on the second insulating film.

[0016] An image display device according to one embodiment of the present invention includes: a substrate having a first surface; a conductive layer disposed on the first surface, comprising a second portion of a single-crystal metal; a semiconductor layer disposed on the second portion, having a bottom surface electrically connected to the second portion, and a surface opposite to the bottom surface comprising a plurality of light-emitting surfaces; a first insulating film covering the side surface of the semiconductor layer, the first surface, and the conductive layer; a plurality of transistors disposed on the first insulating film; a second insulating film covering the first insulating film and the plurality of transistors; and a wiring layer disposed on the second insulating film.

[0017] Invention Effects

[0018] According to one embodiment of the present invention, a method for manufacturing an image display device can be realized that shortens the transfer process of the light-emitting element and improves the yield rate.

[0019] According to one embodiment of the present invention, an image display device can be realized that shortens the transfer process of the light-emitting element and improves the yield rate. Attached Figure Description

[0020] Figure 1 This is a schematic cross-sectional view illustrating a portion of the image display device according to the first embodiment.

[0021] Figure 2 This is a cross-sectional view schematically showing a portion of an image display device according to a modified example of the first embodiment.

[0022] Figure 3 This is a schematic block diagram illustrating the image display device according to the first embodiment.

[0023] Figure 4 This is a schematic top view illustrating a portion of the image display device according to the first embodiment.

[0024] Figure 5A This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the first embodiment.

[0025] Figure 5B This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the first embodiment.

[0026] Figure 5C This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the first embodiment.

[0027] Figure 6A This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the first embodiment.

[0028] Figure 6B This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the first embodiment.

[0029] Figure 7A This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the first embodiment.

[0030] Figure 7B This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the first embodiment.

[0031] Figure 8A This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to a variation of the first embodiment.

[0032] Figure 8B This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to a variation of the first embodiment.

[0033] Figure 9 This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the first embodiment.

[0034] Figure 10A This is a schematic cross-sectional view illustrating a variation of the manufacturing method of the image display device according to the first embodiment.

[0035] Figure 10B This is a schematic cross-sectional view illustrating a variation of the manufacturing method of the image display device according to the first embodiment.

[0036] Figure 10C This is a schematic cross-sectional view illustrating a variation of the manufacturing method of the image display device according to the first embodiment.

[0037] Figure 10D This is a schematic cross-sectional view illustrating a variation of the manufacturing method of the image display device according to the first embodiment.

[0038] Figure 11 This is a schematic perspective view illustrating the image display device of the first embodiment.

[0039] Figure 12 This is a schematic cross-sectional view illustrating a portion of the image display device according to the second embodiment.

[0040] Figure 13 This is a schematic block diagram illustrating the image display device according to the second embodiment.

[0041] Figure 14A This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the second embodiment.

[0042] Figure 14B This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the second embodiment.

[0043] Figure 15A This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the second embodiment.

[0044] Figure 15B This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the second embodiment.

[0045] Figure 16A This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the second embodiment.

[0046] Figure 16B This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the second embodiment.

[0047] Figure 17 This is a schematic cross-sectional view illustrating a portion of the image display device according to the third embodiment.

[0048] Figure 18A This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the third embodiment.

[0049] Figure 18B This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the third embodiment.

[0050] Figure 18C This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the third embodiment.

[0051] Figure 19A This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the third embodiment.

[0052] Figure 19B This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the third embodiment.

[0053] Figure 20A This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the third embodiment.

[0054] Figure 20B This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the third embodiment.

[0055] Figure 21 This is a schematic cross-sectional view illustrating a portion of the image display device according to the fourth embodiment.

[0056] Figure 22A This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the fourth embodiment.

[0057] Figure 22BThis is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the fourth embodiment.

[0058] Figure 23 This is a schematic cross-sectional view illustrating a portion of the image display device according to the fifth embodiment.

[0059] Figure 24A This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the fifth embodiment.

[0060] Figure 24B This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the fifth embodiment.

[0061] Figure 25 This is a schematic cross-sectional view illustrating a portion of the image display device according to the sixth embodiment.

[0062] Figure 26A This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the sixth embodiment.

[0063] Figure 26B This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the sixth embodiment.

[0064] Figure 27A This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the sixth embodiment.

[0065] Figure 27B This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the sixth embodiment.

[0066] Figure 28A This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the sixth embodiment.

[0067] Figure 28B This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the sixth embodiment.

[0068] Figure 29 This is a schematic cross-sectional view of a portion of an image display device illustrating a variation of the sixth embodiment.

[0069] Figure 30A This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to a modified example of the sixth embodiment.

[0070] Figure 30B This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to a modified example of the sixth embodiment.

[0071] Figure 30CThis is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to a modified example of the sixth embodiment.

[0072] Figure 31A This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to a modified example of the sixth embodiment.

[0073] Figure 31B This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to a modified example of the sixth embodiment.

[0074] Figure 32 This is a chart illustrating the characteristics of pixel LED elements.

[0075] Figure 33 This is a block diagram illustrating an image display device according to the seventh embodiment.

[0076] Figure 34 This is a block diagram illustrating a modified example of the seventh embodiment of an image display device. Detailed Implementation

[0077] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

[0078] Furthermore, the accompanying drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the sizes between parts, etc., do not necessarily have to be the same as in reality. In addition, even when showing the same parts, there are cases where the dimensions and ratios of each other are shown differently depending on the accompanying drawings.

[0079] In addition, in this application specification and various figures, the same reference numerals are used for elements that are the same as those described with respect to the figures that have appeared, and detailed descriptions are omitted where appropriate.

[0080] (First Implementation)

[0081] Figure 1 This is a schematic cross-sectional view illustrating a portion of the image display device of this embodiment.

[0082] Figure 1 The diagram schematically illustrates the configuration of the sub-pixels 20 of the image display device according to this embodiment. Pixels constituting an image displayed on the image display device are composed of a plurality of sub-pixels 20.

[0083] The following explanations sometimes use a three-dimensional coordinate system of XYZ. Subpixels 20 are arranged in a two-dimensional plane. This two-dimensional plane with subpixels 20 is designated as the XY plane. Subpixels 20 are arranged along the X-axis and Y-axis. Figure 1 Indicates what will be said later Figure 4The view along line AA' is presented as a cross-sectional view connecting multiple planes perpendicular to the XY plane on a single plane. The same applies to other drawings. Figure 1 Therefore, in cross-sectional views on multiple planes perpendicular to the XY plane, the X and Y axes are not shown; instead, the Z-axis, perpendicular to the XY plane, is shown. That is, in these views, the plane perpendicular to the Z-axis is designated as the XY plane. Furthermore, for convenience, the positive direction of the Z-axis is sometimes designated as "up" or "above," and the negative direction as "down" or "below," but the direction along the Z-axis is not necessarily the direction in which gravity applies. Additionally, the length along the Z-axis is sometimes referred to as height.

[0084] Sub-pixel 20 has a light-emitting surface 151S that is approximately parallel to the XY plane. The light-emitting surface 151S is a surface that mainly radiates light in the positive direction of the Z-axis, which is orthogonal to the XY plane.

[0085] like Figure 1 As shown, the sub-pixel 20 of the image display device includes a substrate 102, a conductive layer 130, a light-emitting element 150, a first interlayer insulating film 156, a transistor 103, a second interlayer insulating film 108, and a wiring layer 110.

[0086] In this embodiment, the substrate 102 on which the light-emitting element 150 is formed is a light-transmitting substrate, such as a glass substrate. The substrate 102 has a first surface 102a. The first surface 102a is a surface that is substantially parallel to the XY plane. The light-emitting element 150 is formed on the first surface 102a. The light-emitting element 150 is driven by a transistor 103 disposed with a first interlayer insulating film 156 in between. The transistor 103 is a thin film transistor (TFT) and is formed on the first interlayer insulating film 156. The process of forming circuit elements including TFTs on a large glass substrate is established for manufacturing liquid crystal panels, organic EL panels, etc., and has the advantage of being able to utilize existing complete sets of equipment.

[0087] Subpixel 20 also includes a color filter 180. The color filter (wavelength conversion component) 180 is disposed on the surface resin layer 170 through a transparent thin film adhesive layer 188. The surface resin layer 170 is disposed on the second interlayer insulating film 108 and the wiring layer 110.

[0088] The following is a detailed explanation of the composition of subpixel 20.

[0089] A conductive layer 130 is disposed on the first surface 102a. The conductive layer 130 includes a connecting plate (first part) 130a. A light-emitting element 150 is disposed on the connecting plate 130a. The connecting plate 130a is a conductive component that has a square or arbitrary polygonal, elliptical, circular, or other shapes when viewed from above in the XY plane, and is in the form of a film, layer, or plate. The connecting plate 130a is electrically connected to the light-emitting element 150 on the bottom surface 153B of the light-emitting element 150.

[0090] In this example, a connecting plate 130a is provided for each sub-pixel 20. Different connecting plates 130a may or may not be connected to each other within the conductive layer 130. In this example, the different connecting plates 130a are connected via vias 161a provided for each connecting plate 130a and wiring (first wiring) 110a to, for example, the following described... Figure 3 3. Power cord.

[0091] A portion or all of the conductive layer 130 is formed of a single-crystal metal. Preferably, the entire conductive layer 130 is formed of a single-crystal metal layer. A portion or all of the connecting plate 130a is formed of a single-crystal metal. The portion of the connecting plate 130a where the light-emitting element 150 is located is formed of a single-crystal metal, for example, a single-crystal metal layer. The single-crystal metal layer may also be a portion of the thickness direction of the surface including the bottom surface 153B to which the light-emitting element 150 is connected. When the outer periphery of the single-crystal metal layer is projected onto the single-crystal metal layer in a top view of the XY plane, it includes the outer periphery of the bottom surface 153B. That is, the outer periphery of the bottom surface 153B is disposed within the outer periphery of the single-crystal metal. The area of ​​the single-crystal metal layer is larger than the area of ​​the bottom surface 153B. Hereinafter, including other embodiments, the conductive layer 130 and the entire connecting plate 130a are formed of a single-crystal metal layer.

[0092] The metallic materials used to form the conductive layer 130 and the connecting plate 130a are, for example, Cu or Hf. The metallic materials used for the conductive layer 130 and the connecting plate 130a are not limited to Cu or Hf, as long as they are metal materials that can be single-crystallized through an annealing process compatible with the LTPS process. Since the connecting plate 130a is formed of a metallic material, it has high conductivity and can be electrically connected to the light-emitting element 150 with low resistance.

[0093] The light-emitting element 150 includes a bottom surface 153B and a light-emitting surface 151S. The light-emitting element 150 is a prism-shaped or cylindrical element having a bottom surface 153B on a connecting plate 130a. The bottom surface 153B is disposed on the connecting plate 130a and electrically connected to the connecting plate 130a. The light-emitting surface 151S is the surface opposite to the bottom surface 153B of the light-emitting element 150.

[0094] Preferably, the outer periphery of the connecting plate 130a is configured such that when the XY plane is viewed from above and the light-emitting element 150 is projected, it includes the outer periphery of the light-emitting element 150. That is, when the XY plane is viewed from above, the outer periphery of the light-emitting element 150 is disposed within the outer periphery of the connecting plate 130a. The conductive layer 130 and the connecting plate 130a are formed of a metal material or the like described above, and have light reflectivity. Therefore, the connecting plate 130a reflects scattered light downwards from the light-emitting element 150 toward the light-emitting surface 151S, substantially improving the luminous efficiency of the light-emitting element 150.

[0095] More preferably, the outer periphery of the connecting plate 130a is configured such that, when viewed from above in the XY plane, the outer periphery of the transistor 103 is not included when the transistor 103 is projected onto the plane containing the connecting plate 130a. That is, when viewed from above in the XY plane, the outer periphery of the connecting plate 130a is positioned further outward than the outer periphery of the transistor 103. Therefore, the transistor 103 is less likely to receive reflected light from the connecting plate 130a, significantly reducing the probability of malfunction. The outer periphery of the transistor 103 when viewed from above in the XY plane refers to the outer periphery of the TFT channel 104 when viewed from above in the XY plane; this also applies to the embodiments and variations described later.

[0096] The light-emitting element 150 includes a p-type semiconductor layer (first semiconductor layer) 153, a light-emitting layer 152, and an n-type semiconductor layer (second semiconductor layer) 151. The p-type semiconductor layer 153, the light-emitting layer 152, and the n-type semiconductor layer 151 are stacked sequentially from the bottom surface 153B toward the light-emitting surface 151S. Therefore, the p-type semiconductor layer 153 is electrically connected to the connecting plate 130a.

[0097] When the light-emitting element 150 is prismatic, its shape when viewed from above in the XY plane is, for example, approximately square or rectangular. When the shape of the light-emitting element 150 when viewed from above in the XY plane is a polygon containing a square, the corners may be rounded. When the shape of the light-emitting element 150 when viewed from above in the XY plane is cylindrical, its shape is not limited to a circle; for example, it may be elliptical. By appropriately selecting the shape and arrangement of the light-emitting elements when viewed from above in the XY plane, the flexibility of layout is increased.

[0098] The light-emitting element 150 preferably uses, for example, an element containing In. X Al Y Ga 1-X-YGallium nitride (GaN) compound semiconductors with light-emitting layers such as N (0≤X, 0≤Y, X+Y<1). Hereinafter, the aforementioned gallium nitride compound semiconductors are sometimes simply referred to as gallium nitride (GaN). In one embodiment of the present invention, the light-emitting element 150 is a so-called light-emitting diode (LED). The wavelength of the light emitted by the light-emitting element 150 is, for example, approximately 467 nm ± 30 nm. The wavelength of the light emitted by the light-emitting element 150 can also be approximately 410 nm ± 30 nm, which is blue-violet light. The wavelength of the light emitted by the light-emitting element 150 is not limited to the above values ​​and can be any suitable wavelength.

[0099] The area of ​​the light-emitting layer 152 when viewed from above the XY plane is set according to the emission color of the red, green, and blue sub-pixels. Hereinafter, the area when viewed from above the XY plane will sometimes be referred to simply as the area. The area of ​​the light-emitting layer 152 is appropriately set according to factors such as visibility and the conversion efficiency of the color conversion unit 182 of the color filter 180. That is, the area of ​​the light-emitting layer 152 of each emission color sub-pixel 20 is sometimes the same, and sometimes it is different according to the emission color. In addition, the area of ​​the light-emitting layer 152 is the area of ​​the region surrounded by the outer periphery of the light-emitting layer 152 projected onto the XY plane.

[0100] A first interlayer insulating film (first insulating film) 156 covers the first surface 102a and the conductive layer 130. The first interlayer insulating film 156 covers the side surface of the light-emitting element 150. The first interlayer insulating film 156 does not cover the light-emitting surface 151S. The first interlayer insulating film 156 insulates the light-emitting elements 150 from each other. The first interlayer insulating film 156 insulates the light-emitting element 150 from circuit elements such as the transistor 103. The first interlayer insulating film 156 provides a flat surface for forming a circuit 101 containing circuit elements such as the transistor 103. By covering the light-emitting element 150, the first interlayer insulating film 156 protects the light-emitting element 150 from the effects of thermal stress, etc., during the formation of the transistor 103, etc.

[0101] The first interlayer insulating film 156 is formed of organic or inorganic insulating material. The insulating material used for the first interlayer insulating film 156 is preferably white resin. White resin reflects the reflected light from the transverse emitted light of the light-emitting element 150, the interface of the color filter 180, etc., so making the first interlayer insulating film 156 white resin helps to substantially improve the luminous efficiency of the light-emitting element 150.

[0102] White resin is formed by dispersing scattering fine particles exhibiting Mie scattering effect in transparent resins such as silicone resins (SOG, Spin On Glass) and phenolic varnish-type phenolic resins. The scattering fine particles are colorless or white and have a diameter approximately 1 / 10 to several times the wavelength of the light emitted by the light-emitting element 150. Preferably, the scattering fine particles have a diameter approximately 1 / 2 the wavelength of the light. Examples of such scattering fine particles include TiO2, Al2O3, and ZnO.

[0103] White resin can also be formed by flexibly using multiple tiny pores dispersed within transparent resin. When whitening the first interlayer insulating film 156, it can also be used in conjunction with SOG, for example, a SiO2 film formed by ALD (Atomic-Layer-Deposition) or CVD (Chemical Vapor Deposition).

[0104] The first interlayer insulating film 156 can also be made of black resin. By making the first interlayer insulating film 156 black resin, light scattering within the sub-pixel 20 can be suppressed, and stray light can be suppressed more effectively. Image display devices that suppress stray light can display clearer images.

[0105] A TFT lower layer film 106 is formed on the first interlayer insulating film 156. The TFT lower layer film 106 is provided for purposes such as ensuring flatness during the formation of the transistor 103 and protecting the TFT channel 104 of the transistor 103 from contamination during heat treatment. The TFT lower layer film 106 is, for example, a stacked film of SiO2 and SiN.

[0106] Transistor 103 is formed on the lower TFT film 106. Besides transistor 103, other transistors, capacitors, and other circuit elements are formed on the lower TFT film 106, and circuit 101 is constructed using wiring and other methods. For example, transistor 103 and the components described later... Figure 3 The driving transistor 26 corresponds to this. In addition, in Figure 3 In the circuit, transistor 24, capacitor 28, etc. are selected as circuit elements. Circuit 101 includes TFT channel 104, insulating layer 105, second interlayer insulating film 108, vias 111s and 111d, and wiring layer 110.

[0107] In this example, transistor 103 is an n-channel thin-film transistor (TFT). Transistor 103 includes a TFT channel 104 and a gate 107. The TFT channel 104 is preferably formed using a low-temperature polycrystalline silicon (LTPS) process. In the LTPS process, the TFT channel 104 is formed by polycrystallineizing and activating a region of amorphous Si formed on the lower TFT film 106. For example, laser annealing is used for the polycrystallineizing and activation of the amorphous Si region. TFTs formed by the LTPS process have sufficiently high mobility.

[0108] The TFT channel 104 includes regions 104s, 104i, and 104d. Regions 104s, 104i, and 104d are all disposed on the lower TFT film 106. Region 104i is disposed between regions 104s and 104d. Regions 104s and 104d are doped with impurities such as phosphorus (P) through ion implantation to form n-type semiconductor regions, and are ohmically connected to vias 111s and 111d.

[0109] The gate 107 is disposed on the TFT channel 104 via an insulating layer 105. The insulating layer 105 is provided to insulate the TFT channel 104 from the gate 107 and from other adjacent circuit elements. If a potential higher than that of region 104s is applied to the gate 107, the current flowing through regions 104s and 104d can be controlled by forming a channel in region 104i.

[0110] The insulating layer 105 is, for example, SiO2. The insulating layer 105 may also be a multilayer insulating layer containing SiO2, Si3N4, etc., depending on the area it covers.

[0111] The gate 107 can be formed, for example, from polycrystalline Si or from high-melting-point metals such as W or Mo. The polycrystalline Si film of the gate 107 is formed, for example, by CVD or the like.

[0112] A second interlayer insulating film (second insulating film) 108 is disposed on the gate 107 and the insulating layer 105. The second interlayer insulating film 108 is formed, for example, of the same material as the first interlayer insulating film 156. That is, the second interlayer insulating film 108 is formed of an inorganic film such as white resin or SiO2. The second interlayer insulating film 108 also functions as a planarization film for forming the wiring layer 110.

[0113] The first interlayer insulating film 156, the lower TFT film 106, the insulating layer 105, and the second interlayer insulating film 108 are configured as described above, and therefore are not located on the upper part of the light-emitting surface 151S. That is, the opening 158 is formed by removing a portion of each of the first interlayer insulating film 156, the lower TFT film 106, the insulating layer 105, and the second interlayer insulating film 108. The light-emitting surface 151S is exposed through the opening 158. As will be described later, the opening 158 is filled with the surface resin layer 170.

[0114] Through-holes 111s and 111d are provided to penetrate the second interlayer insulating film 108 and the insulating layer 105. A wiring layer 110 is formed on the second interlayer insulating film 108. The wiring layer 110 includes multiple wirings with different potentials. In this example, the wiring layer 110 includes wirings 110s, 110d, and 110a.

[0115] A portion of wiring 110s is positioned above region 104s. Wiring 110s is connected, for example, to the area described later. Figure 3 The grounding wire 4 is shown. A portion of wiring 110d is located above region 104d. Another portion of wiring 110d is located near the light-emitting surface 151S, but is not directly connected to the light-emitting surface 151S. Wiring 110d is electrically connected to the light-emitting surface 151S via the light-transmitting electrode 159d, as described later. A portion of wiring 110a is located above the connecting plate 130a. Wiring 110a is connected, for example, to the connection plate 130a described later. Figure 3 The power cord shown is 3.

[0116] exist Figure 1 In subsequent cross-sectional views of wiring layers, unless otherwise specified, the reference numerals for the wiring layers will be displayed in the lateral position of a wiring layer contained in the wiring layer for which reference numerals should be attached.

[0117] A light-transmitting electrode 159d is disposed throughout the wiring 110d. A light-transmitting electrode 159d is disposed throughout the light-emitting surface 151S. The light-transmitting electrode 159d is also disposed between the wiring 110d and the light-emitting surface 151S, electrically connecting the wiring 110d and the light-emitting surface 151S.

[0118] A light-transmitting electrode 159s is disposed along the wiring 110s. The light-transmitting electrode 159s and the wiring 110s are connected together, for example, to... Figure 3 The circuit grounding wire 4. A light-transmitting electrode 159a is provided throughout the wiring 110a. The light-transmitting electrode 159a is connected together with the wiring 110a, for example, to... Figure 3 The power supply line 3 of the circuit. The light-transmitting electrodes 159d, 159s, and 159a are formed of a light-transmitting conductive film. ITO film, ZnO film, etc. are preferably used in the light-transmitting electrodes 159d, 159s, and 159a.

[0119] As in this example, the light-emitting surface 151S is preferably roughened. When the light-emitting surface 151S is roughened, the light extraction efficiency of the light-emitting element 150 can be improved.

[0120] By providing a transparent electrode 159d on the light-emitting surface 151S, the connection area between the transparent electrode 159d and the n-type semiconductor layer 151 can be increased, thereby substantially increasing the area of ​​the light-emitting surface 151S and reducing the connection resistance. Furthermore, since the entire surface exposed through the opening 158 can be used as the light-emitting surface 151S, the area of ​​the light-emitting surface 151S can be substantially increased, improving luminous efficiency. Because the light-emitting surface 151S is made into a rough surface, the contact resistance is reduced by increasing the connection area between the light-emitting surface 151S and the transparent electrode 159d, further improving luminous efficiency.

[0121] Through-hole 111s is disposed between wiring 110s and area 104s, electrically connecting wiring 110s and area 104s. Through-hole 111d is disposed between wiring 110d and area 104d, electrically connecting wiring 110d and area 104d.

[0122] Wiring 110s and transparent electrode 159s are connected to region 104s via via 111s. Region 104s is the source region of transistor 103. Therefore, the source region of transistor 103 is electrically connected to ground wire 4 via via 111s, wiring 110s, and transparent electrode 159s.

[0123] Wiring 110d and transparent electrode 159d are connected to region 104d via via 111d. Region 104d is the drain region of transistor 103. Therefore, the drain region of transistor 103 is electrically connected to n-type semiconductor layer 151 via via 111d, wiring (second wiring) 110d, and transparent electrode 159d.

[0124] Through-hole 161a is provided, penetrating the second interlayer insulating film 108, the insulating layer 105, the TFT lower layer film 106, and the first interlayer insulating film 156. Through-hole 161a is located between wiring 110a and connecting plate 130a, electrically connecting wiring 110a and connecting plate 130a. Therefore, the p-type semiconductor layer 153 is electrically connected, for example, to the connecting plate 130a, through-hole 161a, wiring 110a, and light-transmitting electrode 159a. Figure 3 3. Power supply line of the circuit.

[0125] The wiring layer 110 and the vias 111s, 111d, and 161a are formed, for example, of Al, Cu, or alloys thereof. They may also be formed of a laminated film of Al and Ti, etc. For example, in an Al and Ti laminated film, Al is laminated on a Ti film, and Ti is laminated on Al.

[0126] A surface resin layer 170 covers the second interlayer insulating film 108, the wiring layer 110, and the light-transmitting electrodes 159s, 159d, and 159a. The surface resin layer 170 also fills the opening 158. The surface resin layer 170 is disposed on the light-emitting surface 151S via the light-transmitting electrode 159d. The surface resin layer 170, filling the opening 158, is disposed on the light-transmitting electrode 159d, which is arranged to cover the sides of the first interlayer insulating film 156, the TFT lower layer film 106, the insulating layer 105, and the second interlayer insulating film 108. The surface resin layer 170 is a transparent resin, providing protection for the second interlayer insulating film 108, the wiring layer 110, and the light-transmitting electrodes 159a, 159d, and 159s, and serving to bond the planarization surface of the color filter 180.

[0127] The color filter 180 includes a light-blocking section 181 and a color conversion section 182. The color conversion section 182 is positioned directly above the light-emitting surface 151S of the light-emitting element 150, according to the shape of the light-emitting surface 151S. In the color filter 180, the portion other than the color conversion section 182 is designated as the light-blocking section 181. The light-blocking section 181 is a so-called black matrix, which can reduce color bleeding caused by color mixing and other factors from the adjacent color conversion section 182, thereby enabling the display of a clear image.

[0128] The color conversion unit 182 is set to one layer or two layers or more. Figure 1 The diagram shows a case where the color conversion unit 182 has two layers. Whether the color conversion unit 182 has one or two layers is determined by the color, i.e., the wavelength, of the light emitted by the sub-pixel 20. When the emitted color of the sub-pixel 20 is red, it is preferable that the color conversion unit 182 consists of two layers: a color conversion layer 183 and a filter layer 184 that allows red light to pass through. When the emitted color of the sub-pixel 20 is green, it is preferable that the color conversion unit 182 consists of two layers: a color conversion layer 183 and a filter layer 184 that allows green light to pass through. When the emitted color of the sub-pixel 20 is blue, it is preferable to have only one layer.

[0129] When the color conversion unit 182 has two layers, the first layer is the color conversion layer 183, and the second layer is the filter layer 184. The first color conversion layer 183 is located closer to the light-emitting element 150. The filter layer 184 is stacked on top of the color conversion layer 183.

[0130] The color conversion layer 183 converts the wavelength of light emitted by the light-emitting element 150 to a desired wavelength. When emitting red sub-pixels 20, light with a wavelength of 467nm ± 30nm (the wavelength of the light-emitting element 150) is converted, for example, to light with a wavelength of approximately 630nm ± 20nm. When emitting green sub-pixels 20, light with a wavelength of 467nm ± 30nm (the wavelength of the light-emitting element 150) is converted, for example, to light with a wavelength of approximately 532nm ± 20nm.

[0131] The filter layer 184 blocks the wavelength components of blue light that remain after the color conversion layer 183 has not been converted.

[0132] When the light emitted by sub-pixel 20 is blue, the light-emitting element 150 can output light via the color conversion layer 183 or output light as is without the color conversion layer 183. When the wavelength of the light emitted by the light-emitting element 150 is approximately 467nm ± 30nm, light can also be output without the color conversion layer 183. When the wavelength of the light emitted by the light-emitting element 150 is set to 410nm ± 30nm, it is preferable to provide one color conversion layer 183 in order to convert the wavelength of the output light to approximately 467nm ± 30nm.

[0133] Even in the case of the blue sub-pixel 20, the sub-pixel 20 can have a filter layer 184. By providing a filter layer 184 that allows blue light to pass through in the blue sub-pixel 20, minute external light reflections other than the blue light generated on the surface of the light-emitting element 150 can be suppressed.

[0134] Figure 2 This is a cross-sectional view schematically showing a portion of an image display device according to a modified example of this embodiment.

[0135] exist Figure 2 In this case, the connection method between the light-emitting element 150a of sub-pixel 20a and the wiring 110d1 differs from that in the first embodiment described above. In this modified example, the absence of light-transmitting electrodes on the wirings 110s, 110d1, and 110a also differs from the first embodiment. Otherwise, this modified example is the same as the first embodiment, with the same reference numerals used for the same constituent elements and detailed descriptions appropriately omitted. Furthermore, in Figure 2 The diagram also shows the structure from the surface resin layer 170 to the upper portion. These upper portion structures are also the same as in the first embodiment.

[0136] like Figure 2As shown, sub-pixel 20a includes a light-emitting element 150a and wiring 110d1. A portion of wiring 110d1 is disposed above region 104d. Another portion of wiring 110d1 extends to the light-emitting surface 151S, with its front end connected to the surface containing the light-emitting surface 151S. The surface containing the light-emitting surface 151S is a surface coplanar with the light-emitting surface 151S. The front end of wiring 110d1 is connected to a surface other than the light-emitting surface 151S on this surface. In this example, the light-emitting surface 151S is not roughened, but it can also be roughened. If it is not roughened, the roughening process can be omitted.

[0137] In this embodiment, one of the sub-pixels 20 and 20a described above may be included. In other embodiments and variations thereof described later, an example is shown where the surface containing the light-emitting surface is electrically connected via a light-transmitting electrode. This is not a limitation; the surface containing the light-emitting surface may also be directly connected to a portion of the wiring without via a light-transmitting electrode.

[0138] Figure 3 This is a schematic block diagram illustrating the image display device of this embodiment.

[0139] like Figure 3 As shown, the image display device 1 of this embodiment includes a display area 2. Subpixels 20 are arranged in the display area 2. The subpixels 20 are arranged in a grid pattern, for example. For example, n subpixels 20 are arranged along the X-axis and m subpixels are arranged along the Y-axis.

[0140] Pixel 10 contains multiple sub-pixels 20 that emit light of different colors. Sub-pixel 20R emits red light. Sub-pixel 20G emits green light. Sub-pixel 20B emits blue light. The three sub-pixels 20R, 20G, and 20B emit light at the desired brightness, thus determining the emission color and brightness of a pixel 10.

[0141] A pixel 10 contains three subpixels: 20R, 20G, and 20B. For example, subpixels 20R, 20G, and 20B... Figure 3 As shown, they are arranged in a straight line along the X-axis. Each pixel 10 can also arrange subpixels of the same color into the same column, or, as in this example, arrange subpixels of different colors in each column.

[0142] The image display device 1 also includes a power line 3 and a ground line 4. The power line 3 and the ground line 4 are arranged in a grid pattern along the sub-pixels 20. The power line 3 and the ground line 4 are electrically connected to each sub-pixel 20, supplying power to each sub-pixel 20 from a DC power supply connected between the power terminal 3a and the GND terminal 4a. The power terminal 3a and the GND terminal 4a are respectively located at the ends of the power line 3 and the ground line 4, and are connected to a DC power supply circuit located outside the display area 2. The power terminal 3a is supplied with a positive voltage with reference to the GND terminal 4a.

[0143] The image display device 1 also includes scan lines 6 and signal lines 8. The scan lines 6 are routed in a direction parallel to the X-axis. That is, the scan lines 6 are routed along the row direction of the sub-pixels 20. The signal lines 8 are routed in a direction parallel to the Y-axis. That is, the signal lines 8 are routed along the column direction of the sub-pixels 20.

[0144] The image display device 1 also includes a row selection circuit 5 and a signal voltage output circuit 7. The row selection circuit 5 and the signal voltage output circuit 7 are disposed along the outer edge of the display area 2. The row selection circuit 5 is disposed along the Y-axis direction of the outer edge of the display area 2. The row selection circuit 5 is electrically connected to the sub-pixels 20 of each column via scan lines 6 and supplies selection signals to each sub-pixel 20.

[0145] The signal voltage output circuit 7 is arranged along the X-axis direction of the outer edge of the display area 2. The signal voltage output circuit 7 is electrically connected to the sub-pixels 20 of each row via signal lines 8, and supplies signal voltage to each sub-pixel 20.

[0146] Subpixel 20 includes a light-emitting element 22, a selection transistor 24, a driving transistor 26, and a capacitor 28. Figure 3 And the following Figure 4 In the text, sometimes the select transistor 24 is shown as T1, the drive transistor 26 is shown as T2, and the capacitor 28 is shown as Cm.

[0147] The light-emitting element 22 and the driving transistor 26 are connected in series. In this embodiment, the driving transistor 26 is an n-channel TFT, and the cathode electrode of the light-emitting element 22 is connected to the drain electrode of the driving transistor 26. The main electrodes of the driving transistor 26 and the select transistor 24 are the drain electrode and the source electrode, respectively. The anode electrode of the light-emitting element 22 is connected to a p-type semiconductor layer. The cathode electrode of the light-emitting element is connected to an n-type semiconductor layer. The series circuit of the light-emitting element 22 and the driving transistor 26 is connected between the power supply line 3 and the ground line 4. The driving transistor 26 and... Figure 1 The transistor 103 corresponds to the light-emitting element 22 and Figure 1The light-emitting element 150 corresponds to this. The current flowing through the light-emitting element 22 is determined by the voltage applied between the gate and source of the driving transistor 26, and the light-emitting element 22 emits light with a brightness corresponding to the current flowing through it.

[0148] Select transistor 24 is connected via its main electrode between the gate electrode of drive transistor 26 and signal line 8. The gate electrode of select transistor 24 is connected to scan line 6. A capacitor 28 is connected between the gate electrode of drive transistor 26 and power line 3.

[0149] The row selection circuit 5 selects one row from the arrangement of m rows of sub-pixels 20 and supplies a selection signal to the scan line 6. The signal voltage output circuit 7 supplies a signal voltage with the required analog voltage value to each sub-pixel 20 of the selected row. The signal voltage is applied between the gate and source of the driving transistor 26 of the selected row's sub-pixel 20. The signal voltage is held by the capacitor 28. The driving transistor 26 causes a current corresponding to the signal voltage to flow through the light-emitting element 22. The light-emitting element 22 emits light with a brightness corresponding to the flowing current.

[0150] The row selection circuit 5 sequentially switches the selected row to supply a selection signal. That is, the row selection circuit 5 scans the rows arranged with sub-pixels 20. A current corresponding to the signal voltage flows through the light-emitting element 22 of the sequentially scanned sub-pixels 20 to emit light. Each pixel 10 emits light with a color and brightness determined by the light emitted by the sub-pixels 20 of each of the RGB colors, and displays an image in the display area 2.

[0151] Figure 4 This is a schematic top view illustrating a portion of the image display device of this embodiment.

[0152] In this embodiment, as in Figure 1 As explained, the light-emitting element 150 and the driving transistor 103 are stacked along the Z-axis direction, separated by a first interlayer insulating film 156. In other words, the light-emitting element 150 is formed on a different layer than the layer on which the transistor 103 is formed. The light-emitting element 150 is... Figure 3 The middle corresponds to the light-emitting element 22. The driving transistor 103 is in Figure 3 This corresponds to the driving transistor 26, and is also referred to as T2. To avoid complexity, in Figure 4 The display of the light-transmitting electrode is omitted.

[0153] like Figure 4 As shown, the anode electrode of the light-emitting element 150 is disposed on the connecting plate 130a and electrically connected to the connecting plate 130a. The connecting plate 130a is disposed on the transistor 103, Figure 1The wiring layer 110 shown is the lower layer. The connecting plate 130a is electrically connected to the wiring 110a via a through hole 161a. More specifically, one end of the through hole 161a is connected to the connecting plate 130a, and the other end of the through hole 161a is connected to the wiring 110a via a contact hole 161a1.

[0154] The cathode electrode of the light-emitting element 150 is made of Figure 1 The n-type semiconductor layer 151 shown is provided. Wiring 110d is... Figure 1 The light-transmitting electrode 159d is shown. The light-transmitting electrode 159d covers the light-emitting surface 151S. The light-transmitting electrode 159d is also disposed between the wiring 110d and the light-emitting surface 151S, so the cathode electrode of the light-emitting element 150 is electrically connected to the wiring 110d.

[0155] A portion of wiring 110d is connected to the drain electrode of transistor 103 via via 111d. The drain electrode of transistor 103 is Figure 1 The region 104d is shown. The source electrode of transistor 103 is connected to wiring 110s via via 111s. The source electrode of transistor 103 is Figure 1 The area 104s is shown. In this example, wiring layer 110 includes ground wire 4, and wiring 110s is connected to ground wire 4.

[0156] In this example, power line 3 is located on a layer higher than wiring layer 110. Figure 1 Although the diagram is omitted, an interlayer insulating film is provided on the wiring layer 110. The power line 3 is located on the top interlayer insulating film and is insulated from the grounding line 4.

[0157] Thus, the light-emitting element 150 can be electrically connected to the wiring 110a located on the upper layer of the light-emitting element 150 by using the through hole 161a. In addition, the light-emitting element 150 exposes the light-emitting surface 151S through the opening 158, and a light-transmitting electrode 159d is provided in the opening 158, thereby enabling it to be electrically connected to the transistor 103 located on the upper layer of the light-emitting element 150 via the wiring 110d.

[0158] The manufacturing method of the image display device 1 of this embodiment will be described.

[0159] Figures 5A to 7B This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to this embodiment.

[0160] like Figure 5AAs shown, in the manufacturing method of the image display device 1 of this embodiment, a substrate (first substrate) 102 is prepared. The substrate 102 is a light-transmitting substrate, for example, a generally rectangular glass substrate of about 1500mm × 1800mm. A conductive layer 1130 is formed on the first surface 102a. The conductive layer (metal layer) 1130 is patterned, for example, after a layer of metal material is deposited on the entire surface of the first surface 102a by sputtering or the like, so that the portion where the light-emitting layer is formed remains.

[0161] Alternatively, the conductive layer 1130 may be formed by forming a patterned conductive layer 1130 on a mask having a patterned opening at the location where the light-emitting layer is formed on the first surface 102a.

[0162] The conductive layer 1130 is formed using, for example, a metallic material such as Cu or Hf. In the formation of the conductive layer 1130, sputtering or the like is preferably used to form the film at low temperatures.

[0163] The patterned conductive layer 1130 is monocrystalline through an annealing process. Preferably, the annealing process is performed in a manner that monocrystalline crystallizes the entire patterned conductive layer 1130. To monocrystalline the conductive layer 1130, laser-based annealing is preferred, for example. In pulsed laser annealing, the conductive layer 1130 can be monocrystalline at a low temperature of approximately 400°C to 500°C, suppressing the effect of temperature on the underlying layer of the conductive layer 1130. Therefore, flexible substrates formed from glass or organic resins (described later) can be used in the substrate 102.

[0164] like Figure 5B As shown, a semiconductor layer 1150 is formed on the single-crystallized conductive layer 1130a. From the conductive layer 1130a toward the positive direction of the Z-axis, the semiconductor layer 1150 sequentially forms a p-type semiconductor layer 1153, a light-emitting layer 1152, and an n-type semiconductor layer 1151.

[0165] In the process of forming the semiconductor layer 1150, physical vapor deposition methods such as evaporation, ion beam deposition, molecular beam epitaxy (MBE), and sputtering are used, with cryogenic sputtering being the preferred method. In cryogenic sputtering, the temperature can be further reduced by using light or plasma assistance during film formation, which is therefore preferred. In MOCVD-based epitaxial growth, temperatures exceeding 1000°C are not uncommon. In contrast, it is known that in cryogenic sputtering, GaN crystals including a light-emitting layer can be epitaxially grown on a single-crystal metal layer at temperatures as low as approximately 400°C to 700°C (see Non-Patent Literature 1, 2, etc.). This cryogenic sputtering method is suitable for forming the semiconductor layer 1150 on a circuit substrate with TFTs or the like, formed in an LTPS process.

[0166] Using appropriate film-forming techniques, a GaN semiconductor layer 1150 is grown on a conductive layer 1130a that is monocrystalline over the entire surface, thereby forming a monocrystalline semiconductor layer 1150 containing a light-emitting layer 1152 on the conductive layer 1130a. Although not shown, during the growth of the semiconductor layer 1150, sometimes an amorphous deposit containing Ga or the like, which is the growth material, is deposited in areas where the conductive layer 1130a is not present.

[0167] In this embodiment, the single-crystal metal conductive layer 1130a is used as a seed crystal to promote the crystallization of GaN. When a semiconductor layer 1150 is formed on the single-crystallized conductive layer 1130a, a conductive buffer layer can also be provided on the conductive layer 1130a, and the semiconductor layer can be grown on this buffer layer using the aforementioned low-temperature sputtering method. There are no restrictions on the type of material used in the buffer layer, as long as it is a material that promotes the crystallization of GaN. Graphene sheets as described in other embodiments later can also be used.

[0168] like Figure 5C As shown, Figure 5B The semiconductor layer 1150 shown is shaped into a desired shape by etching or the like to form a light-emitting element 150. The light-emitting element 150 is formed, for example, by a dry etching process, preferably by anisotropic plasma etching (RIE). If deposits are formed at locations where the conductive layer 1130a is not present, the deposits are removed during the etching process for forming the light-emitting element 150.

[0169] After forming the light-emitting element 150, by etching Figure 5B The conductive layer 1130a shown is formed by forming a conductive layer 130. In the formation process of the conductive layer 130, a connecting plate (first portion) 130a is formed. Alternatively, the conductive layer 1130a and the semiconductor layer 1150 can be etched together to form the connecting plate 130a, after which the light-emitting element 150 is formed. Thus, the connecting plate 130a is formed on the first surface 102a, and the light-emitting element 150 is formed on the connecting plate 130a. The outer periphery of the connecting plate 130a is configured such that when the light-emitting element 150 is projected onto the XY plane from a top view, it includes the outer periphery of the light-emitting element 150. That is, when the XY plane is viewed from a top view, the outer periphery of the light-emitting element 150 is disposed within the outer periphery of the connecting plate 130a.

[0170] like Figure 6A As shown, a first interlayer insulating film (first insulating film) 156 is formed by covering the first surface 102a, the conductive layer 130 and the light-emitting element 150.

[0171] like Figure 6BAs shown, the lower TFT film 106 is formed on the first interlayer insulating film 156. The lower TFT film 106 is formed, for example, by CVD.

[0172] The TFT channel (circuit element) 104 is formed on the lower TFT film 106. For example, in the LTPS process, the TFT channel 104 is formed as follows: First, amorphous Si is deposited into the shape of the TFT channel 104. The amorphous Si is deposited, for example, by CVD. The deposited amorphous Si is polycrystalline by film laser annealing to form the TFT channel 104.

[0173] Subsequently, impurities such as phosphorus (P) are introduced into regions 104s and 104d of the source and drain electrodes of the TFT channel 104 using techniques such as ion implantation, thereby forming regions that are n-type semiconductors. The formation processes of these source and drain electrodes can also be performed after the formation process of the gate 107.

[0174] An insulating layer 105 is formed over the TFT lower film 106 and the TFT channel 104. The insulating layer 105 is formed, for example, by CVD. The gate 107 is formed on the TFT channel 104 across the insulating layer 105. In the formation of the gate 107, an appropriate formation method is used depending on the material of the gate 107. For example, if the gate 107 is polycrystalline Si, it is formed by polycrystallineizing amorphous Si through laser annealing, similar to the TFT channel 104. Alternatively, the gate 107 can also be formed by etching a high-melting-point metal film such as W or Mo formed by sputtering. In this way, a transistor (circuit element) 103 is formed.

[0175] The second interlayer insulating film 108 is configured to cover the insulating layer 105 and the gate 107. In forming the second interlayer insulating film 108, an appropriate fabrication method is applied depending on the material of the second interlayer insulating film 108. For example, when the second interlayer insulating film 108 is formed of SiO2, techniques such as ALD and CVD are used.

[0176] The flatness of the second interlayer insulating film 108 can be sufficient to form the wiring layer 110, or it may not necessarily require a planarization process. By not performing a planarization process on the second interlayer insulating film 108, the number of processes can be reduced. For example, if there are areas around the light-emitting element 150 where the thickness of the second interlayer insulating film 108 decreases, the depth of the vias penetrating the first interlayer insulating film 156 and the second interlayer insulating film 108 becomes shallower, thus ensuring a sufficient opening diameter for the vias. Therefore, it is easier to ensure electrical connections based on vias, and the decrease in yield caused by poor electrical characteristics can be suppressed.

[0177] like Figure 7AAs shown, the via 162a is formed to penetrate the second interlayer insulating film 108, the insulating layer 105, the TFT lower layer film 106, and the first interlayer insulating film 156 to reach the connecting plate 130a. The opening 158 is formed to reach the light-emitting surface 151S by removing a portion of the second interlayer insulating film 108, a portion of the insulating layer 105, a portion of the TFT lower layer film 106, and a portion of the first interlayer insulating film 156. As in this example, the light-emitting surface 151S can also be formed by etching the central portion of the surface of the n-type semiconductor layer 151 exposed by removing the first interlayer insulating film 156, etc., in the thickness direction of the n-type semiconductor layer 151. As in this example, the light-emitting surface 151S is preferably roughened.

[0178] Through-hole 112d is formed to penetrate the second interlayer insulating film 108 and the insulating layer 105 to reach region 104d. Through-hole 112s is formed to penetrate the second interlayer insulating film 108 and the insulating layer 105 to reach region 104s. Through-holes 162a, 112d, 112s, and opening 158 are formed, for example, using RIE (Relative Insulation Layer).

[0179] like Figure 7B As shown, by sending Figure 7A The through-hole 162a shown is filled with conductive material to form through-hole 161a. Through-holes 111d and 111s also pass through... Figure 7A The vias 112d and 112s shown are formed by filling them with conductive material. Then, a wiring layer 110 containing wirings 110a, 110d, and 110s is formed on the second interlayer insulating film 108. Wirings 110a, 110d, and 110s are connected to vias 161a, 111d, and 111s, respectively. The wiring layer 110 can also be formed simultaneously with the vias 161a, 111d, and 111s.

[0180] A light-transparent conductive film is formed on the wiring layer 110 and the second interlayer insulating film 108 to form light-transparent electrodes 159a, 159d, and 159s.

[0181] Then, by setting a color filter (wavelength conversion component) 180, etc., the sub-pixels 20 of the image display device 1 of this embodiment are formed.

[0182] Figure 8A as well as Figure 8B This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to a variation of this embodiment.

[0183] Figure 8A as well as Figure 8B It shows the method for forming Figure 2The process of sub-pixel 20a shown. In this example, the process involves forming the TFT channel 104, insulating layer 105, and gate 107, and forming a second interlayer insulating film 108 covering them. Figure 6B Up to the step shown, there are the same steps as described above. Hereinafter, regarding... Figure 6B Application of the process following the shown process Figure 8A as well as Figure 8B The process will be explained in detail below.

[0184] like Figure 8A As shown, vias 162a, 112d, and 112s are formed. An opening 158 is formed to reach the n-type semiconductor layer 151a. In this example, the n-type semiconductor layer 151a is not roughened, thus eliminating the need for an etching process for roughening.

[0185] like Figure 8B As shown, through holes 161a, 111d, and 111s pass through... Figure 8A The vias 162a, 112d, and 112s shown are formed by filling them with conductive material. Then, a wiring layer 110 is formed, and wirings 110a, 110d1, and 110s are formed. Here, one end of wiring 110d1 is connected to via 111d. Wiring 110d1 extends from the position connected to via 111d to the light-emitting surface 151S. The other end of wiring 110d1 is connected to the surface containing the light-emitting surface 151S. That is, the surface containing the light-emitting surface 151S is the n-type semiconductor layer 151a, and wiring 110d1 is directly connected to the n-type semiconductor layer 151a.

[0186] Then, by setting the color filter 180, etc., the sub-pixel 20a of this modified example is formed.

[0187] For example Figure 3 The circuit is a driving circuit that drives the light-emitting element 150 by selecting transistor 24, driving transistor 26, and capacitor 28. This driving circuit is formed within sub-pixels 20 and 20a. A portion of the circuitry outside the driving circuitry is formed outside the sub-pixels 20 and 20a, for example... Figure 1 The periphery of display area 2 shown. For example. Figure 3 The row selection circuit 5 shown is formed simultaneously with the driving transistor, selection transistor, etc., and is formed at the periphery of the display area 2. That is, the row selection circuit 5 can be assembled simultaneously through the above-described manufacturing process.

[0188] The signal voltage output circuit 7 is intended to be assembled into a semiconductor device manufactured through a highly integrated manufacturing process capable of micro-machining. The signal voltage output circuit 7 is mounted on another substrate along with the CPU and other circuit elements, for example, before or after the color filter is assembled, and is interconnected with the sub-pixels 20, 20a, for example, via connectors located at the periphery of the display area.

[0189] Figure 9 This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to this embodiment.

[0190] exist Figure 9 In the diagram above the arrow, the structure includes the color filter 180, and the structure below the arrow includes the light-emitting element 150 and the like formed through the above-described process. Figure 9 The process of attaching a color filter to a structure containing a light-emitting element 150 is shown by the arrow.

[0191] exist Figure 9 To avoid clutter, components other than those on the substrate 102 shown in the illustration are omitted. The omitted components are... Figure 1 The circuit 101 shown includes a TFT channel 104, a wiring layer 110, etc., and a via 161a. In conjunction with... Figure 9 as well as Figures 10A to 10D In the related description, the structure including the light-emitting element 150, the first interlayer insulating film 156, the TFT lower layer film 106, the insulating layer 105, the second interlayer insulating film 108, and the surface resin layer 170 is referred to as the light-emitting circuit section 172. The structure including the substrate 102, the conductive layer 130, the light-emitting circuit section 172, and the components omitting the display are referred to as the structure 1192. Figure 9 In the middle, the following was omitted. Figure 1 The circuit 101 shown includes the TFT channel 104, gate 107, vias 111s and 111d, and wiring layer 110.

[0192] like Figure 9 As shown, the color filter (wavelength conversion component) 180 is bonded to the structure 1192 with one side attached. The other side of the color filter 180 is bonded to the glass substrate 186. A transparent film adhesive layer 188 is provided on one side of the color filter 180, and the transparent film adhesive layer 188 is bonded to the exposed surface of the surface resin layer 170 of the structure 1192.

[0193] In this example, the color filter 180 has color conversion units arranged in the positive direction of the X-axis in the order of red, green, and blue. For red, a red color conversion layer 183R is provided in the first layer; for green, a green color conversion layer 183G is provided in the first layer; and both are provided with filter layers 184 in the second layer. For blue, a single color conversion layer 183B or a filter layer 184 can be provided. A light-blocking part 181 is provided between each color conversion unit, and the frequency characteristics of the filter layer 184 can be changed according to each color of the color conversion unit.

[0194] The positions of the color conversion layers 183R, 183G, and 183B are aligned with the position of the light-emitting element 150, and the color filter 180 is adhered to the structure 1192.

[0195] Figures 10A to 10D This is a schematic cross-sectional view illustrating a variation of the manufacturing method of the image display device according to this embodiment.

[0196] Figures 10A to 10D The image shows a method for forming color filters using inkjet printing.

[0197] like Figure 10A As shown, a structure 1192 with light-emitting elements such as light-emitting elements 150 is prepared to be formed on a substrate 102.

[0198] like Figure 10B As shown, a light-shielding portion 181 is formed on the structure 1192. The light-shielding portion 181 is formed, for example, using screen printing, photolithography, or other techniques.

[0199] like Figure 10C As shown, a phosphor corresponding to the emitted color is ejected from the inkjet nozzle to form a color conversion layer 183. The phosphor colors the areas where the light-shielding portion 181 is not formed. The phosphor uses a fluorescent coating material, such as a general phosphor material, a perovskite phosphor material, or a quantum dot phosphor material. Using perovskite phosphor materials or quantum dot phosphor materials allows for the realization of various emitted colors and provides high monochromaticity, thus improving color reproducibility; therefore, this is preferred. After drawing using the inkjet nozzle, the coating is dried at an appropriate temperature and time. The thickness of the coating film during coloring is set to be thinner than the thickness of the light-shielding portion 181.

[0200] As already explained, for blue emitting subpixels, the color conversion layer 183 is not formed if a color conversion section is not formed. Furthermore, for blue emitting subpixels, when forming a blue color conversion layer, if the color conversion section can be a single layer, it is preferable that the thickness of the blue phosphor coating is the same as the thickness of the light-shielding section 181.

[0201] like Figure 10DAs shown, the paint for the filter layer 184 is ejected from the inkjet nozzle. The paint is applied overlappingly to the phosphor coating. The combined thickness of the phosphor and the paint coating is the same as the thickness of the light-shielding portion 181.

[0202] Whether it's a thin-film color filter or an inkjet color filter, to improve color conversion efficiency, it's desirable for the color conversion layer 183 to be as thick as possible. On the other hand, if the color conversion layer 183 is too thick, the emitted light after color conversion approximates a Lambert, while the blue light that hasn't undergone color conversion is restricted in its emission angle by the light-shielding portion 181. This results in a viewing angle dependence problem in the displayed color of the image. To ensure that the light distribution of the subpixels where the color conversion layer 183 is located is consistent with the light distribution of the blue light that hasn't undergone color conversion, it's desirable that the thickness of the color conversion layer 183 is approximately half the opening size of the light-shielding portion 181.

[0203] For example, in the case of a high-resolution image display device with a resolution of around 250 ppi (pitch per inch), the spacing between subpixels 20 is approximately 30 μm, therefore the thickness of the color conversion layer 183 is expected to be around 15 μm. Here, when the color conversion material is composed of spherical phosphor particles, it is preferable to stack them in the densest possible configuration to suppress light leakage from the light-emitting element 150. Therefore, at least three layers of particles are required. Consequently, the particle diameter of the phosphor material constituting the color conversion layer 183 is preferably, for example, around 5 μm or less, and more preferably around 3 μm or less.

[0204] Figure 11 This is a schematic perspective view illustrating the image display device of this embodiment.

[0205] like Figure 11 As shown, the image display device of this embodiment has a light-emitting circuit section 172 having a plurality of sub-pixels 20 on a substrate 102. Figure 9 The conductive layer 130 shown includes a connecting plate 130a. The connecting plate 130a is disposed on the substrate 102 corresponding to each of the sub-pixels 20. A color filter 180 is provided on the light-emitting circuit section 172. Regarding other embodiments and variations described later, it also has the same characteristics as... Figure 11 The configuration shown is the same.

[0206] The effects of the image display device 1 in this embodiment will be explained.

[0207] In the manufacturing method of the image display device 1 of this embodiment, a light-emitting element 150 is formed by etching a semiconductor layer 1150 crystallized and grown on a substrate 102. Then, the light-emitting element 150 is covered with a first interlayer insulating film 156, and a circuit 101 including circuit elements such as a transistor 103 driving the light-emitting element 150 is fabricated on the first interlayer insulating film 156. Therefore, compared to the case where the monolithically formed light-emitting elements are individually transferred to the substrate 102, the manufacturing process can be significantly shortened.

[0208] In the manufacturing method of the image display device 1 of this embodiment, the conductive layer 1130a is formed by crystallizing the conductive layer 1130 formed on the substrate 102, which can serve as a seed crystal for the crystallization and growth of the semiconductor layer 1150. For example, the conductive layer 1130 can be crystallized by laser annealing, thus achieving sufficiently high productivity.

[0209] For example, in a 4K image quality display device, the number of subpixels exceeds 24 million, and in an 8K image quality display device, the number exceeds 99 million. Forming such a large number of light-emitting elements and mounting them on a circuit board requires a significant amount of time. Therefore, it is difficult to realize a micro-LED-based image display device at a realistic cost. Furthermore, if a large number of light-emitting elements are mounted separately, poor connections during installation can lead to a lower yield rate and further increases in cost.

[0210] In contrast, in the manufacturing method of the image display device 1 of this embodiment, the light-emitting element 150 is formed after the semiconductor layer 1150 is deposited on the conductive layer 1130 formed on the substrate 102. Therefore, the transfer process of the light-emitting element 150 can be reduced. Thus, in the manufacturing method of the image display device 1 of this embodiment, the transfer process time can be shortened and the number of processes can be reduced compared to the conventional manufacturing method.

[0211] A semiconductor layer 1150 with a uniform crystalline structure is grown on a conductive layer 1130a of a single-crystal metal. Therefore, by appropriately patterning the conductive layer 1130a, the light-emitting element 150 can be self-aligned. Thus, there is no need to align the light-emitting element on the substrate 102, and the miniaturization of the light-emitting element 150 is also easy, making it suitable for high-resolution displays.

[0212] After the light-emitting element is directly formed on the substrate 102 by etching or the like, the light-emitting element 150 and the circuit elements formed on the upper layer of the light-emitting element 150 are electrically connected through through holes. Therefore, a uniform connection structure can be achieved, and the decrease in yield can be suppressed.

[0213] In this embodiment, for example, an interlayer insulating film can be used to cover the glass substrate formed as described above, and a driving circuit including TFTs and scanning circuits can be formed on the planarized surface using a process such as LTPS. Therefore, it has the advantage of being able to utilize existing flat panel display manufacturing processes and complete sets of equipment.

[0214] In this embodiment, the light-emitting element 150, formed on a layer lower than transistor 103, can be electrically connected to power lines, ground lines, driving transistors, etc., formed on the upper layer by forming through-holes that penetrate the first interlayer insulating film 156, the lower TFT film 106, the insulating layer 105, and the second interlayer insulating film 108. By using this technically established multilayer wiring technology, a uniform connection structure can be easily achieved, and the yield rate can be improved. Therefore, the decrease in yield rate caused by poor connection of the light-emitting element, etc., can be suppressed.

[0215] In this embodiment, a conductive layer 130 is formed on a first surface 102a of the substrate 102. The conductive layer 130 includes a connecting plate 130a. A light-emitting element 150 is formed on the connecting plate 130a and electrically connected to the connecting plate 130a via a bottom surface 153B. The connecting plate 130a is formed of a material with high conductivity, such as a metal. Therefore, the p-type semiconductor layer 153 of the light-emitting element 150 can be electrically connected to other circuits with low resistance.

[0216] Furthermore, the lower p-type semiconductor layer 153 is connected to the highly conductive connecting plate 130a via its bottom surface 153B, thus eliminating the need for a laterally oriented connecting portion and allowing for a reduction in the overall thickness of the light-emitting element 150. Consequently, the thickness of the first interlayer insulating film 156 can also be reduced, and the depth of the via 161a can be decreased, thereby reducing its diameter. Therefore, the processing accuracy of the via 161a can be substantially improved.

[0217] The connecting plate 130a can be formed of a light-reflective metallic material such as Cu or Hf. The outer periphery of the connecting plate 130a is formed such that, when viewed from above in the XY plane, it includes the outer periphery of the light-emitting element 150 as it would be when the projection light-emitting element 150 is included. That is, when viewed from above in the XY plane, the outer periphery of the light-emitting element 150 is disposed within the outer periphery of the connecting plate 130a. Therefore, the connecting plate 130a also functions as a light reflector, reflecting scattered light and the like downwards towards the light-emitting element 150 onto the light-emitting surface 151S, thereby substantially improving the luminous efficiency of the light-emitting element 150.

[0218] (Second Implementation)

[0219] Figure 12 This is a schematic cross-sectional view illustrating a portion of the image display device of this embodiment.

[0220] In this embodiment, the p-type semiconductor layer 253 provides the light-emitting surface 253S, and the configuration of the transistor 203 differs from that in the other embodiments described above. The same reference numerals are used to denote components identical to those in other embodiments, and detailed descriptions are omitted where appropriate.

[0221] like Figure 12 As shown, the sub-pixel 220 of the image display device in this embodiment includes a substrate 102, a conductive layer 130, a light-emitting element 250, a first interlayer insulating film 156, a transistor 203, a second interlayer insulating film 108, and a wiring layer 110.

[0222] The light-emitting element 250 is disposed on the connecting plate 130a. The outer periphery of the connecting plate 130a is configured such that, when the XY plane is viewed from above, the outer periphery of the light-emitting element 250 is included when the light-emitting element 250 is projected. That is, when the XY plane is viewed from above, the outer periphery of the light-emitting element 250 is disposed within the outer periphery of the connecting plate 130a. Therefore, it is possible to reflect scattered light downwards from the light-emitting element 250 toward the light-emitting surface 253S side, thereby substantially improving the luminous efficiency of the light-emitting element 250, which is the same as in the other embodiments described above.

[0223] The light-emitting element 250 includes a light-emitting surface 253S. Similar to the other embodiments described above, the light-emitting element 250 is a prism-shaped or cylindrical element with a bottom surface 251B on the connecting plate 130a. In the light-emitting element 250, the light-emitting surface 253S is the side opposite to the bottom surface 251B. The bottom surface 251B is connected to the connecting plate 130a.

[0224] The light-emitting element 250 includes an n-type semiconductor layer 251, a light-emitting layer 252, and a p-type semiconductor layer 253. The n-type semiconductor layer 251, the light-emitting layer 252, and the p-type semiconductor layer 253 are stacked sequentially from the bottom surface 251B toward the light-emitting surface 253S. In this embodiment, the light-emitting surface 253S is provided by the p-type semiconductor layer 253.

[0225] The light-emitting element 250 has the same characteristics as... Figure 1 The light-emitting element 150 shown has the same shape when viewed from above in the XY plane. An appropriate shape is selected based on the layout of the circuit components, etc.

[0226] The light-emitting element 250 is the same light-emitting diode as the light-emitting element 150 in the other embodiments described above. That is, the wavelength of the light emitted by the light-emitting element 250 is, for example, blue light emitting at approximately 467nm ± 30nm, or blue-violet light emitting at approximately 410nm ± 30nm. The wavelength of the light emitted by the light-emitting element 250 is not limited to the above values ​​and can be any appropriate wavelength.

[0227] Transistor 203 is disposed on the lower TFT film 106. Transistor 203 is a p-channel TFT. Transistor 203 includes a TFT channel 204 and a gate 107. Preferably, transistor 203 is formed by an LTPS process or the same as in other embodiments described above. In this embodiment, circuit 101 includes a TFT channel 204, an insulating layer 105, a second interlayer insulating film 108, vias 111s and 111d, and a wiring layer 110.

[0228] The TFT channel 204 includes regions 204s, 204i, and 204d. Regions 204s, 204i, and 204d are disposed on the lower TFT film 106. Regions 204s and 204d are doped with impurities such as boron (B) through ion implantation to form p-type semiconductor regions. Region 204s is ohmically connected to via 111s. Region 204d is ohmically connected to via 111d.

[0229] The gate 107 is disposed on the TFT channel 204 through an insulating layer 105. The insulating layer 105 insulates the TFT channel 204 from the gate 107.

[0230] In transistor 203, if a voltage lower than that applied to gate 107 than that applied to region 204s, a channel is formed in region 204i. The current flowing through regions 204s and 204d is controlled by the voltage applied to gate 107 in region 204s. The TFT channel 204 and gate 107 are formed using the same materials and methods as in the other embodiments described above.

[0231] Wiring layer 110 includes wirings 110s, 110d, and 210k. Wirings 110s and 110d are the same as in the first embodiment. A portion of wiring 210k is disposed above the connection plate 130a. Other portions of wiring 210k extend, for example, to the following description. Figure 13 The grounding wire 4 shown is connected to the grounding wire 4.

[0232] Through-holes 111s and 111d are provided through the second interlayer insulating film 108. Through-hole 111s is located between wiring 110s and region 204s. Through-hole 111s electrically connects wiring 110s and region 204s. Through-hole 111d is located between wiring 110d and region 204d. Through-hole 111d electrically connects wiring 110d and region 204d. Through-holes 111s and 111d are formed from the same material and using the same manufacturing method as in the other embodiments described above.

[0233] The via 161k is disposed through the second interlayer insulating film 108, the insulating layer 105, the TFT lower layer film 106, and the first interlayer insulating film 156. The via 161k is disposed between the wiring 210k and the connecting plate 130a, electrically connecting the wiring 210k and the connecting plate 130a.

[0234] Wiring 110s, for example, electrical connections as described later. Figure 13 The power line 3 is shown. Wiring 110d is electrically connected to the p-type semiconductor layer 253 via a transparent electrode 159d.

[0235] In this embodiment, the light-transmitting electrode 159d is disposed throughout the light-emitting surface 253S of the roughened p-type semiconductor layer 253. The light-transmitting electrode 159d is also disposed throughout the wiring 110d. The light-transmitting electrode 159d is also disposed between the light-emitting surface 253S and the wiring 110d, electrically connecting the p-type semiconductor layer 253 and the wiring 110d. In a variation of the first embodiment described above, it is also possible to... Figure 2 As shown in the example, the extended wiring 110d1 is directly connected to the p-type semiconductor layer 253.

[0236] Figure 13 This is a schematic block diagram illustrating the image display device of this embodiment.

[0237] like Figure 13 As shown, the image display device 201 of this embodiment includes a display area 2, a row selection circuit 205, and a signal voltage output circuit 207. In the display area 2, as in other embodiments described above, for example, the sub-pixels 220 are arranged in a grid pattern on the XY plane.

[0238] Pixel 10, like the other embodiments described above, includes multiple sub-pixels 220 that emit light of different colors. Sub-pixel 220R emits red light. Sub-pixel 220G emits green light. Sub-pixel 220B emits blue light. The three sub-pixels 220R, 220G, and 220B emit light at a desired brightness, thereby determining the emission color and brightness of pixel 10.

[0239] A pixel 10 contains three subpixels 220R, 220G, and 220B, which are arranged in a straight line along the X-axis, as shown in this example. Each pixel 10 can arrange subpixels of the same color in the same column, or it can arrange subpixels of different colors in each column, as shown in this example.

[0240] Subpixel 220 includes a light-emitting element 222, a selection transistor 224, a driving transistor 226, and a capacitor 228. Figure 13 In the text, sometimes the select transistor 224 is shown as T1, the drive transistor 226 is shown as T2, and the capacitor 228 is shown as Cm.

[0241] In this embodiment, the light-emitting element 222 is disposed on the ground line 4 side, and the driving transistor 226, connected in series with the light-emitting element 222, is disposed on the power line 3 side. That is, the driving transistor 226 is connected to a side with a lower potential than the light-emitting element 222. The driving transistor 226 is a p-channel transistor.

[0242] A select transistor 224 is connected between the gate electrode of the driving transistor 226 and the signal line 208. A capacitor 228 is connected between the gate electrode of the driving transistor 226 and the power supply line 3.

[0243] The row selection circuit 205 and the signal voltage output circuit 207 supply a signal voltage of a different polarity to the signal line 208 in order to drive the driving transistor 226, which is a p-channel transistor. This is different from the other embodiments described above.

[0244] In this embodiment, since the driving transistor 226 is p-channel, the polarity of the signal voltage differs from that in the other embodiments described above. Specifically, the row selection circuit 205 supplies a selection signal to the scan line 206 to sequentially select one row from the arrangement of m rows of sub-pixels 220. The signal voltage output circuit 207 supplies a signal voltage with the desired analog voltage value to each sub-pixel 220 of the selected row. The driving transistor 226 of the selected row's sub-pixel 220 causes a current corresponding to the signal voltage to flow through the light-emitting element 222. The light-emitting element 222 emits light with a brightness corresponding to the current flowing through it.

[0245] The manufacturing method of the image display device according to this embodiment will be described.

[0246] Figures 14A to 16B This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to this embodiment.

[0247] In this example, it is possible to use methods that are similar to the other embodiments described above. Figure 5A The conductive layer 1130, described in connection with this, is formed on the substrate 102 on the first surface 102a. Hereinafter, the conductive layer 1130 is described on the substrate 102. Figure 5A Application after the process Figure 14A The situation regarding subsequent processes.

[0248] like Figure 14A As shown, in the manufacturing method of the image display device of this embodiment, Figure 5AThe conductive layer 1130 shown is subjected to single-crystallization treatment, and the single-crystallized conductive layer 1130a is formed on the first surface 102a. A semiconductor layer 1150 is formed on the conductive layer 1130a. In this embodiment, the semiconductor layer 1150 is formed from the conductive layer 1130a toward the positive Z-axis in the order of an n-type semiconductor layer 1151, a light-emitting layer 1152, and a p-type semiconductor layer 1153. The semiconductor layer 1150 is formed using the same film deposition technique as in the other embodiments described above. That is, in the formation of the semiconductor layer 1150, low-temperature sputtering is preferred; other methods include physical vapor deposition, ion beam deposition, and MBE.

[0249] In the early stages of semiconductor layer 1150 growth, crystallization defects caused by lattice mismatch are prone to occur, and GaN-based crystals generally exhibit n-type semiconductor characteristics. Therefore, in this embodiment, by growing semiconductor layer 1150 from n-type semiconductor layer 1151 on conductive layer 1130a, the yield rate can be improved. In some cases, a deposit containing the growth-type material is deposited in areas where conductive layer 1130a is absent, as is the case in other embodiments described above.

[0250] like Figure 14B As shown, Figure 14A The semiconductor layer 1150 shown is shaped into a desired form to form a light-emitting element 250. The light-emitting element 250 is formed, for example, using a dry etching process, preferably using RIE.

[0251] Figure 14A The conductive layer 1130a shown is etched into a conductive layer 130 containing a connecting plate 130a. Thus, the connecting plate 130a is formed under the light-emitting element 250.

[0252] like Figure 15A As shown, the first interlayer insulating film 156 is formed to cover the first surface 102a, the conductive layer 130, and the light-emitting element 250.

[0253] like Figure 15B As shown, a TFT lower layer film 106 is formed on the exposed surface of the first interlayer insulating film 156. The TFT lower layer film 106 is formed using CVD or the like. A TFT channel 204 is formed at a predetermined position on the TFT lower layer film 106 and is activated, etc. Furthermore, an insulating layer 105 is formed on both the TFT lower layer film 106 and the TFT channel 204. A gate 107 is formed on the TFT channel 204 via the insulating layer 105. The above formation process is the same as in other embodiments described above, and it is preferable to use an LTPS process.

[0254] The second interlayer insulating film 108 is formed by spreading it over the insulating layer 105 and the gate 107.

[0255] like Figure 16A As shown, the via 162k is formed to penetrate the second interlayer insulating film 108, the insulating layer 105, the TFT lower layer film 106, and the first interlayer insulating film 156 to reach the connecting plate 130a. The opening 158 is formed to reach the light-emitting surface 253S by removing a portion of the second interlayer insulating film 108, a portion of the insulating layer 105, a portion of the TFT lower layer film 106, and a portion of the first interlayer insulating film 156. As in this example, the central portion of the surface of the p-type semiconductor layer 253 exposed by removing the first interlayer insulating film 156, etc., can be etched in the thickness direction of the p-type semiconductor layer 253 to form the light-emitting surface 253S. The light-emitting surface 253S is preferably roughened, which is the same as in the other embodiments described above.

[0256] The through holes 112d and 112s are formed in the same way as in the other embodiments described above.

[0257] like Figure 16B As shown, through holes 161k, 111d, and 111s pass through... Figure 16A The vias 162k, 112d, and 112s shown are formed by filling them with conductive material. Similar to the other embodiments described above, a wiring layer 110 containing wirings 210k, 110d, and 110s is then formed, with wirings 210k, 110d, and 110s respectively connected to vias 161k, 111d, and 111s.

[0258] A transparent conductive film, including transparent electrodes 159k, 159d, and 159s, is formed on wirings 210k, 110d, and 110s, respectively. Wiring 210k and transparent electrodes 159k are, for example, electrically connected to... Figure 13 Grounding wire 4 of the circuit shown.

[0259] Then, by setting a color filter 180, etc., the sub-pixels 220 of the image display device 201 of this embodiment are formed.

[0260] The effects of the image display device in this embodiment will be explained.

[0261] In the image display device of this embodiment, similar to the other embodiments described above, in addition to shortening the transfer process time for forming the light-emitting element 250 and reducing the number of processes, the light-emitting surface 253S can be made a p-type semiconductor layer 253 by making the polarity of the TFT a p-channel. Therefore, it has advantages such as increasing the arrangement of circuit elements and the freedom of circuit design.

[0262] In the manufacturing method of the image display device of this embodiment, since it is grown from an n-type semiconductor layer, the yield rate when forming the semiconductor layer can be improved.

[0263] (Third Implementation)

[0264] Figure 17 This is a schematic cross-sectional view illustrating a portion of the image display device of this embodiment.

[0265] In this embodiment, the graphene layer 140 is provided on the conductive layer 130, and a graphene sheet 140a is provided between the connecting plate 130a and the light-emitting element 150, which differs from the other embodiments described above. The same reference numerals are used to denote the same components as in the other embodiments described above, and detailed descriptions are omitted where appropriate.

[0266] like Figure 17 As shown, the sub-pixel 320 of the image display device in this embodiment includes a graphene layer 140. The graphene layer 140 is disposed on the conductive layer 130. The graphene layer 140 includes a graphene sheet 140a. The graphene sheet 140a, containing a layer of graphene, is disposed between the connecting plate 130a and the light-emitting element 150. The graphene sheet 140a is conductive, thus electrically connecting the light-emitting element 150 and the connecting plate 130a. The graphene layer 140 and the graphene sheet 140a are layered structures consisting of several to approximately 10 layers of single-layer graphene.

[0267] When viewed from above in the XY plane, the graphene sheet 140a has an outer perimeter that is approximately the same as the outer perimeter of the light-emitting element 150.

[0268] In this embodiment, the light-emitting element 150 is configured in the same manner as in the first embodiment. That is, it is stacked from the bottom surface 153B toward the light-emitting surface 151S in the order of p-type semiconductor layer 153, light-emitting layer 152, and n-type semiconductor layer 151.

[0269] The bottom surface 153B is a p-type semiconductor layer 153, which is electrically connected to the connecting plate 130a via a graphene sheet 140a. In this example, the light-emitting surface 151S is roughened, but roughening can also be omitted.

[0270] The configuration of the first interlayer insulating film 156 and the transistor 103 is the same as in the first embodiment, and detailed descriptions are omitted.

[0271] The manufacturing method of the image display device according to this embodiment will be described.

[0272] Figures 18A to 20B This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to this embodiment.

[0273] like Figure 18AAs shown, a graphene layer (a layer containing graphene) 1140 is patterned and formed over a conductive layer 1130a that has been single-crystallized by annealing. The graphene layer 1140 is formed, for example, by a low-temperature processing unit such as pulse sputtering.

[0274] like Figure 18B As shown, a semiconductor layer 1150 is formed over a graphene layer 1140. In this embodiment, the semiconductor layer 1150 is formed from one side of the conductive layer 1130a and the graphene layer 1140 toward the positive Z-axis in the order of a p-type semiconductor layer 1153, a light-emitting layer 1152, and an n-type semiconductor layer 1151.

[0275] In the formation of the semiconductor layer 1150, as in other embodiments, physical vapor deposition methods such as evaporation, ion beam deposition, MBE, and sputtering are used, with low-temperature sputtering being preferred. By growing the GaN semiconductor layer 1150 on the graphene layer 1140, a single-crystallized semiconductor layer 1150 including the light-emitting layer 1152 is formed throughout the graphene layer 1140 (see Non-Patent Literature 1, 2, etc.).

[0276] It is known that when GaN crystals are grown using pulse sputtering, GaN crystal growth is promoted on a graphene layer. In this embodiment, a semiconductor layer 1150 is formed by depositing a graphene layer 1140 grown over a conductive layer 1130a that permeates a single-crystal metal layer, thus enabling the formation of a semiconductor layer 1150 with more stable and higher quality GaN crystals.

[0277] Furthermore, in this embodiment, Figure 17 The conductive layer 130 and the connecting plate 130a shown are formed of a single crystal metal layer, and therefore can be electrically connected to the semiconductor layer 1150 with low resistance.

[0278] like Figure 18C As shown, the semiconductor layer 1150 is shaped into the necessary form using a RIE (Rubber-Insulated Sheet) or similar method to form the light-emitting element 150. At this time, Figure 18B The graphene layer 1140 shown is over-etched to form a graphene sheet (a graphene-containing layer) 140a with an outer peripheral shape corresponding to the outer peripheral shape of the light-emitting element 150. Then, Figure 18B The conductive layer 1130a shown is etched into a conductive layer 130 to form a connecting plate 130a of the desired shape.

[0279] like Figure 19A As shown, the first interlayer insulating film 156 is formed by covering the first surface 102a, the conductive layer 130, the graphene sheet 140a, and the light-emitting element 150.

[0280] like Figure 19BAs shown, a TFT lower layer film 106 is formed on the exposed surface of the first interlayer insulating film 156. Then, as in the other embodiments described above, a transistor 103 is formed through an LTPS process, etc., and a second interlayer insulating film 108 is formed.

[0281] like Figure 20A As shown, through holes 162a, 112d, and 112s are formed, and the light-emitting surface 151S is exposed through the opening 158.

[0282] like Figure 20B As shown, vias 161a, 111d, and 111s are formed. A wiring layer 110 containing wirings 110a, 110d, and 110s is formed, with wirings 110a, 110d, and 1110s connected to vias 161a, 111d, and 111s, respectively. Transparent electrodes 159a, 159d, and 159s are formed across wirings 110a, 110d, and 110s, respectively.

[0283] Then, as in other implementations, a color filter is formed.

[0284] The effects of the image display device in this embodiment will be explained.

[0285] In this embodiment, similar to the other embodiments described above, in addition to shortening the transfer process time for forming the light-emitting element 150 and reducing the number of processes, it also has the following effect: In this embodiment, the light-emitting element 150 is formed via a graphene sheet 140a formed on a single-crystal metal connecting plate 130a. Therefore, the image display device of this embodiment can obtain a light-emitting element 150 with a higher quality crystalline structure. Consequently, the yield rate of the image display device can be improved.

[0286] The addition of graphene layer 140 and graphene sheet 140a is not limited to this embodiment, but can also be applied to variations of the first embodiment and the second embodiment described above, as well as other embodiments described later.

[0287] (Fourth Implementation)

[0288] Figure 21 This is a schematic cross-sectional view illustrating a portion of the image display device of this embodiment.

[0289] In this embodiment, the through-hole 461a is located between the connecting plate 130a and the wiring 410d, which differs from the first embodiment. The light-emitting element 150 is also driven by the p-type transistor 203, which differs from the first embodiment. The same reference numerals are used for components that are the same as in the other embodiments described above, and detailed descriptions are omitted where appropriate.

[0290] like Figure 21 As shown, the sub-pixel 420 of the image display device in this embodiment includes a substrate 102, a conductive layer 130, a light-emitting element 150, a first interlayer insulating film 156, a transistor 203, a second interlayer insulating film 108, a via 461a, and a wiring layer 110. The transistor 203 is a p-channel TFT. The light-emitting element 150 provides a light-emitting surface 151S based on an n-type semiconductor layer 151. The bottom surface 153B of the light-emitting element 150 is disposed on a connecting plate 130a, and the p-type semiconductor layer 153 is electrically connected to the connecting plate 130a.

[0291] The connecting plate 130a is configured in the same manner as in the first embodiment. That is, the connecting plate 130a is positioned directly below the light-emitting element 150, and the outer periphery of the connecting plate 130a is configured such that, when the light-emitting element 150 is projected onto the connecting plate 130a in a top-view XY plane, it includes the outer periphery of the light-emitting element 150. In other words, when the light-emitting element 150 is viewed from above in the XY plane, its outer periphery is disposed within the outer periphery of the connecting plate 130a. Therefore, the connecting plate 130a also functions as a light reflector, improving the actual luminous efficiency of the light-emitting element 150.

[0292] Wiring layer 110 is formed on the second interlayer insulating film 108. Wiring layer 110 includes wirings 410k, 410d, and 110s. Wiring 410k, for example, is connected to... Figure 13 Grounding wire 4 of the circuit shown.

[0293] A portion of the wiring (third wiring) 410d is disposed above the transistor 203 and connected to region 204d via via 111d. Another portion of the wiring 410d is disposed near the light-emitting element 150 and connected to the connecting plate 130a via via 461a. Specifically, via 461a is provided through the second interlayer insulating film 108, the insulating layer 105, the TFT lower layer film 106, and the first interlayer insulating film 156. Via 461a is located between the connecting plate 130a and the wiring 410d, electrically connecting the connecting plate 130a and the wiring 410d.

[0294] A light-transmitting electrode 159k is disposed along the wiring 410k. The light-transmitting electrode 159k is disposed along the light-emitting surface 151S. The light-transmitting electrode 159k is located between the wiring 410k and the light-emitting surface 151S. Therefore, the n-type semiconductor layer 151 is electrically connected, for example, to the light-transmitting electrode 159k and the wiring (fourth wiring) 410k. Figure 13 Grounding wire 4 of the circuit shown.

[0295] A light-transmitting electrode 159d is disposed on the wiring 410d. Therefore, the p-type semiconductor layer 153 is electrically connected to the region 204d, which serves as the drain electrode of the transistor 203, via the connecting plate 130a, the via 461a, the wiring 410d, the light-transmitting electrode 159d, and the via 111d.

[0296] A light-transmitting electrode 159s is disposed along the wiring 110s. The wiring 110s and the light-transmitting electrode 159s are, for example, connected to... Figure 13 The power line 3 is shown. Therefore, region 204s of transistor 203 is electrically connected to the via 111s, wiring 110s, and transparent electrode 159s. Figure 13 Power line 3 of the circuit shown.

[0297] Through holes 461a, 111d, 111s and wiring 410k, 410d, 110s are formed from the same materials and manufacturing methods as in the other embodiments and variations described above.

[0298] Similar to the other embodiments described above, a color filter 180 is also provided.

[0299] The manufacturing method of the image display device according to this embodiment will be described.

[0300] Figure 22A as well as Figure 22B This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to this embodiment.

[0301] In the manufacturing method of this embodiment, the order is the same as that in the manufacturing method of the first embodiment up to the middle. Hereinafter, the process will be described... Figure 6B After the process of forming the second interlayer insulating film 108, the following steps are performed. Figure 22A as well as Figure 22B The situation regarding the process. However, in Figure 6B In the previous embodiment, an n-channel transistor 103 was formed on the lower TFT film 106. In contrast, in this embodiment, a p-channel transistor 203 is formed on the lower TFT film 106. The method for forming the p-channel transistor 203 is the same as in the second embodiment already described, and detailed description is omitted.

[0302] like Figure 22A As shown, the through-hole 462a is formed to penetrate the second interlayer insulating film 108, the insulating layer 105, the TFT lower layer film 106, and the first interlayer insulating film 156 to reach the connecting plate 130a. The opening 158 and the through holes 112d and 112s are formed in the same way as in the other embodiments described above.

[0303] like Figure 22B As shown, Figure 22AThe vias 462a, 112d, and 112s shown are filled with conductive material to form vias 461a, 111d, and 111s. A wiring layer 110 is formed on the second interlayer insulating film 108. A light-transmitting conductive film is formed on the wiring layer 110 to form light-transmitting electrodes 159k, 159d, and 159s.

[0304] The effects of the image display device in this embodiment will be explained.

[0305] The image display device according to this embodiment, in addition to the effects described in the first embodiment, also has the following effects. Specifically, in this embodiment, a circuit configuration can be formed in which the light-emitting surface 151S is an n-type semiconductor layer 151, and the light-emitting element 150 is driven by a p-channel transistor 203. Therefore, it is possible to expand the possibilities for changes in circuit configuration, etc., and to perform flexible circuit design.

[0306] (Fifth Implementation)

[0307] Figure 23 This is a schematic cross-sectional view illustrating a portion of the image display device of this embodiment.

[0308] The image display device of this embodiment replaces the glass substrate with a flexible substrate 502. Light-emitting elements and circuit elements such as transistors are formed on the first surface 502a of the substrate 502. Other aspects are the same as in the first embodiment described above; the same reference numerals are used to refer to the same constituent elements, and detailed descriptions are omitted where appropriate.

[0309] like Figure 23 As shown, the image display device of this embodiment includes a sub-pixel 520. The sub-pixel 520 includes a substrate 502. The substrate 502 includes a first surface 502a. When the substrate 502 is formed of an organic material such as resin, a layer 507 containing a silicon compound is formed on the first surface 502a. The silicon compound-containing layer 507 is composed of SiO2, SiN... x The conductive layer 130 is formed from a metallic material, and a layer 507 containing a silicon compound is provided to improve the adhesion between the substrate 502 and the conductive layer 130.

[0310] The conductive layer 130 and the connecting plate 130a are disposed on the first surface 502a via a silicon compound-containing layer 507. In this example, the structure and constituent elements above the conductive layer 130 and the connecting plate 130a are the same as in the first embodiment described above, and detailed descriptions are omitted.

[0311] The substrate 502 is flexible. The substrate 502 is formed, for example, from polyimide resin. The first interlayer insulating film 156, the second interlayer insulating film 108, and the wiring layer 110 are preferably formed from materials with a certain degree of flexibility, corresponding to the flexibility of the substrate 502. Furthermore, the wiring layer 110, which has the longest wiring length, is at the highest risk of being damaged during bending. When the image display device is bent, the inner surface is subjected to compressive stress and shrinks, while the outer surface is subjected to elongation stress and stretches. A neutral surface exists inside the image display device where the stresses of both sides are offset, and no stretching or contraction due to bending stress occurs on the neutral surface. Therefore, by placing the wiring layer 110 on the neutral surface, the risk of damage to the wiring layer 110 can be avoided. If necessary, multiple protective films can also be provided on the surface and back of the image display device to reduce stress caused by bending. Furthermore, it is preferable to adjust the thickness, film quality, and material of these protective films so that the neutral surface overlaps with the wiring layer 110.

[0312] In this example, the structure and constituent elements above the silicon compound layer 507 are the same as in the first embodiment, but other embodiments and variations described above are also possible. Furthermore, in the sixth embodiment described later, the flexible substrate 502 of this embodiment can also be used.

[0313] The manufacturing method of the image display device according to this embodiment will be described.

[0314] Figure 24A as well as Figure 24B This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to this embodiment.

[0315] like Figure 24A As shown, in this embodiment, a substrate 1002 is prepared that differs from the other embodiments described above. The substrate 1002 includes two substrates 102 and 502. The substrate (first substrate) 102 is, for example, a glass substrate. The substrate (second substrate) 502 is disposed on a first surface 102a of the substrate 102. For example, the substrate 502 is formed by coating polyimide onto the first surface 102a and then firing it. Alternatively, SiN can be formed on the first surface 102a before forming the substrate 502. x Inorganic films, etc. In this case, substrate 502 is formed by coating an inorganic film with a polyimide material and then firing it.

[0316] A layer 507 containing a silicon compound is formed on the first surface 502a of the substrate 502. The first surface 502a of the substrate 502 is the side opposite to the surface on which the substrate 102 is provided.

[0317] A conductive layer 1130 is formed on the exposed surface of the silicon compound-containing layer 507 formed on this substrate 1002, and then patterned. Afterwards, by applying, for example... Figures 5B to 7B , Figure 9 as well as Figures 10A to 10D The above-mentioned process forms the upper structure of sub-pixel 520.

[0318] like Figure 24B As shown, substrate 102 is removed from a structure having an upper structure including color filters (not shown). The removal of substrate 102 is performed, for example, by laser stripping.

[0319] The removal of substrate 102 is not limited to the time mentioned above and can be performed at any appropriate time. Since there are processes that expose substrate 102 to high temperatures after its removal, there is a concern that heating may cause substrate 502 to shrink, etc., if the substrate 502 is made of organic resin. Therefore, it is preferable to remove substrate 102 in a process following such a high-temperature exposure process. For example, substrate 102 is preferably removed after the process of forming wiring layer 110 is completed. By removing substrate 102 at an appropriate time, defects such as cracks and defects in the manufacturing process can sometimes be reduced.

[0320] The effects of the image display device in this embodiment will be explained.

[0321] In addition to the effects described in the other embodiments, the image display device of this embodiment also has the following effects. That is, since the substrate 502 is flexible, it can be bent as an image display device, and can be adhered to curved surfaces and used in wearable terminals without any sense of disharmony.

[0322] (Sixth Implementation Method)

[0323] Figure 25 This is a schematic cross-sectional view illustrating a portion of the image display device of this embodiment.

[0324] In this embodiment, by forming multiple light-emitting surfaces 653S1, 653S2 on a single semiconductor layer 650 including a light-emitting layer, an image display device with higher luminous efficiency is achieved. In the following description, the same reference numerals are used to denote the same components as in other embodiments described above, and detailed descriptions are omitted where appropriate.

[0325] like Figure 25As shown, the image display device of this embodiment includes a subpixel group 620. The subpixel group 620 includes a substrate 102, a conductive layer 130, a semiconductor layer 650, a first interlayer insulating film 156, a plurality of transistors 203-1 and 203-2, a second interlayer insulating film 108, and a wiring layer 110. The conductive layer 130 includes a connecting plate 630a. The connecting plate (second part) 630a is disposed on a first surface 102a of the substrate 102. The semiconductor layer 650 is disposed on the connecting plate 630a. In the cross-sectional views of this embodiment, to avoid visual clutter, the reference numerals for the conductive layer 130 and the connecting plate 630a are listed side-by-side.

[0326] In this embodiment, the conductive layer 130 and the connecting plate 630a are connected, for example, to... Figure 13 The circuit's grounding wire 4. By turning on the p-channel transistors 203-1 and 203-2, electrons are injected from one side of the semiconductor layer 650 via the conductive layer 130 and the connecting plate 130a. By turning on the p-channel transistors 203-1 and 203-2, holes are injected from the other side of the semiconductor layer 650 via the wiring layer 110. The semiconductor layer 650 is injected with holes and electrons, and the light-emitting layer 652 emits light through the combination of holes and electrons.

[0327] For example, a driving circuit for driving the light-emitting layer 652 is applicable. Figure 13 The circuit configuration is shown. As in the other embodiments described above, it can also be configured with an n-type semiconductor layer and a p-type semiconductor layer alternating vertically, and the semiconductor layer driven by an n-channel transistor. In this case, the driving circuit, for example, uses... Figure 3 The circuit configuration.

[0328] The composition of subpixel group 620 is explained in detail.

[0329] A conductive layer 130 is disposed on the first surface 102a. The conductive layer 130 includes a connecting plate 630a. A semiconductor layer 650 is disposed on the first surface 102a via the connecting plate 630a. The semiconductor layer 650 has a bottom surface 651B, and the connecting plate 630a is connected to the bottom surface 651B. The outer periphery of the connecting plate 630a is configured such that, when the semiconductor layer 650 is projected onto the connecting plate 630a in a top-view XY plane, the outer periphery of the semiconductor layer 650 is included. That is, when the XY plane is viewed from above, the outer periphery of the semiconductor layer 650 is disposed within the outer periphery of the connecting plate 630a. The conductive layer 130 and the connecting plate 630a are formed of metallic materials such as Cu and Hf, and therefore have light reflectivity. Thus, the connecting plate 630a reflects scattered light below the semiconductor layer 650 toward the upward-emitting surfaces 653S1 and 653S2. Therefore, the actual luminous efficiency of semiconductor layer 650 is improved.

[0330] Semiconductor layer 650 includes a plurality of light-emitting surfaces 653S1 and 653S2. Semiconductor layer 650 is a prism-shaped or cylindrical laminate having a bottom surface 651B connected to connecting plate 630a. Light-emitting surfaces 653S1 and 653S2 are surfaces opposite to the bottom surface 651B. Light-emitting surfaces 653S1 and 653S2 are preferably surfaces in a plane substantially parallel to the bottom surface 651B. The plane containing light-emitting surface 653S1 and the plane containing light-emitting surface 653S2 can be the same plane or different planes. Light-emitting surfaces 653S1 and 653S2 are disposed separately in the X-axis direction.

[0331] Semiconductor layer 650 includes an n-type semiconductor layer 651, a light-emitting layer 652, and a p-type semiconductor layer 653. The n-type semiconductor layer 651, the light-emitting layer 652, and the p-type semiconductor layer 653 are stacked sequentially from the bottom surface 651B toward the light-emitting surfaces 653S1 and 653S2.

[0332] The bottom surface 651B is an n-type semiconductor, and the n-type semiconductor layer 651 is electrically connected to an external circuit connected via the bottom surface 651B and the connecting plate 630a. In this case, the external circuit is, for example, an n-type semiconductor. Figure 13 4. Grounding wire of the circuit.

[0333] The p-type semiconductor layer 653 has two light-emitting surfaces 653S1 and 653S2 on its upper surface. That is, a subpixel group 620 substantially contains two subpixels. In this embodiment, as in the other embodiments described above, the display area is formed by arranging the subpixel groups 620, which substantially contain two subpixels, in a grid pattern.

[0334] A first interlayer insulating film (first insulating film) 156 covers the first surface 102a, the conductive layer 130, the side surface of the n-type semiconductor layer 651, the side surface of the light-emitting layer 652, and the side surface of the p-type semiconductor layer 653. The first interlayer insulating film 156 covers a portion of the upper surface of the p-type semiconductor layer 653. The light-emitting surfaces 653S1 and 653S2 in the p-type semiconductor layer 653 are not covered by the first interlayer insulating film 156. The first interlayer insulating film 156 is the same as in other embodiments described above, and is preferably made of white resin.

[0335] A TFT lower layer film 106 is formed on the first interlayer insulating film 156. The TFT lower layer film 106 is not disposed on the light-emitting surfaces 653S1 and 653S2. The TFT lower layer film 106 is planarized, and TFT channels 204-1, 204-2, etc. are formed on the TFT lower layer film 106.

[0336] An insulating layer 105 covers the lower TFT film 106 and TFT channels 204-1 and 204-2. A gate 107-1 is disposed on TFT channel 204-1 via the insulating layer 105. A gate 107-2 is disposed on TFT channel 204-2 via the insulating layer 105. Transistor 203-1 includes TFT channel 204-1 and gate 107-1. Transistor 203-2 includes TFT channel 204-2 and gate 107-2.

[0337] The second interlayer insulating film 108 (second insulating film) covers the insulating layer 105 and the gates 107-1 and 107-2.

[0338] TFT channels 204-1 and 204-2 contain p-type doped regions, and transistors 203-1 and 203-2 are p-channel TFTs. Transistor 203-1 is located closer to the light-emitting surface 653S1 than the light-emitting surface 653S2. Transistor 203-2 is located closer to the light-emitting surface 653S2 than the light-emitting surface 653S1.

[0339] A transparent electrode 659d1 is provided on the light-emitting surface 653S1. An opening 658-1 is provided above the light-emitting surface 653S1 and the transparent electrode 659d1. A transparent electrode 659d2 is provided on the light-emitting surface 653S2. An opening 658-2 is provided above the light-emitting surface 653S2 and the transparent electrode 659d2. The second interlayer insulating film 108, the insulating layer 105, the TFT lower layer film 106, and the first interlayer insulating film 156 are not provided in the openings 658-1 and 658-2. The light-emitting surfaces 653S1 and 653S2 are exposed through openings 658-1 and 658-2 formed by removing a portion of each of the second interlayer insulating film 108, the insulating layer 105, the TFT lower layer film 106, and the first interlayer insulating film 156. The openings 658-1 and 658-2 are filled with a surface resin layer 170.

[0340] When viewed from above in the XY plane, the luminescent surfaces 653S1 and 653S2 are squares, rectangles, other polygons, circles, etc. The uppermost shapes of the openings 658-1 and 658-2 can also be squares, rectangles, other polygons, circles, etc. To reduce light loss due to reflection from the walls of the openings 658-1 and 658-2, it is preferable that the openings 658-1 and 658-2 are formed in a conical shape, for example, by widening upwards in area as shown in this example. When viewed from above in the XY plane, the shapes of the luminescent surfaces 653S1 and 653S2 may or may not be similar to the shapes of the uppermost parts of the openings 658-1 and 658-2.

[0341] Wiring layer 110 is disposed on the second interlayer insulating film 108. Wiring layer 110 includes wirings 610s1, 610d1, 610d2, and 610s2. Wirings 610s1 and 610s2 are connected, for example, to... Figure 13 Power line 3 of the circuit shown.

[0342] Vias 111d1, 111s1, 111d2, and 111s2 are provided to penetrate the second interlayer insulating film 108, the insulating layer 105, and the lower TFT film 106. Via 111d1 is located between the p-type doped region of transistor 203-1 and wiring 610d1. Via 111s1 is located between the p-type doped region of transistor 203-1 and wiring 610s1. Via 111d2 is located between the p-type doped region of transistor 203-2 and wiring 610d2. Via 111s2 is located between the p-type doped region of transistor 203-2 and wiring 610s2.

[0343] Wiring 610d1 is connected to the p-type region corresponding to the drain electrode of transistor 203-1 via via 111d1. Wiring 610s1 is connected to the p-type region corresponding to the source electrode of transistor 203-1 via via 111s1. Wiring 610d2 is connected to the region corresponding to the drain electrode of transistor 203-2 via via 111d2. Wiring 610s2 is connected to the region corresponding to the source electrode of transistor 203-2 via via 111s2.

[0344] A transparent electrode 659d1 is disposed on the light-emitting surface 653S1 and also extends across the wiring 610d1. The transparent electrode 659d1 is also disposed between the light-emitting surface 653S1 and the wiring 610d1, electrically connecting the light-emitting surface 653S1 and the wiring 610d1. A transparent electrode 659s1 extends across the wiring 610s1. Therefore, the p-type semiconductor layer 653 is electrically connected to the region corresponding to the drain electrode of the TFT channel 204-1 via the light-emitting surface 653S1, the transparent electrode 659d1, the wiring 610d1, and the via 111d1. The region corresponding to the source electrode of the TFT channel 204-1 is electrically connected to the power line 3 via the via 111s1, the wiring 610s1, and the transparent electrode 659s1.

[0345] A transparent electrode 659d2 is disposed on the light-emitting surface 653S2 and also extends across the wiring 610d2. The transparent electrode 659d2 is also disposed between the light-emitting surface 653S2 and the wiring 610d2, electrically connecting the light-emitting surface 653S2 and the wiring 610d2. A transparent electrode 659s2 extends across the wiring 610s2. Therefore, the p-type semiconductor layer 653 is electrically connected to the region corresponding to the drain electrode of the TFT channel 204-2 via the light-emitting surface 653S2, the transparent electrode 659d2, the wiring 610d2, and the via 111d2. The region corresponding to the source electrode of the TFT channel 204-2 is electrically connected to the power line 3 via the via 111s2, the wiring 610s2, and the transparent electrode 659s2.

[0346] Transistors 203-1 and 203-2 are, for example, driving transistors of adjacent sub-pixels, and are driven sequentially. Holes supplied from one of the two transistors 203-1 and 203-2 are injected into the light-emitting layer 652, and electrons supplied from the connecting plate 630a are injected into the light-emitting layer 652, causing the light-emitting layer 652 to emit light.

[0347] In this embodiment, the drift current flowing in the direction parallel to the XY plane is suppressed by the resistance of the n-type semiconductor layer 651 and the p-type semiconductor layer 653. Therefore, holes injected from the light-emitting surfaces 653S1 and 653S2 and electrons injected from the connecting plate 630a both travel along the stacking direction of the semiconductor layers 650. The outer sides of the light-emitting surfaces 653S1 and 653S2 hardly serve as light sources, so transistors 203-1 and 203-2 can be used to selectively emit light from the multiple light-emitting surfaces 653S1 and 653S2 provided on a semiconductor layer 650.

[0348] Thus, the light source in semiconductor layer 650 is almost entirely determined by the configuration of light-emitting surfaces 653S1 and 653S2.

[0349] The manufacturing method of the image display device according to this embodiment will be described.

[0350] Figures 26A to 28B This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to this embodiment.

[0351] In the manufacturing method of the image display device of this embodiment, the process up to forming a patterned conductive layer on the first surface 102a and then crystallizing the formed conductive layer to form the conductive layer 1130a can be performed in the same manner as in the other embodiments described above. (Explanation follows) Figure 5A After forming the conductive layer 1130a on the first surface 102a in the process, it is applied Figure 26A The process details.

[0352] like Figure 26AAs shown, a semiconductor layer 1150 is formed over the conductive layer 1130a. The semiconductor layer 1150 is formed, for example, by a cryogenic sputtering method.

[0353] like Figure 26B As shown, using dry etching techniques such as RIE, etc., to Figure 26A The semiconductor layer 1150 shown is formed into a semiconductor layer 650 of a desired shape. The desired shape is, for example, a square, rectangle, or other polygons, circles, etc., when viewed from above in the XY plane. Then, a conductive layer 1130a is formed by etching or the like, forming a conductive layer 130 that includes the connecting plate 630a. The outer periphery of the connecting plate 630a is configured such that, when viewed from above in the XY plane, the semiconductor layer 650 is included when projected onto the connecting plate 630a. That is, when viewed from above in the XY plane, the outer periphery of the semiconductor layer 650 is disposed within the outer periphery of the connecting plate 630a.

[0354] like Figure 27A As shown, a first interlayer insulating film 156 is formed by covering the first surface 102a, the conductive layer 130, and the semiconductor layer 650.

[0355] exist Figure 27B As shown, a TFT lower layer 106 is formed over the first interlayer insulating film 156, and TFT channels 204-1 and 204-2 are formed on the TFT lower layer 106. An insulating layer 105 is formed over the TFT lower layer 106 and the TFT channels 204-1 and 204-2. A gate 107-1 is formed on the TFT channel 204-1 via the insulating layer 105. A gate 107-2 is formed on the TFT channel 204-2 via the insulating layer 105. A second interlayer insulating film 108 is formed over the insulating layer 105 and the gates 107-1 and 107-2. The formation methods and materials of the TFT channels 204-1 and 204-2, the insulating layer 105, and the gates 107-1 and 107-2 can be the same as in the other embodiments described above.

[0356] like Figure 28AAs shown, vias 112d1 and 112s1 are formed, penetrating the second interlayer insulating film 108 and the insulating layer 105 to reach the TFT channel 204-1. Vias 112d2 and 112s2 are formed, penetrating the second interlayer insulating film 108 and the insulating layer 105 to reach the TFT channel 204-2. A portion of the second interlayer insulating film 108, a portion of the insulating layer 105, a portion of the TFT lower layer 106, and a portion of the first interlayer insulating film 156 are removed, forming an opening 658-1 reaching the light-emitting surface 653S1. A portion of the second interlayer insulating film 108, a portion of the insulating layer 105, a portion of the TFT lower layer 106, and a portion of the first interlayer insulating film 156 are removed, forming an opening 658-2 reaching the light-emitting surface 653S2.

[0357] like Figure 28B As shown, conductive material is filled into vias 112d1, 112s1, 112d2, and 112s2 to form vias 111d1, 111s1, 111d2, and 111s2. A wiring layer 110, including wirings 610d1, 610s1, 610d2, and 610s2, is formed on the second interlayer insulating film 108. Wirings 610d1, 610s1, 610d2, and 610s2 are respectively connected to vias 111d1, 111s1, 111d2, and 111s2.

[0358] The light-emitting surfaces 653S1 and 653S2 are roughened. Then, a transparent conductive film is formed by covering the wiring layer 110 to form transparent electrodes 659d1, 659s1, 659d2, and 659s2. Transparent electrode 659d1 is formed to cover the light-emitting surface 653S1, electrically connecting the light-emitting surface 653S1 to the wiring 610d1. Transparent electrode 659d2 is formed to cover the light-emitting surface 653S2, electrically connecting the light-emitting surface 653S2 to the wiring 610d2.

[0359] Then, the upper structure, such as the color filter, is formed.

[0360] Thus, a sub-pixel group 620 is formed, which includes a semiconductor layer 650 having two light-emitting surfaces 653S1 and 653S2.

[0361] In this embodiment, two light-emitting surfaces 653S1 and 653S2 are provided on a semiconductor layer 650, but the number of light-emitting surfaces is not limited to two; three or more light-emitting surfaces can also be provided on a semiconductor layer 650. As an example, one or two columns of sub-pixels can also be implemented using a single semiconductor layer 650. Thus, as described later, the recombination current that does not contribute to the light emission of each light-emitting surface can be reduced, and the effect of realizing finer light-emitting elements can be enhanced.

[0362] (Modified Example)

[0363] Figure 29 This is a schematic cross-sectional view of a portion of an image display device illustrating a variation of this embodiment.

[0364] In this modified example, the presence of two p-type semiconductor layers 6653a1 and 6653a2 on the light-emitting layer 652 differs from the sixth embodiment described above. Otherwise, it is the same as the sixth embodiment, with identical reference numerals used for the same constituent elements and detailed descriptions omitted where appropriate.

[0365] like Figure 29 As shown, the image display device of this modified example includes a subpixel group 620a. The subpixel group 620a includes a semiconductor layer 650a. The semiconductor layer 650a includes an n-type semiconductor layer 651, a light-emitting layer 652, and p-type semiconductor layers 6653a1 and 6653a2. The light-emitting layer 652 is stacked on the n-type semiconductor layer 651. The p-type semiconductor layers 6653a1 and 6653a2 are both stacked on the light-emitting layer 652.

[0366] The p-type semiconductor layers 6653a1 and 6653a2 are formed in an island shape on the light-emitting layer 652, and in this example, they are arranged separately along the X-axis direction. A first interlayer insulating film 156 is provided between the p-type semiconductor layers 6653a1 and 6653a2, and the p-type semiconductor layers 6653a1 and 6653a2 are separated by the first interlayer insulating film 156.

[0367] In this example, the p-type semiconductor layers 6653a1 and 6653a2 have approximately the same shape when viewed from above in the XY plane. Their shape is approximately square or rectangular, but can also be other polygonal, circular, etc.

[0368] The p-type semiconductor layer 6653a1 has a light-emitting surface 6653S1. The p-type semiconductor layer 6653a2 has a light-emitting surface 6653S2. The light-emitting surface 6653S1 is exposed through an opening 658-1 formed by removing a portion of each of the first interlayer insulating film 156, the TFT lower layer film 106, the insulating layer 105, and the second interlayer insulating film 108. The exposed light-emitting surface 6653S1 is the surface of the p-type semiconductor layer 6653a1. The light-emitting surface 6653S2 is exposed through an opening 658-2 formed by removing a portion of each of the first interlayer insulating film 156, the TFT lower layer film 106, the insulating layer 105, and the second interlayer insulating film 108. The exposed light-emitting surface 6653S2 is the surface of the p-type semiconductor layer 6653a2.

[0369] The shapes of the light-emitting surfaces 6653S1 and 6653S2 when viewed from above in the XY plane are the same as those in the sixth embodiment, having approximately the same shape, such as a roughly square shape. The shapes of the light-emitting surfaces 6653S1 and 6653S2 are not limited to the square shape of this embodiment; they can also be polygons such as circles, ellipses, or hexagons. The shapes of the light-emitting surfaces 6653S1 and 6653S2 can be similar to the shapes of the openings 658-1 and 658-2, or they can be different shapes.

[0370] A light-transmitting electrode 659d1 is disposed throughout the light-emitting surface 6653S1 and also throughout the wiring 610d1. The light-transmitting electrode 659d1 is located between the light-emitting surface 6653S1 and the wiring 610d1, electrically connecting the two surfaces. A light-transmitting electrode 659d2 is disposed throughout the light-emitting surface 6653S2 and also throughout the wiring 610d2. The light-transmitting electrode 659d2 is located between the light-emitting surface 6653S2 and the wiring 610d2, electrically connecting the two surfaces.

[0371] The manufacturing method of this modified example will be described.

[0372] Figures 30A to 31B This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to this modified example.

[0373] In this variation, it is explained that... Figure 26A The process shown up to the point in the sixth embodiment uses the same process as in the case shown above. Figure 26A The process shown is followed by application Figure 30A The situation regarding subsequent processes.

[0374] like Figure 30A As shown, in this modified example, Figure 26A The semiconductor layer 1150 shown is etched to form a light-emitting layer 652 and an n-type semiconductor layer 651. Further etching is performed to form two p-type semiconductor layers 6653a1 and 6653a2.

[0375] When forming p-type semiconductor layers 6653a1 and 6653a2, deeper etching can be performed. For example, the etching used to form p-type semiconductor layers 6653a1 and 6653a2 can exceed the depth reaching the light-emitting layer 652 and the n-type semiconductor layer 651. Thus, when forming p-type semiconductor layers through deeper etching, it is preferable to... Figure 25 Etching is performed on the outer periphery of the light-emitting surfaces 6653S1 and 6653S2, which is at least 1 μm larger than the outer periphery. By moving the etched location away from the outer periphery of the light-emitting surfaces 6653S1 and 6653S2, recombination current can be suppressed.

[0376] After forming the semiconductor layer 650a, etching is performed. Figure 26A The conductive layer 1130a shown forms a conductive layer 130 including the connecting plate 630a. Alternatively, the conductive layer 1130a and the semiconductor layer 1150 can be etched together to form the connecting plate 630a, and then the semiconductor layer 650 is formed, which is the same as in the other embodiments described above.

[0377] like Figure 30B As shown, a first interlayer insulating film 156 is formed by covering the first surface 102a, the conductive layer 130, and the semiconductor layer 650a.

[0378] like Figure 30C As shown, a TFT lower layer 106 is formed on the first interlayer insulating film 156, and TFT channels 204-1 and 204-2 are formed on the TFT lower layer 106. Furthermore, an insulating layer 105 is formed on the TFT channels 204-1 and 204-2, and gates 107-1 and 107-2 are formed on the insulating layer 105. A second interlayer insulating film 108 is formed covering the insulating layer 105 and the gates 107-1 and 107-2.

[0379] like Figure 31A As shown, through-holes 112d1, 112s1, 112d2, and 112s2 are formed in the same manner as in the sixth embodiment. Opening 658-1 is formed to reach the light-emitting surface 6653S1 by removing a portion of the second interlayer insulating film 108, a portion of the insulating layer 105, a portion of the TFT lower layer film 106, and a portion of the first interlayer insulating film 156. Opening 658-2 is formed to reach the light-emitting surface 6653S2 by removing a portion of the second interlayer insulating film 108, a portion of the insulating layer 105, a portion of the TFT lower layer film 106, and a portion of the first interlayer insulating film 156.

[0380] like Figure 31B As shown, similar to the sixth embodiment, a wiring layer 110 including wirings 610d1, 610s1, 610d2, and 610s2 is formed. Then, a light-transmitting conductive film is formed covering the wiring layer 110. The light-transmitting conductive film is formed into light-transmitting electrodes 659d1, 659s1, 659d2, and 659s2.

[0381] Similar to the sixth embodiment, an upper structure such as a color filter is formed.

[0382] Thus, a sub-pixel group 620a with two light-emitting surfaces 6653S1 and 6653S2 is formed.

[0383] In this modified example, similar to the sixth embodiment, the number of light-emitting surfaces is not limited to two; three or more light-emitting surfaces may be disposed on a semiconductor layer 650a.

[0384] The effects of the image display device in this embodiment will be explained.

[0385] Figure 32 This is a chart illustrating the characteristics of pixel LED elements.

[0386] Figure 32 The vertical axis represents the luminous efficiency [%) of the pixel LED element. The horizontal axis represents the current density flowing through the pixel LED element in relative terms.

[0387] like Figure 32 As shown, in regions where the relative value of current density is less than 1.0, the luminous efficiency of the pixel LED element is approximately constant or monotonically increasing. In regions where the relative value of current density is greater than 1.0, the luminous efficiency monotonically decreases. That is, there exists an appropriate current density for the pixel LED element that maximizes its luminous efficiency.

[0388] By suppressing the current density to a level sufficient to obtain adequate brightness from the light-emitting element, a highly efficient image display device can be expected. However, through... Figure 32 The study shows that at low current densities, the luminous efficiency decreases as the current density decreases.

[0389] As described in the first to fifth embodiments, the light-emitting element is formed by separating the entire semiconductor layer 1150 containing the light-emitting layer using etching or the like. At this time, the interface between the light-emitting layer and the p-type semiconductor layer is exposed at the end of the light-emitting element. Similarly, the interface between the light-emitting layer and the n-type semiconductor layer is exposed at the end.

[0390] In the presence of such an end, electrons and holes recombine at the end. However, this recombination does not contribute to light emission. The recombination at the end occurs almost independently of the current flowing through the light-emitting element. It is believed that the recombination is generated based on the length of the junction surface that contributes to light emission at the end.

[0391] When two cube-shaped light-emitting elements of the same size emit light, since the four sides of each light-emitting element become ends, the two light-emitting elements have a total of 8 ends, and it is possible for them to be recombined at the 8 ends.

[0392] In contrast, in this embodiment, semiconductor layers 650 and 650a have square sides and four ends on the two light-emitting surfaces. However, the injection of electrons and holes in the region between openings 658-1 and 658-2 is relatively low, contributing almost nothing to light emission; therefore, it can be considered that the six ends contribute to light emission. Thus, in this embodiment, by substantially reducing the number of ends of the semiconductor layers, recombination that does not contribute to light emission is reduced. By reducing recombination that does not contribute to light emission, the driving current of each light-emitting surface is reduced.

[0393] In cases where the distance between sub-pixels is shortened for purposes such as achieving high resolution in image display devices, or where the current density is relatively high, the distance between the light-emitting surface 653S1 and the light-emitting surface 653S2 is substantially shortened in the sub-pixel group 620 of the sixth embodiment. In this situation, as in the sixth embodiment, if the p-type semiconductor layer is shared, there is a risk that some holes injected into the driven light-emitting surface may be shunted, resulting in micro-emission from the undriven light-emitting surface. In the modified sub-pixel group 620a, the p-type semiconductor layer is separated into two, with each p-type semiconductor layer having a light-emitting surface, thus reducing the likelihood of micro-emission from the undriven side of the light-emitting surface.

[0394] In this embodiment, the semiconductor layer including the light-emitting layer is crystallized and grown from the n-type semiconductor layer on the interconnect plate 630a, which is preferred from the viewpoint of reducing manufacturing costs. Similar to other embodiments, the stacking order of the n-type semiconductor layer and the p-type semiconductor layer can be replaced by stacking the p-type semiconductor layer, the light-emitting layer, and the n-type semiconductor layer from one side of the interconnect plate 630a, which is the same as described above.

[0395] In this embodiment and its variations, by using the connecting plate 630a for wiring, the semiconductor layer below the semiconductor layers 650, 650a can be electrically connected to the external circuitry independently of the vias of each light-emitting surface. Therefore, it is unnecessary to ensure an area on the connecting plate 630a for via connections, thus enabling a high-density configuration of circuit elements. Furthermore, the lead-out structure of the wiring for connections to external wiring is simplified, thereby expecting an improved yield rate.

[0396] In the image display device of each embodiment described above, specific examples have been given for the sub-pixels and sub-pixel groups. Each specific example is just one instance, and other configuration examples can be obtained by appropriately combining the configuration and process sequence of these embodiments. For example, in the cases of the first to fifth embodiments, through holes may not be used, but a connecting plate may be used for connecting to the power line and ground line, or in the case of the sixth embodiment, through holes may be used to obtain the electrical connection of the light-emitting element.

[0397] (Seventh Implementation)

[0398] The aforementioned image display device, as an image display module with an appropriate number of pixels, can be, for example, a computer monitor, a television, a portable terminal such as a smartphone, or a car navigation system.

[0399] Figure 33 This is a block diagram illustrating the image display device of this embodiment.

[0400] Figure 33 The diagram shows the main components of a computer monitor.

[0401] like Figure 33 As shown, the image display device 701 includes an image display module 702. The image display module 702 is, for example, an image display device configured as described in the first embodiment. The image display module 702 includes: a display area 2 having a plurality of sub-pixels, including sub-pixels 20, arranged thereon; a row selection circuit 5; and a signal voltage output circuit 7.

[0402] The image display device 701 also includes a controller 770. The controller 770 takes in control signals separated and generated by an interface circuit (not shown) as input, and controls the driving of each sub-pixel and the driving sequence for the row selection circuit 5 and the signal voltage output circuit 7.

[0403] (Modified Example)

[0404] The aforementioned image display device, as an image display module with an appropriate number of pixels, can be, for example, a computer monitor, a television, a portable terminal such as a smartphone, or a car navigation system.

[0405] Figure 34 This is a block diagram illustrating a modified example of this embodiment of an image display device.

[0406] Figure 34 The diagram shows the structure of a high-resolution thin-film television.

[0407] like Figure 34 As shown, the image display device 801 includes an image display module 802. The image display module 802 is, for example, the image display device 1 configured as described in the first embodiment. The image display device 801 includes a controller 870 and a frame memory 880. The controller 870 controls the driving sequence of each sub-pixel of the display area 2 based on control signals supplied by the bus 840. The frame memory 880 stores one frame of display data for processing such as smooth dynamic image reproduction.

[0408] The image display device 801 includes an I / O circuit 810. The I / O circuit 810 is in Figure 34The term is simply "I / O". I / O circuit 810 provides interface circuitry for connecting to external terminals, devices, etc. I / O circuit 810 includes, for example, a USB interface for connecting external hard disk devices, an audio interface, etc.

[0409] The image display device 801 includes a receiving unit 820 and a signal processing unit 830. An antenna 822 is connected to the receiving unit 820, which separates and generates necessary signals from the radio waves received by the antenna 822. The signal processing unit 830 includes a DSP (Digital Signal Processor), a CPU (Central Processing Unit), etc., and separates and generates image data, sound data, etc., from the signals separated and generated by the receiving unit 820.

[0410] By configuring the receiving unit 820 and the signal processing unit 830 as high-frequency communication modules such as mobile phone transceivers, WiFi receivers, and GPS receivers, they can also be configured as other image display devices. For example, an image display device with an image display module of appropriate screen size and resolution can be a portable information terminal such as a smartphone or a car navigation system.

[0411] The image display module in this embodiment is not limited to the configuration of the image display device in the first embodiment, and may also be a variation or other embodiment. Furthermore, the image display module in this embodiment and its variations, such as... Figure 11 As shown, it is composed of multiple sub-pixels.

[0412] According to the embodiments described above, a method for manufacturing an image display device and an image display device can be realized that shortens the transfer process of the light-emitting element and improves the yield rate.

[0413] While several embodiments of the present invention have been described above, these embodiments are provided as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, and are included within the scope of the invention and its equivalents as described in the claims. Furthermore, the foregoing embodiments can be combined with each other for implementation.

[0414] Explanation of reference numerals in the attached figures

[0415] 1. Image display device (201, 701, 801); 2. Display area; 3. Power line; 4. Ground line; 5. Row selection circuit (205); 6. Scan line (206); 7. Signal voltage output circuit (207); 8. Signal line (208); 10. Pixel; 20, 20a, 220, 320, 420, 520 sub-pixels; 22, 222 light-emitting elements; 24, 224 selection transistors; 26, 226 driving transistors; 28, 228 capacitors; 101 circuit; 102, 502 substrate; 102a first surface; 103, 203, 203-1, 203-2 transistors; 104, 204, 204-1, 204-2 TFT channel; 105 insulating layer; 107, 107-1, 107-2 gate; 108 second surface; Interlayer insulating film, 110 wiring layer, 110a, 110d, 410d, 410k wiring, 130 conductive layer, 130a, 630a connecting plates, 140 graphene layer, 140a graphene sheet, 150, 250 light-emitting elements, 151S, 253S, 653S1, 653S2, 6653S1, 6653S2 light-emitting surfaces, 153B, 251B, 651B bottom surfaces, 156 first interlayer insulating film, 159d, 159s, 159a, 159k, 659d1, 659d2 light-transmitting electrodes, 161a, 161k, 461a through holes, 180 color filter, 620, 620a sub-pixel groups, 1130, 1130a conductive layers, 1140 graphene layer, 1150 semiconductor layer.

Claims

1. A method for manufacturing an image display device, characterized by, The manufacturing method of the image display device according to claim 1, wherein the step of forming the conductive layer includes steps of: forming a metal layer on the first substrate; and subjecting the metal layer to annealing treatment to form the first portion, in a plan view, an outer periphery of the light emitting element is disposed within an outer periphery of the first portion.

3. The manufacturing method of the image display device according to claim 2, wherein the step of forming the conductive layer includes a step of patterning the metal layer before subjecting the metal layer to annealing treatment.

4. The manufacturing method of the image display device according to claim 1, wherein the first substrate includes a light-transmissive substrate.

5. The manufacturing method of the image display device according to claim 4, wherein the first substrate further includes a second substrate provided on the light-transmissive substrate and having flexibility, the manufacturing method of the image display device further includes a step of removing the light-transmissive substrate after the step of forming the wiring layer.

6. The manufacturing method of the image display device according to claim 1, wherein the manufacturing method of the image display device further includes a step of forming a layer including graphene on the first portion before the step of forming the semiconductor layer.

7. The manufacturing method of the image display device according to claim 1, wherein the manufacturing method of the image display device further includes a step of forming a light-transmissive electrode on the light emitting surface.

8. The manufacturing method of the image display device according to claim 1, wherein the manufacturing method of the image display device further includes a step of forming a through-hole that penetrates the first insulating film and the second insulating film, the through-hole is provided between the first portion and the wiring layer, and electrically connects the first portion and the wiring layer.

9. The manufacturing method of the image display device according to claim 1, wherein the semiconductor layer includes a gallium nitride-based compound semiconductor.

10. The manufacturing method of the image display device according to claim 1, wherein the manufacturing method of the image display device further includes a step of forming a wavelength conversion member on the light emitting element. a substrate having a first surface; a conductive layer provided on the first surface, including a first portion of a single-crystal metal; a light emitting element provided on the first portion, having a bottom surface electrically connected to the first portion, and including a light emitting surface as a surface opposite to the bottom surface; ​ ​ ​ ​ ​ ​ ​ 11. An image display device, characterized by comprising: ​ ​ ​ ​ a first insulating film covering side surfaces of the light emitting element, the first surface, and the conductive layer; a circuit element provided on the first insulating film; a second insulating film covering the first insulating film and the circuit element; a wiring layer provided on the second insulating film; an opening having no first insulating film, no circuit element, and no second insulating film provided in an upper portion of the light emitting surface, a light-transmissive electrode provided on the light emitting surface, the wiring layer being electrically connected to the light emitting surface via the light-transmissive electrode.

12. The image display device according to claim 11, wherein the substrate includes a light-transmissive substrate.

13. The image display device according to claim 11, wherein the substrate includes a substrate having flexibility.

14. The image display device according to claim 11, wherein when viewed in plan, an outer periphery of the light emitting element is disposed inside an outer periphery of the first portion.

15. The image display device according to claim 11, wherein the light emitting element includes a first semiconductor layer of a first conductivity type, a light emitting layer provided on the first semiconductor layer, and a second semiconductor layer of a second conductivity type different from the first conductivity type provided on the light emitting layer, the first semiconductor layer, the light emitting layer, and the second semiconductor layer being stacked in this order from the bottom surface toward the light emitting surface, the first semiconductor layer is provided on the first portion and is electrically connected to the first portion.

16. The image display device according to claim 15, wherein the first conductivity type is p-type and the second conductivity type is n-type.

17. The image display device according to claim 11, further comprising a through-hole penetrating the first insulating film and the second insulating film, provided between the first portion and the wiring layer, and electrically connecting the first portion and the wiring layer.

18. The image display device according to claim 17, wherein the wiring layer includes a first wiring connected to the through-hole and a second wiring connected to a surface including the light emitting surface, the light emitting element is electrically connected to the circuit element via the surface including the light emitting surface and the second wiring.

19. The image display device according to claim 17, wherein the wiring layer includes a third wiring connected to the through-hole and a fourth wiring connected to a surface including the light emitting surface, the light emitting element is electrically connected to the circuit element via the first portion, the through-hole, and the third wiring.

20. The image display device according to claim 11, further comprising a layer including graphene provided between the first portion and the light emitting element.

21. The image display device according to claim 11, wherein the light emitting element includes a gallium nitride-based compound semiconductor.

22. The image display device according to claim 11, further comprising a wavelength conversion member on the light emitting element. provided with: a substrate having a first surface; ​ 23. An image display device, characterized by comprising: ​ ​ a conductive layer provided on the first surface, including a second portion of the single-crystal metal; a semiconductor layer provided on the second portion, having a bottom surface electrically connected to the second portion, and including a plurality of light emitting surfaces on surfaces opposite to the bottom surface; a first insulating film covering side surfaces of the semiconductor layer, the first surface, and the conductive layer; a plurality of transistors provided on the first insulating film; a second insulating film covering the first insulating film and the plurality of transistors; a wiring layer provided on the second insulating film; an opening having no first insulating film, no plurality of transistors, and no second insulating film provided on an upper portion of the light emitting surface, a light-transmissive electrode provided on the light emitting surface, the wiring layer being electrically connected to the light emitting surface via the light-transmissive electrode.

24. The image display device according to claim 23, wherein the semiconductor layer includes a first semiconductor layer, a light emitting layer provided on the first semiconductor layer, and a second semiconductor layer provided on the light emitting layer, the first semiconductor layer, the light emitting layer, and the second semiconductor layer being sequentially stacked from the bottom surface toward the plurality of light emitting surfaces, the second semiconductor layer is separated by the first insulating film.

Images