Lithography method based on thick photoresist application, LED chip and manufacturing method thereof

Abstract

The application provides a photoetching method based on thick photoresist application, an LED chip and a manufacturing method thereof. In the thick photoresist application, the Poisson spot influence of the pattern intersection point is weakened through weak exposure, the SiO2 / metal hard mask process can be cancelled in the subsequent etching process while the pattern distortion is avoided, and the production cost is greatly reduced. Through the cycle operation of low-temperature solidification and development, the uniformity of the thick photoresist and the uniformity of the line width after development are improved. Further, the ICP etching is performed by using an aluminum disc as a bearing disc to make the to-be-etched structure form the preset pattern, the bearing disc made of aluminum material has low cost, high plasticity and high heat conduction performance, and the problems of poor heat conduction performance and low etching rate of the traditional silicon carbide bearing disc can be well solved, so that the production capacity is greatly improved, and the manufacturing cost is effectively reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor manufacturing, and in particular to a photolithography method based on thick photoresist application, an LED chip and a manufacturing method thereof. BACKGROUND

[0002] With the continuous development of semiconductor light emitting technology, the application of LED is changing with each passing day, especially the development of LED in display technology. At the same time, due to the need for high resolution of LED display screen, the pitch of LED chip and the size of chip are becoming smaller and smaller, such as micro light emitting device.

[0003] LED is a kind of semiconductor device which converts electrical energy into light energy. Because it has the advantages of small size, long service life, rich color, low energy consumption and so on, it is widely used in lighting, display, backlight and other fields. As a sub-millimeter light emitting diode, the size of Mini-LED is usually 80-200um. It is a new generation of LED technology, which inherits the characteristics of small pitch LED, such as high efficiency, high reliability, high brightness and fast response time, and has lower power consumption and cost than small pitch LED. However, with the reduction of chip size, the channel ratio is getting higher and higher, which directly affects the light emitting area of the chip. Therefore, it is urgent to prepare high aspect ratio etching channel.

[0004] In the existing manufacturing field, it is usually necessary to apply thick photoresist as an etching mask layer, to carry out sufficient exposure, and to use SiO2 or metal as a hard mask protection layer to avoid the influence on the epitaxial layer caused by the incomplete development of thick photoresist.

[0005] It should be noted that in the prior art, in order to adapt to the needs of special processes, thick photoresist (i.e. thick photoresist) is usually coated for exposure in some photolithography steps. For example, in the process of 0.13um process node, sometimes the thickness of the photoresist to be coated is 6um or more than 6um, while the thickness of the general photoresist is 2um or less than 2um. We define this photoresist which is more than or equal to three times the general thickness value as "thick photoresist".

[0006] It should be noted that when the development rate under the exposure amount tends to the maximum value, the exposure amount is called sufficient / overexposure, and vice versa.

[0007] However, as shown in Figure 1 , Figure 2 The above method still has the following disadvantages:

[0008] 1. By using thick photoresist as a mask layer, the exposure energy required by thick photoresist is extremely high, and the strong diffraction caused thereby will form a serious Poisson spot at the intersection of the channel, and the Poisson spot area will still be etched abnormally after etching.

[0009] 2. The thick photoresist is affected by the depth of the glue layer, and the exposure degree of its upper and lower surfaces is obviously different, which leads to the fact that the photoresist is very inclined in the subsequent development and hardening process due to the reflow channel side wall of the photoresist, so that the channel width is too wide, which seriously affects the light emitting area.

[0010] 3. Using SiO2 or metal as a mask protection layer, the cost is high, and the process is complex.

[0011] Therefore, the present application is designed based on the application of thick photoresist, and the present application is generated. SUMMARY

[0012] The purpose of the present application is to provide a lithography method based on the application of thick photoresist, LED chip and its manufacturing method, so as to improve the etching morphology of high aspect ratio channel.

[0013] In order to achieve the above purpose, the technical scheme adopted by the present application is as follows:

[0014] The lithography method based on the application of thick photoresist comprises the following steps:

[0015] S01, forming a positive photoresist layer on the surface of the structure to be etched;

[0016] S02, forming an exposure area in the positive photoresist layer by weak exposure;

[0017] S03, curing the positive photoresist layer;

[0018] S04, developing the positive photoresist layer to remove the photoresist corresponding to the exposure area;

[0019] S05, repeating steps S03 to S04 to form a positive photoresist layer with uniform preset pattern;

[0020] S06, using the positive photoresist layer with uniform preset pattern as a mask, and etching the structure to be etched to form the preset pattern.

[0021] Preferably, the step S06 comprises: using the positive photoresist layer with uniform preset pattern as a mask, and performing ICP etching on the structure to be etched by taking aluminum disc as a bearing disc.

[0022] Preferably, the step S03 is realized by reducing the ambient temperature to realize the curing of the positive photoresist layer.

[0023] Preferably, multi-step etching is achieved by adjusting at least one of the ICP source power, bias source power, and gas flow rate.

[0024] Preferably, the positive photoresist layer is scanned by plasma before the multi-step etching.

[0025] Preferably, the total number of times steps S03 to S04 are executed is n, where n is a positive integer and n≥2; the ambient temperature corresponding to the nth execution of step S03 is T. n Then T n ≥T n-1 .

[0026] Preferably, T n -T n-1 ≥5℃.

[0027] Preferably, step S04 is performed at room temperature.

[0028] Preferably, the coefficient of thermal expansion of the positive photoresist layer is not higher than 50*10. -6 / ℃.

[0029] Preferably, the positive photoresist layer comprises a plurality of photoresist sub-layers, and the coefficient of thermal expansion of the top surface photoresist sub-layer is not higher than 50*10. -6 / ℃.

[0030] Preferably, the preset pattern includes a channel with an intersection and a depth-to-width ratio greater than 1.

[0031] Preferably, the thickness of the positive photoresist layer is 6–50 μm, including the endpoint values.

[0032] Preferably, the positive photoresist layer comprises EPG-562 photoresist.

[0033] The present invention also provides a method for manufacturing an LED chip, wherein a plurality of LED light-emitting units isolated from each other by means of etching method described above are formed, and the LED light-emitting units are of a horizontal structure. The manufacturing method includes the following steps:

[0034] A01. Provide a substrate;

[0035] A02. Growing an epitaxial stack, wherein the epitaxial stack comprises a first type semiconductor layer, an active layer, and a second type semiconductor layer sequentially stacked on the surface of the substrate;

[0036] A03. By etching the epitaxial stack, a portion of the first type semiconductor layer is exposed, thereby forming a plurality of grooves and mesa, wherein the grooves and mesa are disposed opposite to each other;

[0037] A04. Deeply etching the epitaxial stack to expose the substrate surface to form a plurality of sub-epitaxial stacks arranged in parallel with each other by the channel according to any one of the photolithography methods described above;

[0038] A05. Forming a first electrode deposited on the recess and away from the recess sidewall, and a second electrode deposited on the mesa, and the first electrode and the second electrode are arranged away from each other.

[0039] Preferably, the angle between the channel and the epitaxial stack is 55°-90°, including the end point value.

[0040] The application also provides an LED chip, which is obtained by the manufacturing method described above.

[0041] The application also provides another manufacturing method of an LED chip, which forms a plurality of LED light emitting units isolated from each other by a channel according to any one of the etching methods described above, and the LED light emitting units are vertical structures, and the manufacturing method comprises the following steps:

[0042] B01. Providing a substrate;

[0043] B02. Growing an epitaxial stack, which comprises a first type semiconductor layer, an active layer and a second type semiconductor layer stacked in sequence on the surface of the substrate;

[0044] B03. Deeply etching the epitaxial stack to expose the substrate surface to form a plurality of sub-epitaxial stacks arranged in parallel with each other by the channel according to any one of the photolithography methods described above;

[0045] B04. Providing a conductive substrate, and bonding the epitaxial stack surface and the conductive substrate through a bonding layer to form an integrated body;

[0046] B05. Stripping the substrate to expose the first type semiconductor layer;

[0047] B06. Forming a first electrode on the exposed surface of the first type semiconductor layer.

[0048] Preferably, the angle between the channel and the epitaxial stack is 55°-90°, including the end point value.

[0049] Preferably, the LED chip is obtained by the manufacturing method described above.

[0050] The photoetching method based on thick photoresist application provided by the application is used for etching the to-be-etched structure to form a preset pattern with a cross. Firstly, a positive photoresist layer is formed on the surface of the to-be-etched structure; secondly, the positive photoresist layer is formed with an exposure area under the action of weak exposure; thirdly, the positive photoresist layer is solidified; fourthly, the positive photoresist layer is developed to remove the photoresist corresponding to the exposure area; then, solidification and development are repeatedly performed to form a positive photoresist layer with a uniform preset pattern; finally, the positive photoresist layer with the uniform preset pattern is used as a mask, and the to-be-etched structure is etched to form a preset pattern with a cross. Therefore, when the thick photoresist is applied, the Poisson spot influence of the pattern cross point is weakened by weak exposure, the pattern distortion is avoided, the SiO2 / metal hard mask process can be cancelled in the subsequent etching process, the production cost is greatly reduced, and the uniformity of the thick photoresist and the uniformity of the line width after development are improved through the cyclic operation of low-temperature solidification and development.

[0051] Further, the to-be-etched structure is etched to form the preset pattern by using an aluminum disc as a carrier disc for ICP etching. The aluminum material carrier disc has low cost, high plasticity and high thermal conductivity, and can well solve the problems of poor thermal conductivity and low etching rate of the traditional silicon carbide carrier disc. Therefore, the production capacity is greatly improved, and the manufacturing cost is effectively reduced.

[0052] Then, at least one of the ICP source power, the bias source power and the gas flow rate is adjusted to realize multi-step etching, so as to ensure the uniformity of the ICP etching depth and the uniformity of the line width after etching.

[0053] Further, before the multi-step etching, the positive photoresist layer is scanned by plasma to ensure that the photoresist pattern has no residual film and to improve the flatness of the photoresist.

[0054] Finally, the total number of times of executing steps S03 to S04 is n, where n is a positive integer and n≥2; when the environmental temperature corresponding to the n-th execution of step S03 is T n , T n ≥T n-1 ; by adjusting the solidification temperature for multiple times, the sidewall morphology of the photoresist is well improved while the etching resistance of the photoresist is improved.

[0055] The application further provides an LED chip and a manufacturing method thereof, a plurality of LED light emitting units are formed by the above-mentioned photolithography method and are isolated from each other by channels, regular and flat channels are formed, the risk that the channel and the electrode groove are out of alignment and affect the performance of the LED chip is avoided, meanwhile, the above-mentioned photolithography method can effectively solve the problem that the channel of the LED chip has a large inclination, the channel with a steep side is obtained, so that the size of the channel can be effectively reduced, the effective area and the light emitting area of the LED chip are maximized, and the method is especially suitable for micro-LED chips (such as Mini / Micro-LED, etc.), the yield of the micro-LED chips can be greatly improved, and the manufacturing cost can be effectively reduced. BRIEF DESCRIPTION OF DRAWINGS

[0056] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of the provided drawings.

[0057] Figure 1 A topographic map after the cross-channel formed by deep etching of the LED chip in the prior art;

[0058] Figure 2 An FIB test map after the cross-channel formed by deep etching of the LED chip in the prior art;

[0059] Figure 3 A flow chart of the photolithography method provided in Embodiment 1 of the present application;

[0060] Figure 4 A variation diagram of the developing rate of the EPG-562 photoresist (with a thickness of 10 um) under different exposure amounts provided in Embodiment 1 of the present application;

[0061] Figures 5.1 to 5.7 A structure diagram corresponding to the manufacturing method of the LED chip provided in Embodiment 2 of the present application;

[0062] Figures 6.1 to 6.7 A structure diagram corresponding to the manufacturing method of the LED chip provided in Embodiment 3 of the present application;

[0063] Figure 7 A topographic map of the LED chip provided in Embodiment 2 of the present application after deep etching to form a groove;

[0064] Figure 8 An FIB test map of the LED chip provided in Embodiment 2 of the present application after deep etching to form a groove;

[0065] Explanation of symbols in the drawings:

[0066] L1, L2...Ln: Sub-elongational stack;

[0067] 1. Substrate; 2. Type I semiconductor layer; 3. Active layer; 4. Type II semiconductor layer; 5.1. Groove; 5.2. Mesa; 6. Channel; 7. Transparent conductive layer; 8. Insulating layer; 9. Second electrode; 10. First electrode; 11. Conductive substrate. Detailed Implementation

[0068] To make the content of this invention clearer, the following description, in conjunction with the accompanying drawings, further illustrates the invention. This invention is not limited to this specific embodiment. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without inventive effort are within the scope of protection of this invention.

[0069] Example 1

[0070] like Figure 3 As shown, a photolithography method based on thick photoresist applications includes: providing a structure to be etched, the structure including a semiconductor material layer; and etching the structure to be etched to form a preset pattern with intersections, wherein the etching process includes:

[0071] S01, A positive photoresist layer is formed on the surface of the structure to be etched;

[0072] Based on the above embodiments, in one embodiment of this application, the positive photoresist layer includes EPG-562 photoresist.

[0073] Based on the above embodiments, in one embodiment of this application, the thickness of the positive photoresist layer is 6-50 μm, including the endpoint values.

[0074] Based on the above embodiments, in one embodiment of this application, the coefficient of thermal expansion of the positive photoresist layer is not higher than 50*10. -6 / ℃.

[0075] Based on the above embodiments, in one embodiment of this application, the positive photoresist layer comprises a plurality of photoresist sub-layers, and the coefficient of thermal expansion of the photoresist sub-layer on the top surface is not higher than 50*10. -6 / ℃.

[0076] S02. The positive photoresist layer is exposed by weak exposure.

[0077] It should be noted that when the development rate under the exposure is close to the maximum value, the exposure is called sufficient / overexposure, and vice versa.

[0078] like Figure 4The development rate of the EPG-562 photoresist (10um in thickness) under different exposure amounts is shown in the schematic view, and in an embodiment of the present application, the exposure energy corresponding to the part with a larger slope (i.e. in the dashed line frame) is selected based on the above embodiment.

[0079] Further, based on the application of the EPG-562 photoresist, the exposure energy can be selected as follows: the exposure energy corresponding to each micrometer of the thickness of the photoresist is 14-17 mj / cm 2 The total exposure energy is accumulated according to the total thickness of the photoresist, and the present application does not limit this.

[0080] S03, curing the positive photoresist layer to improve the flatness of the thick photoresist;

[0081] In an embodiment of the present application, the step S03 is implemented by reducing the ambient temperature based on the above embodiment.

[0082] In an embodiment of the present application, the ambient temperature T1 corresponding to the first curing is preferably 20-100℃, and the curing time is 5-100s based on the above embodiment.

[0083] S04, developing the positive photoresist layer to remove the photoresist corresponding to the exposed area;

[0084] In an embodiment of the present application, the step S04 is implemented by the first development with the developing solution at room temperature based on the above embodiment.

[0085] It should be noted that the developing solution includes TMAH developing solution, TBAH developing solution, etc., and the present application does not limit this.

[0086] S05, repeating the steps S03-S04 to form a positive photoresist layer with a uniform preset pattern;

[0087] In an embodiment of the present application, the total number of times of implementing the steps S03-S04 is n, wherein n is a positive integer and n≥2; when the ambient temperature Tn corresponding to the nth implementation of the step S03 is T n , then T n ≥T n-1 .

[0088] In an embodiment of the present application, T n -T n-1 ≥5℃ based on the above embodiment.

[0089] On the basis of the above-mentioned embodiments, in one embodiment of the present application, the environmental temperature T2 corresponding to the second curing is preferably 50-120℃, and the curing time is 10-100s. After the second curing, the second development is performed after cooling to room temperature. It should be noted that the developer used in the second development can be the same as or different from the developer corresponding to the first development, which is not limited in the present application.

[0090] It should be noted that the present embodiment does not limit the specific range of the number n; similarly, the curing temperature corresponding to the third curing, the fourth curing, …, the n-th curing is preferably T n -T n-1 ≥5℃, which is not limited in the present embodiment.

[0091] S06, using the positive photoresist layer with the uniform preset pattern as a mask, etching the structure to be etched to form the preset pattern.

[0092] On the basis of the above-mentioned embodiments, in one embodiment of the present application, the step S06 includes: using the positive photoresist layer with the uniform preset pattern as a mask, performing ICP etching by using an aluminum plate as a bearing plate to make the structure to be etched form the preset pattern.

[0093] On the basis of the above-mentioned embodiments, in one embodiment of the present application, at least one of the ICP source power, the bias source power and the gas flow rate in the ICP etching process is adjusted to realize multi-step etching.

[0094] On the basis of the above-mentioned embodiments, in one embodiment of the present application, before the multi-step etching, the positive photoresist layer is scanned by plasma.

[0095] It should be noted that the present embodiment does not limit the number of etching steps. In one embodiment of the present application, the upper electrode power, the lower electrode power and the gas flow rate in the ICP etching process are adjusted to realize multi-step etching, specifically, the etching steps include 2-step etching:

[0096] Firstly, the positive photoresist layer can be scanned by plasma in an O2 / Ar atmosphere; then, the first-step etching is performed by using the upper electrode power of 800-1800W, the lower electrode power of 100-700W and the gas flow rate of 100-250sccm.

[0097] Secondly, the second-step deep etching is performed by using Cl2 / BCl3 gas, at this time, the upper electrode power is 800-1800W, the lower electrode power is 300-800W, and the gas flow rate is not less than 200sccm.

[0098] In an embodiment of the present application, the preset pattern includes a channel 6 with an intersection and a depth-width ratio greater than 1, based on the above-mentioned embodiments.

[0099] According to the technical solution described above, the photoetching method based on thick photoresist application is provided to etch the to-be-etched structure to form a preset pattern with an intersection. First, a positive photoresist layer is formed on the surface of the to-be-etched structure. Then, the positive photoresist layer is exposed to weak light to form an exposed area. Next, the positive photoresist layer is solidified. Then, the positive photoresist layer is developed to remove the photoresist corresponding to the exposed area. Subsequently, the solidification and development are repeated to form a positive photoresist layer with a uniform preset pattern. Finally, the positive photoresist layer with a uniform preset pattern is used as a mask to etch the to-be-etched structure to form a preset pattern with an intersection. Thus, when thick photoresist is applied, the weak exposure weakens the Poisson spot effect at the intersection of the pattern, which avoids pattern distortion and cancels the SiO2 / metal hard mask process in the subsequent etching process, greatly reducing production costs. The low-temperature solidification and development cycle improves the uniformity of the thick photoresist and the uniformity of the line width after development.

[0100] Further, the ICP etching is performed on the to-be-etched structure to form the preset pattern using an aluminum disc as a carrier disc. The aluminum carrier disc has low cost, high plasticity, and high thermal conductivity, which can effectively solve the problems of poor thermal conductivity and low etching rate of traditional silicon carbide carrier discs. Thus, the production capacity is greatly improved, and the manufacturing cost is effectively reduced.

[0101] Then, at least one of the ICP source power, the bias source power, and the gas flow rate is adjusted to realize multi-step etching, which ensures the uniformity of the ICP etching depth and the uniformity of the line width after etching.

[0102] Further, before the multi-step etching, the positive photoresist layer is scanned by plasma to ensure that the photoresist pattern has no residual film and to improve the flatness of the photoresist.

[0103] Finally, the steps S03 and S04 are repeated n times, where n is a positive integer and n≥2. When the environmental temperature corresponding to the n-th execution of step S03 is T n , then T n >T n-1 . By adjusting the solidification temperature multiple times, the sidewall morphology of the photoresist is improved while the etching resistance of the photoresist is enhanced.

[0104] Embodiment 2

[0105] This invention also provides a method for manufacturing an LED chip, which uses the etching method described in Embodiment 1 to form a plurality of LED light-emitting units that are isolated from each other by channels 6, and the LED light-emitting units are of a horizontal structure. The manufacturing method includes the following steps:

[0106] A01, such as Figure 5.1 As shown, a substrate 1 is provided;

[0107] A02, such as Figure 5.2 As shown, an epitaxial stack is grown, the epitaxial stack comprising a first type semiconductor layer 2, an active layer 3, and a second type semiconductor layer 4 sequentially stacked on the surface of the substrate 1;

[0108] A03, such as Figure 5.3 As shown, by etching the epitaxial stack, a portion of the first type semiconductor layer 2 is exposed, thereby forming a plurality of grooves 5.1 and mesas 5.2, wherein the grooves 5.1 and mesas 5.2 are disposed opposite to each other;

[0109] A04, such as Figure 5.4 As shown, the epitaxial stack is deeply etched to expose the surface of the substrate 1 using any of the above photolithography methods, forming a plurality of sub-epitaxy stacks arranged at intervals through the channels 6;

[0110] For ease of display, Figure 5.4 Only two sub-epitaxial layers (L1, L2) are shown. In the actual manufacturing process of the product, there may be tens of thousands of sub-epitaxial layers, depending on the specific situation. This application does not limit this.

[0111] A05, such as Figure 5.7 As shown, a first electrode 10 and a second electrode 9 are fabricated. The first electrode 10 is deposited in the groove 5.1 and away from the sidewall of the groove 5.1; the second electrode 9 is deposited on the mesa 5.2, and the first electrode 10 and the second electrode 9 are positioned away from each other.

[0112] It should be noted that before fabricating the first electrode 10 and the second electrode 9, as follows: Figure 5.5 As shown, a transparent conductive layer 7 can also be fabricated on the platform 5.2 to serve as a current spreader; then, as... Figure 5.6 As shown, an insulating layer 8 is formed on the sidewall of the epitaxial stack to serve as insulation protection between the electrode and the sidewall and / or a reflector; this embodiment does not limit this.

[0113] Based on the above embodiments, in one embodiment of this application, the angle between the channel 6 and the epitaxial stack is 55° to 90°, including the endpoint value.

[0114] This invention also provides an LED chip, including a horizontal structure LED chip, which is obtained by any of the manufacturing methods described above.

[0115] This invention also provides an LED chip and its fabrication method, wherein a plurality of LED light-emitting units isolated from each other by channels 6 are formed by the photolithography method described in Embodiment 1. Figure 7 , Figure 8 As shown, a regular and flat channel 6 is formed, avoiding the risk of overlap between the trench and the electrode recess 5.1, which would affect the performance of the LED chip. At the same time, the above photolithography method can effectively solve the problem of large tilt angle of the LED chip channel 6, and obtain a channel 6 with steep sides. This can effectively reduce the size of the channel 6 and maximize the effective area and light-emitting area of ​​the LED chip. It is especially suitable for micro LED chips (such as Mini / Micro-LED), which can greatly improve its production capacity and effectively reduce manufacturing costs.

[0116] Example 3

[0117] This invention also provides another method for manufacturing an LED chip, which uses the etching method described in Embodiment 1 to form a plurality of LED light-emitting units that are isolated from each other by channels 6, and the LED light-emitting units have a vertical structure. The manufacturing method includes the following steps:

[0118] B01, such as Figure 6.1 As shown, a substrate 1 is provided;

[0119] B02, such as Figure 6.2 As shown, an epitaxial stack is grown, the epitaxial stack comprising a first type semiconductor layer 2, an active layer 3, and a second type semiconductor layer 4 sequentially stacked on the surface of the substrate 1;

[0120] B03, such as Figure 6.3 As shown, the epitaxial stack is deeply etched to expose the surface of the substrate 1 using any of the above photolithography methods, forming a plurality of sub-epitaxy stacks arranged at intervals through the channels 6;

[0121] For ease of display, Figure 6.3 Only three sub-epipolar layers (L1, L2, L3) are shown. In the actual manufacturing process of the product, there may be tens of thousands of sub-epipolar layers, depending on the specific situation. This application does not limit this.

[0122] B04, such as Figure 6.4 , Figure 6.5 As shown, a conductive substrate 11 is provided, and the epitaxial stack is bonded to the conductive substrate 11 through a bonding layer to form an integral structure.

[0123] B05, such as Figure 6.6As shown, the substrate 1 is peeled off to expose the first type semiconductor layer 2;

[0124] B06, such as Figure 6.7 As shown, a first electrode 10 is formed on the exposed surface of the first type semiconductor layer 2.

[0125] It should be noted that in this embodiment, the conductive substrate 11 can serve as the second electrode 9 of the LED chip and make contact with the outside.

[0126] Based on the above embodiments, in one embodiment of this application, the angle between the channel 6 and the epitaxial stack is 55° to 90°, including the endpoint value.

[0127] Based on the above embodiments, in one embodiment of this application, the LED chip is obtained by any of the manufacturing methods described above.

[0128] This invention also provides an LED chip and its manufacturing method. The photolithography method described in Embodiment 1 forms a plurality of LED light-emitting units isolated from each other by channels 6, creating regular and flat channels 6. This avoids the risk of trenches overlapping with electrodes and affecting LED chip performance. Simultaneously, the photolithography method effectively solves the problem of large tilt angles in the LED chip channels 6, resulting in channels 6 with steep sides. This effectively reduces the size of the channels 6, maximizing the effective area and light-emitting area of ​​the LED chip. This is particularly suitable for micro LED chips (such as Mini / Micro-LED), significantly increasing production capacity and effectively reducing manufacturing costs.

[0129] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0130] It should also be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or apparatus comprising a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or apparatus that includes the aforementioned element.

[0131] The foregoing description of the disclosed embodiments enables a person skilled in the art to make or use the application. Modifications of these embodiments will occur to persons of skill in the art, and that the generic principles defined herein can be applied to other embodiments without departing from the spirit or scope of the application. Therefore, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A photolithography method for thick photoresist applications, characterized in that, include: A structure to be etched is provided, the structure including a semiconductor material layer; and the structure to be etched is etched to form a preset pattern with intersections, wherein the etching process includes the following steps: S01, A positive photoresist layer is formed on the surface of the structure to be etched; S02. The positive photoresist layer is exposed by weak exposure. S03. Curing the positive photoresist layer; S04. Develop the positive photoresist layer to remove the photoresist corresponding to the exposed area; S05. Repeat steps S03 to S04 to form a positive photoresist layer with a uniform preset pattern. S06. Using a positive photoresist layer with a uniform preset pattern as a mask, the structure to be etched is etched to form the preset pattern. Step S06 includes: using a positive photoresist layer with a uniform preset pattern as a mask, and using an aluminum disk as a carrier disk to perform ICP etching to form the preset pattern on the structure to be etched. Step S03 involves lowering the ambient temperature to cure the positive photoresist layer.

2. The photolithography method based on thick photoresist application according to claim 1, characterized in that, Multi-step etching can be achieved by adjusting at least one of the upper electrode power, lower electrode power, and gas flow rate during the ICP etching process.

3. The photolithography method based on thick photoresist application according to claim 1, characterized in that, The number of times steps S03 to S04 are repeated is n, where n is a positive integer and n≥2; the ambient temperature corresponding to the nth execution of step S03 is T. n Then T n >T n-1 .

4. The photolithography method based on thick photoresist application according to claim 3, characterized in that, T n - T n-1 ≥5℃。 5. The photolithography method based on thick photoresist application according to claim 1, characterized in that, Perform step S04 at room temperature.

6. The photolithography method based on thick photoresist application according to claim 1, characterized in that, The coefficient of thermal expansion of the positive photoresist layer is not higher than 50*10. -6 / ℃.

7. The photolithography method based on thick photoresist application according to claim 1, characterized in that, The positive photoresist layer comprises several photoresist sub-layers, and the coefficient of thermal expansion of the top surface photoresist sub-layer is not higher than 50*10. -6 / ℃.

8. The photolithography method based on thick photoresist application according to claim 1, characterized in that, The preset pattern includes channels with intersections and a depth-to-width ratio greater than 1.

9. The photolithography method based on thick photoresist application according to claim 1, characterized in that, The thickness of the positive photoresist layer is 6~50um, including the endpoint values.

10. The photolithography method based on thick photoresist application according to claim 1, characterized in that, The positive photoresist layer includes EPG-562 photoresist.

11. A method for manufacturing an LED chip, characterized in that, A plurality of LED light-emitting units isolated from each other by channels are formed using the photolithography method based on thick photoresist application as described in any one of claims 1 to 10, wherein the LED light-emitting units are of a horizontal structure, and the fabrication method includes the following steps: A01. Provide a substrate; A02. Growing an epitaxial stack, wherein the epitaxial stack comprises a first type semiconductor layer, an active layer, and a second type semiconductor layer sequentially stacked on the surface of the substrate; A03. By etching the epitaxial stack, a portion of the first type semiconductor layer is exposed, thereby forming a plurality of grooves and mesa, wherein the grooves and mesa are disposed opposite to each other; A04. Using the photolithography method according to any one of claims 1 to 10, the epitaxial stack is deeply etched to expose the substrate surface, forming a plurality of sub-epitaxy stacks arranged at intervals between each other through channels; A05. Fabricate a first electrode and a second electrode, wherein the first electrode is deposited in the groove and away from the sidewall of the groove; the second electrode is deposited on the platform, and the first electrode and the second electrode are positioned away from each other.

12. The method for manufacturing an LED chip according to claim 11, characterized in that, The angle between the channel and the epitaxial stack is 55° to 90°, including the endpoint values.

13. An LED chip, comprising a horizontally structured LED chip, characterized in that, The LED chip is obtained by the manufacturing method according to any one of claims 11 to 12.

14. A method for manufacturing an LED chip, characterized in that, A plurality of LED light-emitting units isolated from each other by channels are formed using the photolithography method based on thick photoresist application as described in any one of claims 1 to 10, wherein the LED light-emitting units are of a vertical structure, and the fabrication method includes the following steps: B01. Provide a substrate; B02. Growing an epitaxial stack, wherein the epitaxial stack comprises a first type semiconductor layer, an active layer, and a second type semiconductor layer sequentially stacked on the surface of the substrate; B03. Using the photolithography method according to any one of claims 1 to 10, the epitaxial stack is deeply etched to expose the substrate surface, forming a plurality of sub-epitaxy stacks arranged at intervals between each other through channels; B04. A conductive substrate is provided, and the conductive substrate is bonded to the surface of the epitaxial stack through a bonding layer to form an integral structure; B05. Peel off the substrate to expose the first type of semiconductor layer; B06. A first electrode is formed on the exposed surface of the first type of semiconductor layer.

15. The method for manufacturing an LED chip according to claim 14, characterized in that, The angle between the channel and the epitaxial stack is 55° to 90°, including the endpoint values.

16. An LED chip, comprising a vertically structured LED chip; characterized in that, The LED chip is obtained by the manufacturing method according to any one of claims 14 to 15.

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