Processor BOOT program loading and curing method

Abstract

The present invention discloses a method for loading and solidifying a processor BOOT program, belonging to the technical field of computers, including a processor of the FT-2000 / 4 model, a first QSPI FLASH memory, an FPGA control logic unit, an external debugging board including a second QSPI FLASH memory, and an industrial control computer. The first QSPI Flash memory is configured with a first QSPI interface, the processor is configured with a second QSPI interface, and the second QSPI FLASH memory is configured with a third QSPI interface. This debugging method is based on the QSPI interface and uses the method of an external QSPI FLASH debugging board to load and solidify the BOOT program, greatly reducing the complexity of the debugging environment during its solidification and effectively solving the existing problems.

Description

Technical Field

[0001] The present invention belongs to the technical field of airborne computers, and particularly relates to a method for loading and solidifying a processor BOOT program. Background Art

[0002] The boot program (BOOT) is an important software indispensable in airborne embedded computer products. Its main functions include providing a basic hardware initialization environment for the embedded computer products; moving the software program to the memory; booting the embedded operating system; and providing a basic program burning function for the computer to achieve software solidification and upgrade.

[0003] However, the current solidification and loading of the BOOT program still rely on a relatively complex development environment and expensive debugging equipment. Taking the FT-2000 / 4 processor as an example, it supports a standard debugging interface. The debugging interface signals are shown in Appendix Figure 1 , and the debugging environment is shown in Appendix Figure 2 , which includes an industrial control computer with a TRACE32 software environment and a TRACE32 emulator. The overall debugging structure of the FT-2000 / 4 processor is shown in Appendix Figure 3 , and the user uses the debugging host to connect to the product processor through the emulator and can only perform the solidification and loading of the BOOT program after controlling the processor.

[0004] This process mainly faces four aspects of problems:

[0005] Firstly, the procurement price of the TRACE32 emulator is currently high in the market, which is not conducive to controlling the production cost;

[0006] Secondly, this process relies on a dedicated debugging environment and equipment. The debugging host must install the corresponding debugging software, which is not only time-consuming but also greatly increases the labor cost;

[0007] Thirdly, when upgrading the delivered products, due to the complex external field environment, software upgrade errors often occur (during the debugging process, there are many erase operations, and it is easy to accidentally erase the BOOT), resulting in the situation of erasing the solidified BOOT program. Therefore, it is necessary to carry a variety of debugging equipment and a variety of connection signal lines to prevent the above situation from occurring, resulting in low work efficiency, high error rate and complex process for technical personnel to work in the complex and changeable external field environment;

[0008] Fourthly, when solidifying the BOOT program for the first time, when the initialization data in the product FLASH is abnormal, it may cause the processor to enter a disordered state, thus affecting the use of the emulator and causing problems in the operation of burning the BOOT using the emulator.

[0009] In summary, when using traditional methods to debug products, since the BOOT solidification method in the product's FLASH memory is very troublesome, and the recovery of the product after accidentally erasing the BOOT is troublesome and costly, the debugging efficiency of batch products is relatively low. Summary of the Invention

[0010] In view of this, the present invention provides a method for loading and solidifying the processor BOOT program, which at least partially solves the technical problem in the prior art that during the debugging process, due to a large number of erasing and writing operations, when accidentally erasing the BOOT in the product, the method of recovering the product is troublesome and costly, resulting in a reduction in debugging efficiency.

[0011] A method for loading and solidifying the processor BOOT program is applicable to the debugging of product loading and solidification. The product includes a processor of the FT-2000 / 4 model, a first QSPI FLASH memory, and an FPGA control logic unit. The first QSPI Flash memory can be installed with BOOT and is configured with a first QSPI interface. The processor is configured with a second QSPI interface. The method includes:

[0012] A debugging adapter board is configured. The debugging adapter board includes a second QSPI FLASH memory and a switch for chip selection discrete quantity input. The second QSPI FLASH memory specifies a storage area to solidify the BOOT software, and the BOOT software includes the function of online programming and is provided with a third QSPI interface. The first QSPI interface, the second QSPI interface, and the third QSPI interface all include a protocol chip selection signal, a data line signal, and a clock signal. The chip selection signal of the second QSPI interface is respectively connected to the signals of the first QSPI interface and the third QSPI interface through the switch in a corresponding manner;

[0013] The chip selection signal of the second QSPI interface of the product is introduced into the FPGA control logic unit. The FPGA control logic unit obtains the state of the switch in real time. When the switch is in the off state, the chip selection signal of the second QSPI interface points to the chip selection signal of the first QSPI interface in the first QSPI FLASH memory;

[0014] When the switch is in the on state, the chip selection signal of the second QSPI interface points to the chip selection signal of the third QSPI interface in the second QSPI FLASH memory, realizing that when the BOOT of the product is accidentally erased or when the product does not install BOOT, the BOOT program can be solidified in the first QSPI FLASH memory through the debugging adapter board.

[0015] The technical beneficial effects of the present invention:

[0016] The standard debugging interface for BOOT program solidification requires a complex and expensive debugging environment and debugging equipment support, which causes inconvenience in mass production and field upgrades. The standard debugging interface depends on the product FLASH data status, resulting in the inability to perform BOOT solidification operations when the FLASH data is abnormal. By supporting the debugging method of an external FLASH debugging board, the product debugging method is more diverse, the BOOT program solidification has lower requirements on the debugging environment and product status, and is more operable and portable. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 It is a JTAG debugging interface signal table in the prior art;

[0019] Figure 2 It is a TRACE32 simulator debugging environment support table in the prior art;

[0020] Figure 3 It is the structural diagram of the debugging method based on TRACE32 simulator;

[0021] Figure 4 It is a structural diagram of the debugging method of the present invention. DETAILED DESCRIPTION

[0022] The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0023] The following describes the embodiments of the present disclosure through specific examples, and those skilled in the art can easily understand other advantages and effects of the present disclosure from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. The present disclosure can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present disclosure. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present disclosure.

[0024] It should be noted that the following description relates to various aspects of embodiments within the scope of the appended claims. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on this disclosure, those skilled in the art should understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of the aspects set forth herein can be used to implement a device and / or practice a method. Additionally, this device and / or method can be implemented using other structures and / or functionality in addition to one or more of the aspects set forth herein.

[0025] An example of the embodiment is FT-2000 / 4. At the current stage, FT-2000 / 4 adopts a standard debugging interface. However, when the program is first solidified and started, there are phenomena such as unsuccessful access to FLASH, and operation problems such as inconvenience in field and mass production debugging. FT-2000 / 4 supports the standard JTAG debugging interface. Users can connect the debugging host to the CPU core through a debugging emulator, and then perform the corresponding BOOT program solidification operation after controlling the core. However, this method has the following problems: First, during software upgrade or software debugging in the field, there is often a risk of damaging the startup software BOOT. However, using the JTAG debugging interface requires a complex and expensive debugging environment support, resulting in inconvenient use; Second, such a complex debugging environment also brings great inconvenience to the mass production of products. Third, when the BOOT program is first solidified using the standard JTAG debugging interface, if the initialization data in the product FLASH is abnormal, the processor may enter a chaotic state, thus affecting the use of the emulator and causing the operation of burning the BOOT using the emulator to be unsuccessful. In view of the above problems, the present invention proposes a method for loading and solidifying the BOOT program of the FT-2000 / 4 processor. This debugging method is based on the QSPI interface and uses an external QSPI FLASH debugging board, which greatly reduces the complexity of the debugging environment during BOOT program solidification and effectively solves the existing problems.

[0026] The method for loading and solidifying the BOOT program of the processor of the present invention, as Figure 3As shown, it is applicable to the debugging of product loading and curing. The product includes a processor of the FT-2000 / 4 model, a first QSPI FLASH memory, and an FPGA control logic unit. The first QSPI Flash memory can be installed with BOOT and configured with a first QSPI interface. The processor is configured with a second QSPI interface. Being installable with BOOT and configured with a first QSPI interface means that the first QSPI Flash memory is installed with BOOT and configured with a first QSPI interface, or, the first QSPI Flash memory is not installed with BOOT but is provided with a first QSPI interface. The method includes,

[0027] Configuring a debugging adapter board. The debugging adapter board includes a second QSPI FLASH memory and a switch for chip select discrete input. The second QSPI FLASH memory specifies a storage area to solidify the BOOT software, and the BOOT software includes an in-circuit programming function and is provided with a third QSPI interface. The first QSPI interface, the second QSPI interface, and the third QSPI interface all include a protocol chip select signal, a data line signal, and a clock signal. The chip select signal of the second QSPI interface is respectively connected to the signals of the first QSPI interface and the third QSPI interface through the switch;

[0028] Introducing the chip select signal of the second QSPI interface of the product into the FPGA control logic unit. The FPGA control logic unit obtains the status of the switch in real time. When the switch is in the off state, the chip select signal of the second QSPI interface points to the chip select signal of the first QSPI interface in the first QSPI FLASH memory;

[0029] When the switch is in the on state, the chip select signal of the second QSPI interface points to the chip select signal of the third QSPI interface in the second QSPI FLASH memory, realizing that when the BOOT of the product is accidentally erased or when the product does not install BOOT, the BOOT program can be solidified in the first QSPI FLASH memory through the debugging adapter board.

[0030] When the first QSPI Flash memory of the product is not installed with BOOT but is provided with a first QSPI interface, that is, it cannot normally start and execute the software program. The debugger directly triggers the switch action. When the FPGA control logic unit receives the action signal of the switch, it instructs the QSPI_CS0 chip select signal of the second QSPI interface to be connected to the QSPI_CS0 of the third QSPI interface, and the BOOT program can be quickly solidified in the first QSPI Flash. Based on this, the product can be debugged or the product function can be normally executed without relying on additional equipment;

[0031] When the first QSPI Flash memory of the product is installed with BOOT and set with the first QSPI interface, during debugging, when it is found that the BOOT in the first QSPI Flash memory is abnormal or accidentally erased, the debugger directly triggers the switch action. When the FPGA control logic unit receives the action signal of the switch, it instructs the QSPI_CS0 chip select signal of the second QSPI interface to be connected to the QSPI_CS0 of the third QSPI interface. Without the assistance of an emulator, the product can be quickly restored through the debug adapter board, improving the debugging efficiency of the product.

[0032] As a specific implementation provided in this case, an industrial control computer is also configured. The industrial control computer has a serial port transmission function, and the industrial control computer stores the binary file of the BOOT program. The binary file stored in it is stored in the first FLASH through the industrial control computer. The BOOT software in the second QSPI Flash memory includes a program relocation function and a serial port programming function, that is, when the software runs, it first loads the binary program stored in the QSPI FLASH into the memory, and then through the serial port programming method, the program and file can be solidified into the FLASH selected by the second QSPI interface chip.

[0033] As a specific implementation provided in this case, as Figure 4 shown, the specific settings of the QSPI interface are as follows:

[0034] The first QSPI interface includes the chip select signal of QSPI_CS0_FLASH, the data line (data line 0) of QSPI_Io0_FLASH, QSPI_Io1_FLASH (data line 1), and QSPI_CLK_FLASH (clock signal);

[0035] The second QSPI interface includes QSPI_CS0 (chip select signal), QSPI_Io0 (data line 0), QSPI_Io1 (data line 1), and QSPI_CLK (clock signal);

[0036] The third QSPI interface QSPI_CS0_JTAG (chip select signal), QSPI_Io0_JTAG (data line 0), QSPI_Io1_JTAG (data line 0), and QSPI_CLK_JTAG (clock signal), where:

[0037] The QSPI_Io0, QSPI_Io1, and QSPI_CLK signals of the second QSPI interface are respectively connected to the QSPI_Io0_FLASH, QSPI_Io1_FLASH, and QSPI_CLK_FLASH signals of the first QSPI interface and the protocol chip select signals of the QSPI_Io0_JTAG, QSPI_Io1_JTAG, and QSPI_CLK_JTAG of the third QSPI interface. QSPI_CS0 is connected to QSPI_CS0_FLASH or QSPI_CS0_JTAG through a switch.

[0038] When the switch is triggered by the debugger, the FPGA control logic unit controls the connection of the QSPI_CS0 chip select signal to QSPI_CS0_JTAG. When the switch is triggered again, the FPGA control logic unit controls the connection of the QSPI_CS0 chip select signal to QSPI_CS0_FLASH.

[0039] Furthermore, a QSPI FLASH memory and an output discrete quantity are integrated on the debugging adapter board. Among them: the BOOT software is solidified in the FLASH, and the QSPI interface and discrete quantity of the FLASH are externally connected to the debugging board connector; the third QSPI interface of the debugging adapter board is used to receive the QSPI_CS0_JTAG signal and the control information sent by the QSPI_Io0_JTAG signal and the QSPI_Io1_JTAG signal.

[0040] As a specific implementation provided in this case, after power-on, select the QSPI_CS0 signal chip select of the second QSPI interface to point to the second QSPI FLASH in the debugging board, load the BOOT program into the memory of the product to be debugged, select the QSPI_CS0 chip select of the second QSPI interface to point to the first QSPI FLASH in the product, and use a PC with a serial port function to perform software solidification or debugging work. Specifically,

[0041] Step 1: Before debugging, by changing the value of the external discrete quantity, control the switch to turn on or off, and select the second QSPI FLASH on the debugging board as the starting FLASH memory.

[0042] Step 2: After power-on, utilize the QSPI startup mechanism of the processor, that is, after power-on, first execute the program instructions stored in the QSPI FLASH memory selected by the QSPI interface of the processor. Monitor the external discrete quantity through the control logic unit to control the pointing of QSPI_CS0. At this time, if it is detected that the external discrete quantity switch is on, QSPI_CS0 selects the QSPI_CS0_JTAG signal on the debugging board.

[0043] Step 3: Receive the chip select information of QSPI_CS0 sent by the QSPI_CS0_JTAG signal through the QSPI interface on the debug board, start the second QSPI FLASH on the debug board, and load the BOOT software into the memory of the product to be debugged.

[0044] As a specific implementation provided in this case, select that the chip select of QSPI_CS0 points to the FLASH in the product, and use a PC with a serial port function to perform software solidification or debugging work, which specifically includes the following steps:

[0045] Step 1: Change the value of the external discrete quantity, and select the first QSPI FLASH on the product to be debugged as the starting FLASH memory.

[0046] Step 2: Monitor the external discrete quantity through the control logic to control the pointing of QSPI_CS0. When it is detected that the external discrete quantity switch is off, select the QSPI_CS0_FLASH signal with QSPI_CS0.

[0047] Step 3: Use an industrial control computer with a serial port function to solidify the BOOT program in the first QSPI FLASH to achieve BOOT software upgrade or the first solidification of the BOOT software.

[0048] As mentioned above, the above are only specific implementation manners of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present disclosure should be covered by the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A method for loading and solidifying a processor BOOT program, which is applicable to the debugging of loading and solidifying of a product. The product includes a processor of the FT-2000 / 4 model, a first QSPI FLASH memory, and an FPGA control logic unit. The first QSPI Flash memory can be installed with a BOOT and is configured with a first QSPI interface, and the processor is configured with a second QSPI interface. It is characterized in that, The method includes configuring a debug adapter board, which includes a second QSPI FLASH memory and a switch for chip selection discrete input. The second QSPI FLASH memory designates a storage area to solidify the BOOT software, and the BOOT software includes the function of online programming, and is provided with a third QSPI interface. The first QSPI interface, the second QSPI interface, and the third QSPI interface all include a protocol chip selection signal, a data line signal, and a clock signal. The chip selection signal of the second QSPI interface is respectively connected to the signals of the first QSPI interface and the third QSPI interface through the switch in a corresponding manner; The chip selection signal of the second QSPI interface of the product is introduced into the FPGA control logic unit. The FPGA control logic unit obtains the state of the switch in real time. When the switch is in the off state, the chip selection signal of the second QSPI interface points to the chip selection signal of the first QSPI interface in the first QSPI FLASH memory; When the switch is in the on state, the chip selection signal of the second QSPI interface points to the chip selection signal of the third QSPI interface in the second QSPI FLASH memory, realizing that when the BOOT of the product is accidentally erased or when the product does not have the BOOT installed, the BOOT program can be solidified in the first QSPI FLASH memory through the debug adapter board; The first QSPI interface includes the chip selection signal of QSPI_CS0_FLASH, QSPI_Io0_FLASH, QSPI_Io1_FLASH, and QSPI_CLK_FLASH; the second QSPI interface includes QSPI_CS0, QSPI_Io0, QSPI_Io1, and QSPI_CLK; the third QSPI interface includes QSPI_CS0_JTAG, QSPI_Io0_JTAG, QSPI_Io1_JTAG, and QSPI_CLK_JTAG, where, The QSPI_Io0, QSPI_Io1, and QSPI_CLK signals of the second QSPI interface are respectively connected to the QSPI_Io0_FLASH, QSPI_Io1_FLASH, and QSPI_CLK_FLASH signals of the first QSPI interface and the protocol chip selection signals of QSPI_Io0_JTAG, QSPI_Io1_JTAG, and QSPI_CLK_JTAG of the third QSPI interface. The QSPI_CS0 is connected to the QSPI_CS0_FLASH or QSPI_CS0_JTAG through the switch; When the switch is triggered by the debugger, the FPGA control logic unit controls the connection between the QSPI_CS0_FLASH chip selection signal and the QSPI_CS0_JTAG. When the switch is triggered again, the FPGA control logic unit controls the connection between the QSPI_CS0 chip selection signal and the QSPI_CS0_FLASH.

2. The method according to claim 1, wherein An industrial control computer is also configured. The industrial control computer has a serial port transmission function, and a binary file of the BOOT program is stored in the control computer. The binary file stored in it is stored in the first FLASH through the industrial control computer.

3. The method according to claim 2, wherein After power-on, select the QSPI_CS0 signal of the second QSPI interface to select and point to the second QSPI FLASH in the debug board, and load the BOOT program into the memory of the product to be debugged. Select the QSPI_CS0 chip select of the second QSPI interface to point to the first QSPI FLASH in the product, and use a PC with a serial port function to perform software solidification or debugging work.

4. The method according to claim 3, wherein The BOOT software in the second QSPI FLASH memory includes a program relocation function and a serial port programming function. That is, when the software runs, it first loads the binary program stored in the QSPI FLASH into the memory, and then the program and files can be solidified into the FLASH selected by the second QSPI interface through serial port programming.

5. The method according to claim 4, characterized in that, The debug adapter board integrates a QSPI FLASH memory and an output discrete quantity, where: The BOOT software is solidified in this FLASH, and the QSPI interface and discrete quantity of this FLASH are externally connected to the debug board connector; the third QSPI interface of the debug adapter board is used to receive the control information sent by the QSPI_CS0_JTAG signal, the QSPI_Io0_JTAG signal, and the QSPI_Io1_JTAG signal.

6. The method according to claim 5, wherein After power-on, select the QSPI_CS0 signal of the second QSPI interface to select and point to the FLASH in the debug board, and loading the BOOT program into the memory of the product to be debugged includes the following steps: Step 7.1, before debugging, by changing the value of the external discrete quantity, control the switch to be on or off, and select the starting FLASH memory as the second QSPI FLASH on the debug board. Step 7.2, after power-on, use the QSPI startup mechanism of the processor, that is, after power-on, first execute the program instructions stored in the QSPI FLASH memory selected by the QSPI interface of the processor. Monitor the external discrete quantity through the control logic unit to control the pointing of QSPI_CS0. At this time, if it is detected that the external discrete quantity switch is on, QSPI_CS0 selects the QSPI_CS0_JTAG signal on the debug board. Step 7.3, receive the QSPI_CS0 chip select information sent by the QSPI_CS0_JTAG signal through the QSPI interface on the debug board, start the second QSPI FLASH on the debug board, and load the BOOT software into the memory of the product to be debugged.

7. The method according to claim 6, wherein Select the QSPI_CS0 chip select to point to the FLASH in the product, and use a PC with a serial port function to perform software solidification or debugging work, which specifically includes the following steps: Step 8.1, change the value of the external discrete quantity, and select the starting FLASH memory as the first QSPI FLASH on the product to be debugged. Step 8.2, monitor the external discrete quantity through the control logic to control the pointing of QSPI_CS0. When the external discrete quantity switch is detected to be off at this time, select the QSPI_CS0_FLASH signal with QSPI_CS0. Step 8.3, use an industrial control computer with a serial port function to solidify the BOOT program in the first QSPI FLASH to achieve BOOT software upgrade or the first solidification of the BOOT software.

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