A digital-analog heterogeneous redundancy start mode configuration system and method

Abstract

A digital-analog hybrid redundant start mode configuration system and method, the system comprises a digital start mode capturer configured to capture digital start mode configuration information from an input digital signal; an analog-digital converter configured to measure an input analog signal, convert the analog signal into a digital signal, and obtain an analog signal sample value; an analog start mode capturer configured to capture analog start mode configuration information from the analog signal sample value; a start mode verification mode detector configured to determine a start mode verification mode according to the analog signal sample value; and a start mode verifier configured to verify the digital start mode configuration information and the analog start mode configuration information according to the start mode verification mode. The digital-analog hybrid redundant start mode configuration system and method improve the functional safety and fault diagnosis rate of system start mode configuration, and users can adjust the start mode according to the functional safety level of demand or use scenario.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a digital-analog heterogeneous redundancy startup mode configuration system and method for highly reliable multi-core heterogeneous system-on-chips (SoCs) and microcontrollers (MCUs). Background Technology

[0002] During system startup, processors typically need to determine the startup mode based on startup mode configuration pins. Traditional startup mode configuration methods fall into two main categories: 1) using a set of digital input / output (DIO) pins; and 2) using one or more analog signal pins (AIO) to configure the startup mode by adjusting the amplitude of input voltage and current signals.

[0003] To detect failures in the startup mode selection circuit, parity checking or ECC checking is typically used to protect the startup mode selection. Using digital signal input requires adding an extra input signal as verification information for startup mode configuration; while using analog signal input requires increasing the precision of the analog signal to represent more verification information.

[0004] Neither purely digital nor analog startup methods can effectively avoid common-cause failures in the startup mode detection circuit. For example, if the analog-to-digital conversion circuit fails when using analog startup mode selection, the startup mode selection information and startup mode verification information will be incorrectly sampled, thereby reducing the fault diagnosis rate of the startup mode sampling circuit. Summary of the Invention

[0005] To address the shortcomings of existing technologies, the present invention aims to provide a heterogeneous redundancy startup mode configuration system and method that supports both digital signal and analog startup mode configuration. While ensuring the functional safety of the system startup mode configuration, the startup mode can be adjusted according to the functional safety level requirements of the usage scenario.

[0006] To achieve the above objectives, the present invention provides a heterogeneous redundancy startup mode configuration system for analog and digital systems, comprising:

[0007] A digital start mode capturer is used to capture digital start mode configuration information from input digital signals;

[0008] An analog-to-digital converter is used to measure an input analog signal, convert the analog signal into a digital signal, and obtain the analog signal sample value.

[0009] A simulated startup mode capturer is used to capture simulated startup mode configuration information from the sampled values ​​of the simulated signal;

[0010] A startup mode verification detector is used to determine the startup mode verification method based on the sampled values ​​of the analog signal.

[0011] A startup mode verifier is used to verify the digital startup mode configuration information and the analog startup mode configuration information according to the startup mode verification method.

[0012] Furthermore, it also includes an input selection module for setting the input startup mode.

[0013] Furthermore, the digital boot mode capturer captures and latches the digital boot mode configuration information after the processor is initially powered on.

[0014] Furthermore, the analog-to-digital converter may be one or more.

[0015] Furthermore, the analog startup mode capture device is used to activate the analog-to-digital converter to measure the input analog signal; and to convert the sampled value of the analog signal output by the analog-to-digital converter into analog startup configuration information.

[0016] Furthermore, the analog startup mode capture device extracts a set number of bits from the high bits of the analog signal sample value output by the analog-to-digital converter as analog startup configuration information.

[0017] Furthermore, the startup mode verification detector selects the high-order bits of the analog signal sample value output by the analog-to-digital converter as the selection bits according to a set number of bits, and uses the remaining bits as startup mode selection information.

[0018] Furthermore, the startup mode verification method includes: not verifying the startup mode, performing parity verification on the startup mode, performing 1-bit error verification on the startup mode and enabling 1-bit error correction function, and performing 2-bit error verification on the startup mode and enabling 1-bit error correction function.

[0019] Furthermore, the startup mode verifier selects either digital startup mode configuration information or analog startup mode configuration information as the verification data for the startup mode, based on the startup mode verification method, and verifies the other startup mode configuration information.

[0020] To achieve the above objectives, the present invention also provides a method for configuring a heterogeneous digital-analog startup mode, employing the heterogeneous digital-analog startup mode configuration system described above, comprising:

[0021] Select the startup mode;

[0022] Capture and lock digital boot mode configuration information;

[0023] Measure the input analog signal and capture the analog startup mode configuration information from the sampled analog signal values;

[0024] The startup mode verification method is determined based on the sampled values ​​of the analog signal.

[0025] According to the boot mode verification method, verify the digital boot mode configuration information and the analog boot mode configuration information.

[0026] Furthermore, the step of capturing analog startup mode configuration information from analog signal sample values ​​further includes:

[0027] A set number of bits are extracted from the high bits of the analog signal sampled value output by the analog-to-digital converter as analog startup configuration information.

[0028] Furthermore, the step of determining the verification method of the startup mode based on the sampled values ​​of the analog signal further includes:

[0029] The high-order bits of the analog signal sample value output by the analog-to-digital converter are selected as the selection bits according to the set number of bits, and the remaining bits are used as start-up mode selection information.

[0030] Furthermore, the startup mode verification method includes: not verifying the startup mode, performing parity verification on the startup mode, performing 1-bit error verification on the startup mode and enabling 1-bit error correction function, and performing 2-bit error verification on the startup mode and enabling 1-bit error correction function.

[0031] Furthermore, the step of verifying the digital startup mode configuration information and the analog startup mode configuration information according to the startup mode verification method further includes: selecting either the digital startup mode configuration information or the analog startup mode configuration information as the verification data for the startup mode according to the startup mode verification method, and verifying the other startup mode configuration information.

[0032] To achieve the above objectives, the present invention also provides a chip, including the analog-digital heterogeneous redundancy boot mode configuration system described above.

[0033] To achieve the above objectives, the present invention also provides an electronic device, including a memory and a processor, wherein the memory stores computer instructions, and the processor employs the chip described above, wherein the processor is configured to run the instructions to perform the steps of the analog-digital heterogeneous startup mode configuration method described above.

[0034] To achieve the above objectives, the present invention also provides a computer-readable storage medium storing computer instructions thereon, which, when executed, perform the steps of the analog-digital heterogeneous redundancy startup mode configuration method as described above.

[0035] The digital-analog heterogeneous redundancy startup mode configuration system and method provided by this invention have the following technical advantages compared with the prior art:

[0036] It supports both digital signal and analog boot mode configurations, verifies digital boot mode configuration information and analog boot mode configuration information, and improves the functional security of system boot mode configuration.

[0037] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. Attached Figure Description

[0038] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used together with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings:

[0039] Figure 1 A schematic diagram of the structure of an embodiment of the digital-analog heterogeneous redundancy startup mode configuration system according to the present invention;

[0040] Figure 2 A schematic diagram of another embodiment of the digital-analog heterogeneous redundancy startup mode configuration system according to the present invention;

[0041] Figure 3 A flowchart of the digital-analog heterogeneous redundancy startup mode configuration method according to the present invention;

[0042] Figure 4 This is a schematic diagram of the electronic device structure according to the present invention. Detailed Implementation

[0043] Embodiments of this application will now be described in more detail with reference to the accompanying drawings. While some embodiments of this application are shown in the drawings, it should be understood that this application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this application. It should be understood that the drawings and embodiments of this application are for illustrative purposes only and are not intended to limit the scope of protection of this application.

[0044] It should be understood that the steps described in the method embodiments of this application may be performed in different orders and / or in parallel. Furthermore, the method embodiments may include additional steps and / or omit the steps shown. The scope of this application is not limited in this respect.

[0045] The term "comprising" and its variations as used herein are open-ended inclusion, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Definitions of other terms will be given in the description below.

[0046] It should be noted that the terms "one" and "multiple" used in this application are illustrative rather than restrictive, and those skilled in the art should understand that, unless explicitly stated otherwise in the context, they should be understood as "one or more". "Multiple" should be understood as two or more.

[0047] In this embodiment of the invention: heterogeneous redundancy. This refers to a redundant system composed of two devices with different performance, models, functions, and principles, one of which is in operation and the other in standby mode. Generally, in a redundant system, the device that is constantly in operation has better performance and more complete functions, while the device that is constantly in standby mode often only has partial functions, such as sequential control functions. Therefore, this type of redundancy structure is also called incomplete redundancy.

[0048] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0049] Example 1

[0050] Figure 1 A schematic diagram of a configuration system for heterogeneous startup modes according to an embodiment of the present invention is shown below. Figure 1 As shown, the heterogeneous redundancy startup mode configuration system for analog and digital systems in this embodiment includes,

[0051] The digital boot mode capturer 10 captures and latches digital boot mode configuration information from digital input pins (DIO_0 to DIO_N) at a specific moment during processor startup (generally after the processor has initially powered on) for use by the boot mode verifier 50.

[0052] The analog-to-digital converter (ADC) 20 accepts instructions from the analog startup mode capture unit 30 to measure the analog signal input to the analog input pin (AIO_0), and sends the sampled analog signal value to the analog startup mode capture unit 30 and the startup mode verification detector 40.

[0053] The analog startup mode capture device 30 starts the analog-to-digital converter 20 during the processor startup phase to measure the analog signal input to IO_0, and converts the sampled value of the analog signal output by the analog-to-digital converter 20 into the corresponding analog startup mode configuration information for use by the startup mode verifier 50.

[0054] The startup mode verification detector 40 is used to analyze the sampled values ​​of the analog signal output by the analog-to-digital converter 20, and selects the corresponding startup mode verification method based on the analysis results and sends it to the startup mode verifier 50.

[0055] In this embodiment of the invention, the startup mode verification detector 40 uses the high-bit information of the analog signal sample value as the selection bit and the remaining bits as startup mode selection information.

[0056] The startup mode verifier 50 verifies the digital startup mode configuration information of the digital startup mode capture device 10 and the analog startup mode configuration information of the analog startup mode capture device 30 according to the verification method output by the startup mode verification method detector 40, and then outputs the final startup mode or verification error information.

[0057] In this embodiment of the invention, the startup mode verifier 50 selects either analog or digital startup mode information as the startup mode information based on the startup mode verification method detected by the startup mode verification method detector 40. Simultaneously, it uses the other startup mode information as verification data for verification calculation. After verification, the final startup mode is output. If an error is detected, a verification error is reported. In this embodiment, the startup mode verifier 50 selects either digital startup mode configuration information or analog startup mode configuration information as the startup mode verification data based on the startup mode verification method sent by the startup mode verification method detector 40, while verifying the other startup mode configuration information. This allows for mutual verification between the digital and analog startup mode configuration information, improving the functional security of the system's startup mode configuration.

[0058] Input selection module 60 is used to set the input start mode.

[0059] In this embodiment of the invention, the input selection module 60 can select analog startup mode input, digital startup mode input, or both analog startup mode input and digital startup mode input simultaneously, according to the user's needs or the functional safety level requirements of the application scenario.

[0060] In this embodiment of the invention, the input selection module 60 outputs an analog signal to the analog-to-digital converter (ADC) 20 and sends a digital signal to the digital startup mode capturer 10 when the startup mode needs to be verified.

[0061] Example 2

[0062] Figure 2 This is a schematic diagram of another embodiment of the digital-analog heterogeneous redundancy startup mode configuration system according to the present invention, as shown below. Figure 2 As shown, the heterogeneous redundancy startup mode configuration system for analog and digital systems in this embodiment includes:

[0063] Digital Startup Mode Capturer:

[0064] After the processor is initially powered on, the configuration of the digital boot mode is captured from the digital input pins (DIO_0 to DIO_N), and the captured N+1 bits of digital boot mode configuration information (DBM[N:0]) are latched for use by the processor.

[0065] Analog-to-digital converter (ADC):

[0066] The analog signal input to the analog input pin (AIO_0) is measured and converted into a digital signal for output.

[0067] In this embodiment of the invention, if the requirement of the startup mode selection pin is higher than the accuracy of the ADC, the startup mode selection pin needs to be grouped and multiple ADCs are used to measure multiple analog-digital pins.

[0068] Simulated Startup Mode Capturer:

[0069] During the processor startup phase, the ADC is started to measure the analog signal input to AIO_0, and the (P+1) bit analog signal sample value ASV[P:0] is obtained;

[0070] The measurement result (analog signal sample value ASV[P:0]) is converted into M+1 bit analog startup mode configuration information (ABM[M:0]) and sent to the startup mode verifier.

[0071] In this embodiment of the invention, the conversion method used is as follows: the high PM bit of ASV is extracted as the simulated startup mode configuration information, thereby avoiding the influence of ADC sampling error on startup mode selection.

[0072] Startup mode verification method detector:

[0073] By analyzing the sampling results of the ADC analog signal, the verification method is selected and determined;

[0074] In this embodiment of the invention, the high-order bits of the ASV are used as selection bits, and the remaining bits are used as start-up mode selection information. For example, if the ASV is a 6-bit data, the verification method is determined as follows:

[0075] The two most significant bits (bit5, bit4) of the ASV are used as selection bits to encode the check method. The check encoding is as follows:

[0076] b00: No startup mode verification performed;

[0077] b01: Perform parity check on the startup mode (requires 1 parity bit);

[0078] b10: Perform 1-bit error checking on the startup mode and start 1-bit error correction (using 7-4 Hamming code, requiring 3-bit check bits).

[0079] b11: Perform two-bit error checking on the startup mode and enable one-bit error correction (using 8-4 Hamming code, requiring 4-bit check bits).

[0080] Startup mode verifier:

[0081] The startup mode verifier selects corresponding data from the analog startup mode configuration information (ABM[M:0]) and digital startup mode configuration information (DBM[N:0]) for verification based on the verification method detected by the startup mode verification method detector. After verification, the final startup mode (SBM[X:0]) is output for system use. If an error (ERR) is detected, it is reported to the system controller. For example, ASV is 6 bits of data, with the high two bits used as the verification method code and the low four bits ABM[3:0] representing the analog startup mode configuration information. DBM[3:0] represents the 4-bit digital startup mode configuration verification information. Depending on the verification method, the startup mode verifier selects different DBM data to verify ABM. The startup mode verification methods based on the different verification codes sent by the startup mode verification method detector are as follows:

[0082] b00: No boot mode verification is performed, then SBM[3:0] = ABM[3:0], and the verification error flag ERR is forced to 0.

[0083] b01: Perform parity checking on the boot mode, SBM[3:0] = ABM[3:0], and simultaneously calculate the parity value P of ABM. If P = DBM[0], then ERR=0; if P is not equal to DBM[0], then ERR=1. In this mode, only one digital boot mode IO is needed for verification, saving system IO resources. However, due to the relatively low diagnostic coverage of parity checking, the functional safety level of this mode is relatively low.

[0084] b10: Perform 1-bit error checking and activate 1-bit error correction function for the startup mode (using 7-4 Hamming code, requiring 3-bit check bits), SBM[3:0] = ABM[3:0], and simultaneously use DBM[2:0] to check and correct ABM[3:0]. Since 7-4 Hamming code can only detect 1-bit errors and correct them, ERR is forced to 0. If an error exceeding 1 bit occurs, this mode cannot detect it. This mode requires 3-bit digital startup mode I / O for verification, necessitating the use of more digital I / O resources. Due to the relatively high diagnostic coverage of 7-4 Hamming code verification, this mode has a relatively high functional safety level.

[0085] b11: Perform two-bit error checking and activate 1-bit error correction in the startup mode (using 8-4 Hamming code, requiring 4-bit check bits), SBM[3:0] = ABM[3:0], and simultaneously use DBM[3:0] to check and correct ABM[3:0]. If there is no error or a 1-bit error occurs, ERR=0; if a 2-bit error is detected, ERR=1. This mode requires 4-bit digital startup mode I / O for verification, necessitating the use of more digital I / O resources. Compared to 7-4 Hamming code, 8-4 Hamming code verification further improves diagnostic coverage, resulting in a relatively higher functional safety level.

[0086] In this embodiment of the invention, the startup mode verifier uses the above-mentioned startup mode verification method to verify the analog startup mode configuration information and the digital startup mode configuration information, so that the digital-analog heterogeneous redundant startup mode configuration system of the present invention has adaptive adjustment function, security level function and adjustable system IO resource usage function.

[0087] Input selection module:

[0088] Through multiple analog switches (AS0, AS1…ASM), digital switches (DS0, DS1…DSM), and digital-to-analog converters, analog start mode input, digital start mode input, or simultaneous analog start mode input and digital start mode input can be achieved.

[0089] In this embodiment of the invention, the input selection module outputs an analog signal to the analog-to-digital converter (ADC) when a startup mode requiring verification is needed, and simultaneously sends a digital signal to the digital startup mode capture device.

[0090] Example 3

[0091] Figure 3 The flowchart of the digital-analog heterogeneous redundancy startup mode configuration method according to the present invention will be referred to below. Figure 3 The method for configuring the heterogeneous redundancy startup mode of the present invention will be described in detail.

[0092] First, in step 301, based on the user's needs or the functional safety level requirements of the application scenario, select either the simulated startup mode or the digital startup mode.

[0093] In this embodiment of the invention, the input selection module 60 uses multiple analog switches (AS0, AS1…ASM), digital switches (DS0, DS1…DSM), and a digital-to-analog converter to select between analog startup mode and digital startup mode.

[0094] In step 302, the digital boot mode configuration information is captured and locked.

[0095] In this embodiment of the invention, the digital startup mode capturer 10 captures and locks the digital startup mode configuration information from the digital input pins (IO_0 to IO_N) and sends it to the startup mode verifier 50.

[0096] After the processor is initially powered on, the configuration of the digital boot mode is captured from the digital input pins (DIO_0 to DIO_N), and the captured N+1 bits of digital boot mode configuration information (DBM[N:0]) are latched and sent to the boot mode verifier 50.

[0097] In step 303, the input analog signal is measured, and the analog startup mode configuration information is captured from the analog signal sample value.

[0098] In this embodiment of the invention, the analog startup mode capture device 30 starts the analog-to-digital converter 20 to measure the analog signal input to AIO_0 during the processor startup phase, and obtains the (P+1) bit analog signal sample value ASV[P:0];

[0099] The measurement result (analog signal sample value ASV[P:0]) is converted into M+1 bit analog startup mode configuration information (ABM[M:0]) and sent to the startup mode verifier.

[0100] In this embodiment of the invention, the simulated startup mode capture device 30 extracts the high P-Mbit of the ASV as simulated startup mode configuration information, thereby avoiding the influence of ADC sampling error on startup mode selection.

[0101] In step 304, the verification method of the startup mode is determined based on the sampled values ​​of the analog signal.

[0102] In this embodiment of the invention, the startup mode verification method detector 40 selects and determines the verification method by analyzing the sampling results of the ADC analog signal;

[0103] In this embodiment of the invention, the startup mode verification detector 40 uses the high-order bits of the ASV as the selection bits and the remaining bits as startup mode selection information. For example, if the ASV is a 6-bit data, the verification method is determined as follows:

[0104] Use the two most significant bits of ASV (bit5, bit4) as selection bits to encode the check method:

[0105] b00: No startup mode verification performed;

[0106] b01: Perform parity check on the startup mode (requires 1 parity bit);

[0107] b10: Perform 1-bit error checking on the startup mode and start 1-bit error correction (using 7-4 Hamming code, requiring 3-bit check bits).

[0108] b11: Perform 2-bit error checking on the startup mode and enable 1-bit error correction (using 8-4 Hamming code, requiring 4-bit check bits).

[0109] In step 305, the digital boot mode configuration information and the analog boot mode configuration information are verified.

[0110] In this embodiment of the invention, the startup mode verifier 50 selects corresponding data from the analog startup mode configuration information (ABM[M:0]) and the digital startup mode configuration information (DBM[N:0]) for verification according to the verification method detected by the startup mode verification method detector 40. After verification, the final startup mode (SBM[X:0]) is output for system use. If an error (ERR) is detected, it is reported to the system controller.

[0111] For example, ASV is 6 bits of data, with the high two bits used as the verification method encoding and the low four bits (ABM[3:0]) representing the analog startup mode configuration information. DBM[3:0] represents the 4-bit digital startup mode configuration verification information. Depending on the verification method, the startup mode verifier selects different DBM data to verify ABM. The startup mode verification methods, based on the different verification codes sent by the detector, are as follows:

[0112] b00: No boot mode verification is performed, then SBM[3:0] = ABM[3:0], and the verification error flag ERR is forced to 0.

[0113] b01: Perform parity checking on the boot mode, SBM[3:0] = ABM[3:0], and simultaneously calculate the parity value P of ABM. If P = DBM[0], then ERR=0; if P is not equal to DBM[0], then ERR=1. In this mode, only one digital boot mode IO is needed for verification, saving system IO resources. However, due to the relatively low diagnostic coverage of parity checking, the functional safety level of this mode is relatively low.

[0114] b10: Perform 1-bit error checking and activate 1-bit error correction function for the startup mode (using 7-4 Hamming code, requiring 3-bit check bits), SBM[3:0] = ABM[3:0], and simultaneously use DBM[2:0] to check and correct ABM[3:0]. Since 7-4 Hamming code can only detect 1-bit errors and correct them, ERR is forced to 0. If an error exceeding 1 bit occurs, this mode cannot detect it. This mode requires 3-bit digital startup mode I / O for verification, necessitating the use of more digital I / O resources. Due to the relatively high diagnostic coverage of 7-4 Hamming code verification, this mode has a relatively high functional safety level.

[0115] b11: Perform two-bit error checking and activate 1-bit error correction in the startup mode (using 8-4 Hamming code, requiring 4-bit check bits), SBM[3:0] = ABM[3:0], and simultaneously use DBM[3:0] to check and correct ABM[3:0]. If there is no error or a 1-bit error occurs, ERR=0; if a 2-bit error is detected, ERR=1. This mode requires 4-bit digital startup mode I / O for verification, necessitating the use of more digital I / O resources. Compared to 7-4 Hamming code, 8-4 Hamming code verification further improves diagnostic coverage, resulting in a relatively higher functional safety level.

[0116] In this embodiment of the invention, the above-mentioned startup mode verification method is used to verify the analog startup mode configuration information and the digital startup mode configuration information, so that the digital-analog heterogeneous redundant startup mode configuration system of the present invention has adaptive adjustment function, security level function and adjustable system IO resource usage function.

[0117] Example 4

[0118] The present invention also provides a chip including the digital-analog heterogeneous redundant startup mode configuration system as described above, which can avoid common cause failure of startup mode detection circuit and improve the fault diagnosis rate of startup mode sampling circuit.

[0119] Example 5

[0120] In the embodiments of this application, an electronic device is also provided. Figure 4 This is a schematic diagram of the electronic device structure according to an embodiment of this application, such as... Figure 4 As shown, the electronic device of this application includes a processor 401 and a memory 402, wherein,

[0121] The processor 401 uses the chip described in the embodiment above.

[0122] The memory 402 stores a computer program, which, when read and executed by the processor 401, performs the steps described above in the embodiment of the digital-analog heterogeneous redundancy startup mode configuration method.

[0123] Example 6

[0124] In the embodiments of this application, a computer-readable storage medium is also provided, which stores a computer program, wherein the computer program is configured to execute the steps in the embodiments of the analog-digital heterogeneous redundancy startup mode configuration method as described above when running.

[0125] In the embodiments of this application, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0126] It will be understood by those skilled in the art that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A configuration system for heterogeneous startup mode of digital and analog circuits, characterized in that, include: A digital start mode capturer is used to capture digital start mode configuration information from input digital signals; An analog-to-digital converter is used to measure an input analog signal, convert the analog signal into a digital signal, and obtain the analog signal sample value. A simulated startup mode capturer is used to capture simulated startup mode configuration information from the sampled values ​​of the simulated signal; A startup mode verification detector is used to determine the startup mode verification method based on the sampled values ​​of the analog signal. A startup mode verifier is used to verify the digital startup mode configuration information and the analog startup mode configuration information according to the startup mode verification method. The analog startup mode capturer extracts a set number of bits from the high bits of the analog signal sample value output by the analog-to-digital converter as analog startup configuration information; The startup mode verification detector extracts a specific high bit from the analog signal sample value output by the analog-to-digital converter as a selection bit, and selects a preset verification scheme through the encoding of the selection bit. The startup mode verifier selects either the digital startup mode configuration information or the analog startup mode configuration information as the verification data for the startup mode, and verifies the other startup mode configuration information.

2. The digital-analog heterogeneous redundancy startup mode configuration system according to claim 1, characterized in that, Also includes: The input selection module is used to set the input startup mode.

3. The heterogeneous redundancy startup mode configuration system according to claim 1, characterized in that, The digital boot mode capturer captures and latches the digital boot mode configuration information after the processor is initially powered on.

4. The digital-analog heterogeneous redundancy startup mode configuration system according to claim 1, characterized in that, The analog-to-digital converter may be one or more.

5. The digital-analog heterogeneous redundancy startup mode configuration system according to claim 1, characterized in that, The analog startup mode capture device is used to activate the analog-to-digital converter to measure the input analog signal; and to convert the sampled value of the analog signal output by the analog-to-digital converter into analog startup mode configuration information.

6. The digital-analog heterogeneous redundancy startup mode configuration system according to claim 1, characterized in that, The startup mode verification detector selects the high-order bits of the analog signal sample value output by the analog-to-digital converter as the selection bits according to a set number of bits, and uses the remaining bits as startup mode selection information.

7. The digital-analog heterogeneous redundancy startup mode configuration system according to claim 1, characterized in that, The startup mode verification methods include: not verifying the startup mode, performing parity verification on the startup mode, performing 1-bit error verification on the startup mode and enabling 1-bit error correction function, and performing 2-bit error verification on the startup mode and enabling 1-bit error correction function.

8. The digital-analog heterogeneous redundancy startup mode configuration system according to claim 1, characterized in that, The startup mode verifier selects either digital startup mode configuration information or analog startup mode configuration information as the verification data for the startup mode, based on the startup mode verification method, and verifies the other startup mode configuration information.

9. A method for configuring a heterogeneous digital-analog startup mode, employing the heterogeneous digital-analog startup mode configuration system according to any one of claims 1-8, comprising: Select the startup mode; Capture and lock digital boot mode configuration information; Measure the input analog signal and capture the analog startup mode configuration information from the sampled analog signal values; The startup mode verification method is determined based on the sampled values ​​of the analog signal. According to the boot mode verification method, verify the digital boot mode configuration information and the analog boot mode configuration information.

10. The method for configuring a heterogeneous startup mode for digital and analog circuits according to claim 9, characterized in that, The step of capturing analog startup mode configuration information from analog signal sample values ​​further includes: extracting a set number of bits from the high bits of the analog signal sample values ​​output by the analog-to-digital converter as analog startup mode configuration information.

11. The method for configuring a heterogeneous startup mode for digital and analog circuits according to claim 9, characterized in that, The step of determining the startup mode verification method based on the analog signal sample value further includes: selecting the high bits of the analog signal sample value output by the analog-to-digital converter as the selection bits according to a set number of bits, and using the remaining bits as startup mode selection information.

12. The method for configuring a heterogeneous startup mode for digital and analog circuits according to claim 11, characterized in that, The startup mode verification methods include: not verifying the startup mode, performing parity verification on the startup mode, performing 1-bit error verification on the startup mode and enabling 1-bit error correction function, and performing 2-bit error verification on the startup mode and enabling 1-bit error correction function.

13. The method for configuring a heterogeneous startup mode for digital and analog circuits according to claim 9, characterized in that, The step of verifying the digital startup mode configuration information and the analog startup mode configuration information according to the startup mode verification method further includes: selecting either the digital startup mode configuration information or the analog startup mode configuration information as the verification data for the startup mode according to the startup mode verification method, and verifying the other startup mode configuration information.

14. A chip, characterized in that, The system is equipped with the digital-analog heterogeneous redundancy startup mode configuration system as described in any one of claims 1-8.

15. An electronic device, characterized in that, It includes a memory and a processor, the memory storing computer instructions, the processor employing the chip of claim 14, and the processor being configured to execute the instructions to perform the steps of the digital-analog heterogeneous redundancy startup mode configuration method of any one of claims 9-13.

16. A computer-readable storage medium, characterized in that, It stores computer instructions, which, when executed, perform the steps of the digital-analog heterogeneous redundancy startup mode configuration method according to any one of claims 9-13.

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