A Reconfigurable 3D Chip and Its Integration Method

Abstract

The present invention discloses a reconfigurable 3D chip and an integration method thereof. The method includes: designing the architecture of the reconfigurable 3D chip; performing semiconductor manufacturing on the reconfigurable computing logic chip of the reconfigurable 3D chip to obtain an uncut reconfigurable logic wafer; according to the architecture of the reconfigurable 3D chip, bonding the reconfigurable logic wafer and the memory wafer face to face by using a hybrid technology, and connecting the signal IOs of the reconfigurable logic wafer and the signal IOs of the memory wafer together; cutting the bonded stacked chip to obtain independent stacked wafers; and packaging the stacked wafers to obtain the reconfigurable 3D chip.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and more particularly, to a reconfigurable 3D chip and an integration method thereof. Background Art

[0002] With the continuous development of artificial intelligence technology, the demand for chip computing power is increasing. Chip designers must continuously improve computing power to meet the growing demand. The computing power of a chip, that is, the computing performance of the chip, is affected by various factors. The main functional components of a chip mainly include a memory, an arithmetic unit, a controller, an input device, and an output device. Its basic working process is that the original data is pre-stored in the memory or enters the memory through the input device. Under the control of the program, the controller sends the data in the memory to the arithmetic unit for calculation, and then writes the calculated data into the memory or sends it to the output device. During the entire data calculation process, the data needs to be transferred back and forth between the memory and the arithmetic unit. Therefore, the amount of data transferred between the arithmetic unit and the memory per unit time and the time consumed by the data on the transmission path will directly affect the performance of the chip. The ability to transfer data between the chip arithmetic unit and the memory can be represented by two parameters: bandwidth and latency. With the continuous development of modern semiconductor technology, the processing speed of the arithmetic unit in the chip has been continuously improved, far exceeding the read / write bandwidth and latency that the memory can provide, resulting in the "memory wall" problem. There are many types of memories. Currently, the large-capacity high-speed memory outside the chip is mainly DRAM. In the traditional architecture, there are mainly two forms of interconnection between DRAM and the computing chip: PCB board-level 2D interconnection and silicon substrate 2.5D interconnection. For the PCB board-level 2D interconnection form between the DRAM memory and the computing chip, the physical distance between the memory and the computing unit is centimeter-level, and the load on the data signal link is also large, resulting in a very low data transmission bandwidth. At the same time, due to the limitation of the number of chip IO ports, the interconnection bandwidth is further limited, making it difficult to meet the needs of the computing unit and resulting in performance degradation. Based on the 2.5D integration of the silicon substrate, the memory die and the computing die are interconnected on a silicon substrate. Although it greatly reduces the interconnection distance compared with the PCB board-level interconnection, shrinking the interconnection distance between the memory and the calculator to the millimeter-level, its essence is still a two-dimensional planar interconnection structure, and the memory bandwidth improvement is limited and still cannot meet the computing requirements. Taking the 2.5D interconnection between HBM DRAM and the computing chip as an example, a single HBM DRAM particle can only provide an interface bit width of 1024 bits, and the data transmission bit width is limited. Summary of the Invention

[0003] In view of the deficiencies of the prior art, the present invention provides a reconfigurable 3D chip and an integration method thereof.

[0004] According to one aspect of the present invention, an integration method of a reconfigurable 3D chip is provided, including:

[0005] Design the architecture of a reconfigurable 3D chip;

[0006] Perform semiconductor manufacturing on the reconfigurable computing logic chip of the reconfigurable 3D chip to obtain an uncut reconfigurable logic wafer;

[0007] According to the architecture of the reconfigurable 3D chip, bond the reconfigurable logic wafer and the memory wafer face-to-face using a hybrid technology, and connect the signal IOs of the reconfigurable logic wafer and the signal IOs of the memory wafer;

[0008] Cut the bonded stacked chips to obtain independent stacked wafers;

[0009] Package the stacked wafers to obtain a reconfigurable 3D chip.

[0010] Optionally, it further includes:

[0011] According to the architecture of the reconfigurable 3D chip, develop and verify the RTL code of the reconfigurable 3D chip to determine the chip RTL code.

[0012] Optionally, performing semiconductor manufacturing on the reconfigurable computing logic chip of the reconfigurable 3D chip to obtain an uncut reconfigurable logic wafer includes:

[0013] According to the architecture of the reconfigurable 3D chip, perform logic synthesis on the reconfigurable 3D chip to obtain the gate-level netlist of the reconfigurable 3D chip;

[0014] Perform placement and routing on the reconfigurable computing logic chip of the reconfigurable 3D chip according to the gate-level netlist to determine the GDS file of the reconfigurable computing logic chip;

[0015] According to the GDS file, perform semiconductor manufacturing on the GDS of the reconfigurable computing logic chip to obtain an uncut reconfigurable logic wafer.

[0016] Optionally, according to the architecture of the reconfigurable 3D chip, bonding the reconfigurable logic wafer and the memory wafer face-to-face using a hybrid technology and connecting the signal IOs of the reconfigurable logic wafer and the signal IOs of the memory wafer includes:

[0017] Determine the hybrid bonding scheme of the reconfigurable computing logic chip according to the hybrid bonding rules of the reconfigurable 3D chip architecture;

[0018] According to the hybrid bonding scheme, bond the reconfigurable logic wafer and the memory wafer face-to-face using a hybrid technology, and connect the signal IOs of the reconfigurable logic wafer and the signal IOs of the memory wafer.

[0019] According to another aspect of the present invention, there is provided a reconfigurable 3D chip, including:

[0020] A reconfigurable computing die and a memory die disposed on the top layer of the reconfigurable computing die, wherein

[0021] the memory die includes a plurality of memory cells, each reconfigurable computing unit of the reconfigurable computing die is configured with an independent memory cell, and the reconfigurable computing unit is connected to its corresponding memory cell in a tightly coupled manner.

[0022] Optionally, a data flow computing mode is adopted between multiple reconfigurable computing units to realize data transfer.

[0023] Optionally, the memory die is a single-layer or multi-layer stacked memory.

[0024] Optionally, the memory cell is one or more logical storage blocks.

[0025] Optionally, the reconfigurable computing units inside the reconfigurable computing die form a two-dimensional array.

[0026] Optionally, the memory die on the top layer is directly stacked with the reconfigurable computing die at the bottom layer, and signal connection is achieved through through-silicon vias or hybrid bonding technology.

[0027] Thus, the present invention provides a method for three-dimensionally integrating DRAM particles and reconfigurable computing dies into a reconfigurable 3D chip. The reconfigurable computing die is a configurable data flow computing architecture, which naturally matches well with application programs having data flow computing characteristics. It has distributed on-chip computing resources. Combining with three-dimensionally integrated DRAM particles, it can reduce the physical distance between the computing unit and the storage unit to the micron level, greatly improving the memory access bandwidth, and thus significantly improving the computing performance of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] By referring to the following drawings, the exemplary embodiments of the present invention can be more completely understood:

[0029] Figure 1 is a schematic flow chart of an integration method of a reconfigurable 3D chip provided by an exemplary embodiment of the present invention;

[0030] Figure 2 is a design flow chart of a 3D chip formed by stacking a reconfigurable computing die and a memory die provided by an exemplary embodiment of the present invention;

[0031] Figure 3 is a schematic structural diagram of a reconfigurable 3D chip provided by an exemplary embodiment of the present invention;

[0032] Figure 4 is a three-dimensional integration schematic diagram of a memory die and a reconfigurable computing die provided by an exemplary embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0033] Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Apparently, the described embodiments are only a part of the embodiments of the present invention, rather than all embodiments of the present invention. It should be understood that the present invention is not limited by the exemplary embodiments described herein.

[0034] It should be noted that: Unless otherwise specifically stated, the relative arrangements, numerical expressions, and numerical values of the components and steps set forth in these embodiments do not limit the scope of the present invention.

[0035] Those skilled in the art can understand that terms such as "first" and "second" in the embodiments of the present invention are only used to distinguish different steps, devices, or modules, etc., and neither represent any specific technical meaning nor indicate an inevitable logical order between them.

[0036] It should also be understood that in the embodiments of the present invention, "a plurality of" may refer to two or more, and "at least one" may refer to one, two, or more.

[0037] It should also be understood that for any component, data, or structure mentioned in the embodiments of the present invention, without clear limitation or contrary indication in the context, it can generally be understood as one or more.

[0038] In addition, the term "and / or" in the present invention is merely a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in the present invention generally represents an "or" relationship between the associated objects before and after.

[0039] It should also be understood that the present invention emphasizes the differences between the various embodiments. The same or similar parts can be referred to each other. For the sake of brevity, they will not be described one by one.

[0040] Meanwhile, it should be understood that for the sake of convenience of description, the dimensions of the various parts shown in the drawings are not drawn according to the actual proportional relationship.

[0041] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way a limitation on the present invention or its application or use.

[0042] Techniques, methods, and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, the techniques, methods, and devices should be regarded as part of the specification.

[0043] It should be noted that like reference numerals and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.

[0044] Embodiments of the present invention can be applied to electronic devices such as terminal devices, computer systems, servers, etc., which can operate together with many other general-purpose or special-purpose computing system environments or configurations. Examples of well-known terminal devices, computing systems, environments, and / or configurations suitable for use with electronic devices such as terminal devices, computer systems, servers, etc. include, but are not limited to: personal computer systems, server computer systems, thin clients, thick clients, handheld or laptop devices, microprocessor-based systems, set-top boxes, programmable consumer electronics, network personal computers, minicomputer systems, mainframe computer systems, and distributed cloud computing technology environments including any of the above systems, and so on.

[0045] Electronic devices such as terminal devices, computer systems, servers, etc. can be described in the general context of computer system-executable instructions (such as program modules) executed by a computer system. Generally, program modules can include routines, programs, object programs, components, logic, data structures, etc., which perform specific tasks or implement specific abstract data types. The computer system / server can be implemented in a distributed cloud computing environment where tasks are executed by remote processing devices linked through a communication network. In a distributed cloud computing environment, program modules can be located on local or remote computing system storage media including storage devices.

[0046] Figure 1 is a schematic flow diagram of an integration method of a reconfigurable processing chip according to the first aspect of the present invention. This embodiment can be applied to an electronic device, such as Figure 1 As shown, the integration method 100 of the reconfigurable 3D chip includes the following steps:

[0047] Step 101, design the architecture of the reconfigurable 3D chip;

[0048] Step 102, perform semiconductor manufacturing on the reconfigurable computing logic chip of the reconfigurable 3D chip to obtain an uncut reconfigurable logic wafer;

[0049] Step 103, according to the architecture of the reconfigurable 3D chip, bond the reconfigurable logic wafer and the memory wafer face-to-face using a hybrid technology, and connect the signal IOs of the reconfigurable logic wafer and the signal IOs of the memory wafer together;

[0050] Step 104, cut the bonded and stacked chip to obtain independent stacked wafers;

[0051] Step 105: Package the stacked wafers to obtain a reconfigurable 3D chip.

[0052] Optionally, it further includes:

[0053] Develop and verify the RTL code of the reconfigurable 3D chip according to the architecture of the reconfigurable 3D chip to determine the chip RTL code.

[0054] Optionally, perform semiconductor manufacturing on the reconfigurable computing logic chip of the reconfigurable 3D chip to obtain an uncut reconfigurable logic wafer, including:

[0055] Perform logic synthesis on the reconfigurable 3D chip according to the architecture of the reconfigurable 3D chip to obtain the gate-level netlist of the reconfigurable 3D chip;

[0056] Perform placement and routing on the reconfigurable computing logic chip of the reconfigurable 3D chip according to the gate-level netlist to determine the GDS file of the reconfigurable computing logic chip;

[0057] Manufacture the GDS of the reconfigurable computing logic chip through semiconductor manufacturing according to the GDS file to obtain an uncut reconfigurable logic wafer.

[0058] Optionally, according to the architecture of the reconfigurable 3D chip, bond the reconfigurable logic wafer and the memory wafer face to face using a hybrid technology, and connect the signal IOs of the reconfigurable logic wafer and the memory wafer together, including:

[0059] Determine the hybrid bonding scheme of the reconfigurable computing logic chip according to the hybrid bonding rules of the reconfigurable 3D chip architecture;

[0060] According to the hybrid bonding scheme, bond the reconfigurable logic wafer and the memory wafer face to face using a hybrid technology, and connect the signal IOs of the reconfigurable logic wafer and the memory wafer together.

[0061] Specifically, referring to Figure 2 as shown, the design process of bonding the reconfigurable die and the DRAM die to form a 3D chip is shown, and the specific steps are as follows:

[0062] First, perform the architecture design of the reconfigurable 3D chip. After determining the chip architecture through design space exploration, develop and verify the RTL code to ensure the correctness of the chip RTL code.

[0063] After the RTL code verification is completed, perform logic synthesis to obtain the gate-level netlist of the chip.

[0064] Then enter the IC physical implementation stage, perform layout and wiring on the reconfigurable computing logic chip, obtain the GDS file of the reconfigurable computing logic chip and the hybrid bonding design scheme determined according to the hybrid bonding rule, and ensure the correctness of the bonding position relationship between the logic wafer and the DRAM wafer. The GDS of the reconfigurable computing logic chip is manufactured by semiconductor manufacturing to obtain an uncut reconfigurable logic wafer.

[0065] According to the hybrid bonding scheme design, bond the reconfigurable logic wafer and the DRAM wafer face to face using the hybrid bonding technology, and reliably connect the signal I / O of the reconfigurable logic wafer and the signal I / O of the DRAM wafer together; then, cut and slice the bonded stacked chip to obtain independent stacked wafers, and package the wafers to obtain the final reconfigurable 3D chip.

[0066] The present invention proposes a method for three-dimensional integration of DRAM particles and reconfigurable computing die. The reconfigurable computing die is a configurable data flow computing architecture, which naturally matches well with application programs with data flow computing characteristics. It has distributed on-chip computing resources. Combining with three-dimensional integrated DRAM particles, it can reduce the physical distance between the computing unit and the storage unit to the micron level, greatly improving the memory access bandwidth, and thus significantly improving the chip computing performance.

[0067] Therefore, the reconfigurable 3D chip of the present invention adopts a reconfigurable computing architecture, which is a data-stream computing architecture without instruction scheduling, capable of achieving fully data-driven computing, with high computing energy efficiency and good flexibility at the same time. On the one hand, compared with the shared memory computing architecture of NV GPGPU, the data-stream computing mode of the reconfigurable computing architecture can greatly reduce the access to external memory, thereby reducing the dependence on memory access bandwidth and being less likely to encounter memory access bottlenecks. For example, for the general matrix multiplication operation commonly used in artificial intelligence algorithms, the reconfigurable computing architecture does not need to read and write intermediate results back and forth in external memory, which can save 50% of the memory access bandwidth. For the computing die, multiple reconfigurable computing cores can be deployed on the chip. Combining with 3D stacked DRAM dies, a one-to-one vertical interconnection can be achieved between the computing cores and the DRAM memory, reducing the interconnection distance to the micron level, achieving a large memory access bandwidth of 512GB / s, and providing a close storage capacity of up to 128MB for each computing core, which can directly save a large amount of on-chip SRAM layout. Each reconfigurable computing die contains 32 reconfigurable computing cores on the chip, so a single die can achieve an extremely high memory access bandwidth of 16TB / s. By vertically stacking DRAM dies, near-memory computing can be achieved, effectively breaking through the "memory wall" problem and significantly improving the overall performance of the packaged chip. On the other hand, the conventional GPGPU computing architecture is instruction-driven, and a large amount of precious area on the computing chip is consumed in instruction-related processing and scheduling, resulting in tight computing resources. At the same time, its single instruction multiple thread (SIMT) computing mode has low computing resource utilization in processing sparse data sets, general computing, and typical artificial intelligence algorithms, typically less than 50%. With its high-density computing unit array and flexible programmable on-chip interconnection network, the reconfigurable computing architecture can achieve higher computing resource utilization than GPGPU and higher actual computing power. In terms of computing energy efficiency, the core computing power die of this project is designed with a reconfigurable computing architecture. The reconfigurable computing architecture completely eliminates instruction overhead and drives task execution through dynamically configured information. The accelerated program code can be transformed into a reconfigurable computing task configuration through a reconfigurable compiler, and the configuration information drives the entire array to operate in a manner similar to "application-specific integrated circuit (ASIC)", with very high computing energy efficiency. The reconfigurable computing architecture can fully exploit and release various parallel capabilities contained in the program itself, such as instruction-level parallelism (implemented through meta-pipelines), data-level parallelism (implemented through SIMD), and task-level parallelism (coarse-grained pipelining, virtualization), and can achieve a very high degree of computing parallelism. Under the same process area, the computing performance of the reconfigurable computing architecture is more than twice that of NVIDIA GPUs, and the computing energy efficiency can reach more than ten times.

[0068] In addition, Figure 3 For the schematic diagram of the reconfigurable 3D chip according to the second aspect of the embodiments of the present application, refer to Figure 3As shown, the reconfigurable 3D chip includes:

[0069] A reconfigurable computing die and a memory die disposed on the top layer of the reconfigurable computing die, where

[0070] The memory die includes multiple memory cells. Each reconfigurable computing unit of the reconfigurable computing die is configured with an independent memory cell, and a tight coupling method is used to connect the reconfigurable computing unit and its corresponding memory cell.

[0071] Optionally, a data flow computing mode is adopted between multiple reconfigurable computing units to achieve data transfer.

[0072] Optionally, the memory die is a single-layer or multi-layer stacked memory.

[0073] Optionally, the memory cell is one or more logical storage blocks.

[0074] Optionally, the reconfigurable computing units inside the reconfigurable computing die form a two-dimensional array.

[0075] Optionally, the top-layer memory die and the bottom-layer reconfigurable computing die are directly stacked, and signal connection is achieved through through-silicon vias or hybrid bonding technology.

[0076] Specifically, the present invention proposes a reconfigurable 3D chip obtained by three-dimensionally integrating DRAM particles and reconfigurable computing dies. The logical schematic diagram of the integration of the reconfigurable computing die and DRAM is as Figure 3 shown. In the figure, the PE reconfigurable computing unit is the main computing module that provides computing power. The memory in the figure is the memory, corresponding to the DRAM memory in the 3D integration. Figure 1 The reconfigurable chip architecture shown has the following differences from the traditional CPU / GPU: ① The traditional CPU / GPU is a shared memory computing architecture, and all computing units operate on a unified memory space, resulting in a large demand for memory access bandwidth; the reconfigurable computing die is a distributed memory computing architecture, each PE is equipped with an independent storage space, and each computing unit PE and its corresponding memory adopt a tight coupling method, so the memory access latency is also lower. ② The traditional CPU / GPU is an instruction-driven computing mode, and the data interaction between computing units is all through the global memory, and the computing performance is easily limited by the memory bandwidth and latency; the reconfigurable computing architecture adopted in the present invention is a data flow computing mode, which supports direct data transfer between computing units. Each PE completes its own computing task on its own independent storage space, and the processed data is directly transferred from the local PE to other PEs, thereby realizing data stream computing.

[0077] The present invention proposes a method of integrating DRAM die and reconfigurable elements into a complete chip through three-dimensional stacking. Its basic structure is as Figure 4 shown. The top layer is a DRAM die, which can be a single die or multiple dies. The DRAM die itself can be a single layer or multiple stacked DRAMs. The bottom layer is a reconfigurable computing die, with an internal two-dimensional array composed of basic computing units PE. The DRAM die on the top layer is directly stacked with the reconfigurable computing die on the bottom layer, and signal interconnection between the two is achieved through through-silicon vias (TSV). One PE of the reconfigurable computing die can directly correspond to a part or the complete physical / logical storage block of the top-layer DRAM, or can correspond to multiple DRAM logical storage blocks.

[0078] Therefore, the present application has the following beneficial effects:

[0079] (1) The three-dimensional integration of DRAM die and reconfigurable die reduces the physical distance between the memory and the computing unit to the micron level, significantly improving the memory access bandwidth and reducing the memory access latency, thus significantly enhancing the overall performance of the integrated chip.

[0080] (2) Significantly improves the single-core storage capacity. Since DRAM itself has the characteristic of high storage density, and the DRAM die can also be stacked in multiple layers, the method of three-dimensional integration through vertical stacking can enable a single PE to have a larger storage capacity.

[0081] (3) The reconfigurable computing die has stronger computing power. Since the DRAM memory and the reconfigurable computing die are three-dimensionally stacked and integrated, it can provide stronger memory access performance for the reconfigurable computing die. Therefore, the memory space on the reconfigurable chip can be significantly reduced, freeing up more silicon area for computing resources, and thus enabling the reconfigurable computing die to achieve stronger computing power.

[0082] (4) Reduces the power consumption of the overall chip. The three-dimensional integration of DRAM die and reconfigurable die significantly reduces the connection distance between the computing unit and the storage unit, and the load resistance and capacitance on the connection are also correspondingly significantly reduced. Therefore, the power consumption of memory access is significantly reduced, effectively reducing the power consumption of the entire chip.

[0083] The basic principle of the present invention is described above in combination with specific embodiments. However, it should be noted that the advantages, advantages, effects, etc. mentioned in the present invention are only examples and not limitations. It cannot be considered that these advantages, advantages, effects, etc. are essential for each embodiment of the present invention. In addition, the above-disclosed specific details are only for the purpose of illustration and easy understanding, and are not limitations. The above details do not limit the present invention to necessarily adopt the above specific details to implement.

[0084] In the present specification, each embodiment is described in a progressive manner. The key point of each embodiment is to illustrate the differences from other embodiments. For the same or similar parts among the embodiments, reference can be made to each other. For system embodiments, since they basically correspond to method embodiments, they are described relatively simply. For related parts, reference can be made to the partial description of method embodiments.

[0085] The block diagrams of devices, systems, equipment, and systems involved in the present invention are only illustrative examples and are not intended to require or imply that they must be connected, arranged, and configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, systems, equipment, and systems can be connected, arranged, and configured in any way. Words such as "including", "comprising", "having", etc. are open-ended terms, meaning "including but not limited to", and can be used interchangeably with each other. The word "or" and "and" used herein refer to the word "and / or" and can be used interchangeably with each other, unless the context clearly indicates otherwise. The word "such as" used herein refers to the phrase "such as but not limited to" and can be used interchangeably with each other.

[0086] The methods and systems of the present invention can be implemented in many ways. For example, the methods and systems of the present invention can be implemented by software, hardware, firmware, or any combination of software, hardware, and firmware. The above order of steps for the methods is only for illustration. The steps of the methods of the present invention are not limited to the specific order described above, unless otherwise specifically stated. In addition, in some embodiments, the present invention can also be implemented as a program recorded on a recording medium, and these programs include machine-readable instructions for implementing the methods according to the present invention. Therefore, the present invention also covers a recording medium storing a program for executing the methods according to the present invention.

[0087] It should also be noted that in the systems, equipment, and methods of the present invention, each component or each step can be decomposed and / or recombined. These decompositions and / or recombinations should be regarded as equivalent solutions of the present invention. The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these aspects are very obvious to those skilled in the art, and the general principles defined herein can be applied to other aspects without departing from the scope of the present invention. Therefore, the present invention is not intended to be limited to the aspects shown herein, but rather to the broadest scope consistent with the principles and novel features disclosed herein.

[0088] The above description has been given for purposes of illustration and description. In addition, this description is not intended to limit the embodiments of the present invention to the forms disclosed herein. Although multiple example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, changes, additions, and sub-combinations thereof.

Claims

1. An integration method for a reconfigurable 3D chip, characterized in that, Including: Designing the architecture of a reconfigurable 3D chip; Performing semiconductor manufacturing on the reconfigurable computing logic chip of the reconfigurable 3D chip to obtain an uncut reconfigurable logic wafer; According to the architecture of the reconfigurable 3D chip, bonding the reconfigurable logic wafer and the memory wafer face-to-face using a hybrid technology, and connecting the signal IOs of the reconfigurable logic wafer and the signal IOs of the memory wafer together; Cutting the bonded stacked chips to obtain independent stacked wafers; Packaging the stacked wafers to obtain the reconfigurable 3D chip; According to the architecture of the reconfigurable 3D chip, developing and verifying the RTL code of the reconfigurable 3D chip to determine the chip RTL code; Performing semiconductor manufacturing on the reconfigurable computing logic chip of the reconfigurable 3D chip to obtain an uncut reconfigurable logic wafer, including: According to the architecture of the reconfigurable 3D chip, performing logic synthesis on the reconfigurable 3D chip to obtain the gate-level netlist of the reconfigurable 3D chip; Performing placement and routing on the reconfigurable computing logic chip of the reconfigurable 3D chip according to the gate-level netlist to determine the GDS file of the reconfigurable computing logic chip; According to the GDS file, performing semiconductor manufacturing on the GDS of the reconfigurable computing logic chip to obtain an uncut reconfigurable logic wafer.

2. The method according to claim 1, characterized in that According to the architecture of the reconfigurable 3D chip, bonding the reconfigurable logic wafer and the memory wafer face-to-face using a hybrid technology, and connecting the signal IOs of the reconfigurable logic wafer and the signal IOs of the memory wafer together, including: Determining the hybrid bonding scheme of the reconfigurable computing logic chip according to the hybrid bonding rules of the reconfigurable 3D chip architecture; According to the hybrid bonding scheme, bonding the reconfigurable logic wafer and the memory wafer face-to-face using a hybrid technology, and connecting the signal IOs of the reconfigurable logic wafer and the signal IOs of the memory wafer together.

3. A reconfigurable 3D chip obtained by an integration method of the reconfigurable 3D chip according to any one of claims 1-2, characterized in that, Including: A reconfigurable computing die and a memory die disposed on the top layer of the reconfigurable computing die, where The memory die includes a plurality of memory cells, each reconfigurable computing unit of the reconfigurable computing die is configured with an independent memory cell, and the reconfigurable computing unit and its corresponding memory cell are connected in a tightly coupled manner.

4. The reconfigurable 3D chip according to claim 3, wherein Data transfer is achieved among multiple reconfigurable computing units by using a data flow computing mode.

5. The reconfigurable 3D chip according to claim 3, characterized in that, The memory die is a single-layer or multi-layer stacked memory.

6. The reconfigurable 3D chip according to claim 5, wherein, The memory cell is one or more logical storage blocks.

7. The reconfigurable 3D chip according to claim 3, wherein The reconfigurable computing units inside the reconfigurable computing die form a two-dimensional array.

8. The reconfigurable 3D chip according to claim 3, wherein The memory die on the top layer and the reconfigurable computing die on the bottom layer are directly stacked and signal connection is achieved through through-silicon vias or hybrid bonding technology.

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