Through-hole manufacturing method

Abstract

Embodiments of the present disclosure relate to via manufacturing methods. A method for manufacturing an insulating conductive via is presented. The via passes through a first stack of layers to a first layer. A first cavity partially extending into the first stack of layers is formed. A second stack of layers is formed over the first stack of layers and in the first cavity. The second stack of layers includes an etch stop layer and an insulating layer. A second cavity extending completely through the stack of first layers and the stack of second layers to the first layer is then formed. An insulating liner then covers the walls and the bottom of the second cavity. The insulating liner is then anisotropically etched and the second cavity is filled with a conductive material forming a core of the via.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Greek Patent Application No. 20210100851, filed on 7 December 2021, and to French Patent Application No. 2200140, filed on 10 January 2022, the entire contents of which are incorporated herein by reference to the fullest extent permitted by law. Technical Field

[0003] This disclosure generally relates to electronic devices and methods of manufacturing the same, and more specifically, to through-holes and methods of manufacturing the same. Background Technology

[0004] The fabrication of vias, especially conductive vias, is an element present in most electronic device manufacturing methods.

[0005] Electronic devices are becoming increasingly smaller. This necessitates smaller vias, which in turn requires more precise manufacturing methods.

[0006] It is necessary to know all or part of the disadvantages of through-hole manufacturing methods in this field. Summary of the Invention

[0007] In one embodiment, a method is provided for fabricating an insulating conductive via through a first stack of layers reaching a first layer. The first stack includes at least a second conductive or semiconductor layer. The method includes: a) forming a first cavity in the first stack, the first cavity partially penetrating the second layer; b) forming a second stack including a third etch stop layer covering an upper surface of the first stack and the walls and bottom of the first cavity with a fourth insulating layer; c) etching a second cavity through the first and second stacks, the second cavity extending between the bottom of the first cavity and the first layer; d) forming a fifth insulating layer covering the second stack and the walls and bottom of the second cavity; e) anisotropically etching the fifth layer to form an insulating sheath of the via on the walls of the second cavity, the etching selectively etching the material of the fifth layer over the material of the third layer; and f) filling the second cavity with a conductive material to form a conductive core of the via.

[0008] According to one embodiment, step f) further includes filling the first cavity with a conductive material.

[0009] According to an embodiment, the first layer is made of a conductive material or a semiconductor material.

[0010] According to one embodiment, step c) includes photolithography.

[0011] According to an embodiment, the materials of the fourth layer and the fifth layer can be selectively etched onto the material of the first layer.

[0012] According to one embodiment, the fourth and fifth layers are made of silicon oxide, and the second layer is made of silicon.

[0013] According to an embodiment, the method includes a step of removing the third layer between steps e) and f).

[0014] According to an embodiment, the third layer is made of a material that can be selectively etched onto the material of the first layer.

[0015] According to one embodiment, the third layer is made of amorphous carbon.

[0016] According to an embodiment, the first stack has a thickness greater than or equal to 6 μm.

[0017] According to an embodiment, the first stack includes at least one sixth layer made of insulating material between the first layer and the second layer.

[0018] According to one embodiment, the second stack includes a seventh layer made of insulating material between the third layer and the first stack.

[0019] According to one embodiment, the material of the third layer can be selectively etched on the seventh layer.

[0020] According to one embodiment, the first stack includes at least one eighth layer located between the second layer and the second stack. Attached Figure Description

[0021] The foregoing features and advantages, as well as other features and advantages, will be described in detail in the remainder of the disclosure of specific embodiments given by way of illustration and not limitation, with reference to the accompanying drawings, wherein:

[0022] Figures 1 to 8 The steps of a through-hole manufacturing method are shown. Detailed Implementation

[0023] In the various figures, the same features are indicated by the same reference numerals. In particular, common structural and / or functional features in the various embodiments may have the same reference numerals and may have the same structure, dimensions, and material properties.

[0024] For clarity, only the steps and elements useful for understanding the embodiments described herein are shown and described in detail.

[0025] Unless otherwise stated, when referring to two elements connected together, it means that there is no direct connection between them except for the conductor, and when referring to two elements connected together, it means that the two elements can be connected or they can be coupled through one or more other elements.

[0026] In the following disclosure, unless otherwise stated, when referring to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or when referring to relative position qualifiers, such as the terms "up", "down", "above", "below", etc., or when referring to orientation qualifiers, such as "horizontal", "vertical", etc., the orientation shown in the figure is used.

[0027] Unless otherwise stated, the expressions “about,” “approximately,” “basically,” and “in the order of…” indicate within 10%, preferably within 5%.

[0028] Unless otherwise stated, the terms “insulating” or “conducting” should be understood as “electrically insulating” and “conducting”.

[0029] Figures 1 to 8 The method for forming vias or connecting pads (preferably conductive vias) in at least one conductive layer is shown, preferably in a sequential manner. The vias formed by this method are insulating vias, and therefore include an insulating sheath and a conductive core.

[0030] Figure 1 The steps of a method for manufacturing a through-hole, preferably a conductive through-hole, are shown.

[0031] During this step, a stack of layers 10 is formed. The stack of layers 10 includes a lower layer 12 and a stack of layers 10' located on top of layer 12. The stack of layers 10' corresponds to the layers through which vias pass, allowing the vias to reach layer 12. Therefore, the stack of layers 10' contacts layer 12 at the location where the vias are formed. The stack of layers 10' has, for example, a thickness greater than or equal to 6 μm.

[0032] Layer 12 is, for example, a conductive or semiconductor layer. Layer 12 is preferably a conductive layer, and more preferably a metal layer made of, for example, copper.

[0033] The stack of layers 10' includes at least one conductive or semiconductor layer 14. Layer 14 is preferably a semiconductor layer, such as a silicon layer. Layer 14 extends over layer 12.

[0034] exist Figure 1 In the example, layer stack 10' includes a lower layer 16 below layer 14. Layer 16 is the layer in stack 10' that is closest to layer 12. Figure 1 In the example, layer 16 is in contact with layer 12. Layer 16 is preferably made of an insulating material.

[0035] exist Figure 1In the example, layer stack 10' includes an upper layer 18 above layer 14. Layer 18 is the layer of layer stack 10' that is furthest from layer 12. Therefore, the upper surface of layer 18 corresponds to the upper surface of layer stack 10' and layer stack 10, i.e., the surface furthest from layer 12. Figure 1 In the example, layer 18 is in contact with layer 14. Layer 16 is made of, for example, an insulating material or a conductive or semiconductor material.

[0036] The layer stack 10' may, for example, include one or more layers (not shown) located between layer 16 and layer 14. The layer stack 10' may, for example, include one or more layers (not shown) located between layer 18 and layer 14. According to another embodiment, the layer stack 10' includes only layer 14.

[0037] Figure 2 Another step in the through-hole manufacturing method is shown.

[0038] During this step, a cavity 20 is formed in the layer stack 10' at the location where the via is provided. The cavity 20 is formed, for example, by a photolithography step.

[0039] Cavity 20 extends from the upper surface of the stack of layers 10, through layer 18 (if present), and reaches layer 14. Preferably, cavity 20 extends partially within layer 14. In other words, cavity 20 passes through layer 18 and extends within layer 14. The bottom of cavity 20 is located within layer 14. The bottom of cavity 20 is separated from layer 12 by a portion of layer 14.

[0040] The bottom dimension of cavity 20 is larger than the required dimension of the through hole in the bottom plane of cavity 20.

[0041] Figure 3 Another step in the through-hole manufacturing method is shown.

[0042] During this step, in the presence of Figure 2 The steps obtained result in a stack of layers 22, i.e., for example, in a structure formed by... Figure 2 The steps involved in this process resulted in a continuous stack of layers 22. In other words, the stack of layers 22 covers the upper surface of the stack of layers 10' as well as the walls and bottom of the cavity 20. Figure 3 In the example, the stack of layers 22 includes layers 24, 26, and 28.

[0043] Layer 24 is an electrically insulating layer, for example, made of an oxide such as silicon oxide. Layer 24 is the lower layer of the layer stack 22, that is, the layer closest to layer 12. Layer 24 is in contact with the upper surface of the layer stack 10', the walls of the cavity 20, and the bottom of the cavity 20.

[0044] Layer 26, the intermediate layer of the stack 22 forming layers, preferably completely covers layer 24. Layer 26 at least covers layer 24 in cavity 20.

[0045] Layer 28, the uppermost layer of the stack 22 forming layers, i.e., the layer furthest from layer 12, preferably completely covers layer 26. Layer 28 at least covers layer 26 in cavity 20. Thus, layer 26 is located between layers 24 and 28. Layer 28 is, for example, an electrically insulating layer made of the same material as layer 24. Layer 28 is able to protect layer 26.

[0046] Layer 26 is made of a material that can be selectively etched onto the material of layer 12. In other words, there is an etching method for etching the material of layer 26 at a rate at least twice that of etching the material of layer 12. The material of layer 26 can also be selectively etched onto the material of layer 24. In other words, there is an etching method for etching the material of layer 26 at a rate at least twice that of etching the material of layer 24. Furthermore, the material of layer 14 can be selectively etched onto the material of layer 28. In other words, there is an etching method for etching the material of layer 14 at a rate at least twice that of etching the material of layer 28. The material of layer 28 can be selectively etched onto the materials of layers 12 and 26. In other words, there is a method for etching the material of layer 28 at a rate at least twice that of etching the materials of layers 12 and 26. Layer 26 is made of, for example, amorphous carbon.

[0047] More generally, the stack of layers 22 includes at least layers 26 and 28. Layer 24 may be omitted.

[0048] Figure 4 Another step in the through-hole manufacturing method is shown.

[0049] During this step, in the presence of Figure 3 A photomask 30 is formed on the structure produced by the steps. The mask 30 is made of resin, for example.

[0050] The mask 30 includes an opening 32 at the level of the cavity 20. This opening extends through the mask 30 to the layer stack 22 at the bottom of the cavity 20. In other words, the opening 32 partially exposes the layer stack 22 at the bottom of the cavity 20. The dimension of the opening 32 in the bottom plane of the cavity 20 is smaller than the dimension of the bottom of the cavity 20.

[0051] Figure 5 Another step in the through-hole manufacturing method is shown.

[0052] Figure 5 The steps include etching the stack 22 of layers through the opening 32. This etching step also causes at least a partial etching of the resin mask 30.

[0053] Then, Figure 5The steps include etching through opening 32 the portion of stack 10' located in front of opening 32. This etching step forms a cavity 34 in the stack of layers 22 and 10'. The cavity 34 reaches layer 12 and thus exposes the portion of layer 12 in front of opening 32.

[0054] Etching layer 14 preferably removes the remaining portion of mask 30. Etching layer 14 may result in partial etching of layer 28. The thickness of layer 28 and mask 30 are preferably chosen such that layer 26 is completely covered by layer 28 after the layer stack 10' is etched. Therefore, layer 26 is preferably not exposed during the etching of the layer stack 10'.

[0055] Figure 6 Another step in the through-hole manufacturing method is shown.

[0056] During this step, in the presence of Figure 5 An insulating layer 36 is formed on the structure produced by the steps. Layer 36 is made of the same material as layer 28.

[0057] Layer 36 conformally covers the structure. In other words, layer 36 covers the upper surface of layer 28 as well as the walls and bottom of cavity 34.

[0058] A portion of layer 36 located on the wall of cavity 34 is designed to form a sheath for the via, i.e., to insulate the conductive via from the layers of the stack 10', particularly layer 14. Therefore, the thickness of layer 36 is insufficient to completely fill cavity 34.

[0059] Figure 7 Another step in the through-hole manufacturing method is shown.

[0060] This step includes anisotropic etching of layers 28 and 36. Therefore, portions of layers 28 and 36 located on layer 26 are etched. The portion of layer 36 located at the bottom of cavity 34, i.e., the portion in contact with layer 12, is etched. Thus, layer 12 is exposed. Similarly, layer 26 is exposed. Preferably, the upper surface of layer 26 is completely exposed. The portion of layer 36 located on the wall of cavity 34 is not removed. In particular, the sidewall of layer 14 is separated from cavity 34 through the portion of layer 36.

[0061] The etching is a selective etching of the materials of layers 28 and 36. Therefore, the etching prevents the materials of layers 26 and 12 from being etched during the etching of layers 28 and 36. Thus, layer 26 protects its portion positioned on the layer stack 10 during the etching of layers 28 and 36, and ensures that portions of layers 28 and 36 not on the sidewalls of cavity 34 can be completely removed.

[0062] Figure 8 Another step in the through-hole manufacturing method is shown.

[0063] During this step, layer 26 is etched, for example, by oxygen or hydrogen plasma. Since the material of layer 26 can be selectively etched onto the materials of layers 24 and 12, layers 24 and 12 are not etched or destroyed in this step.

[0064] Furthermore, a conductive core 38 forms a through-hole. For example, the core 38 completely fills cavities 34 and 20. The core preferably extends from layer 12 to the level of the upper surface of layer 24. Thus, the core 38 contacts layer 12 through its lower surface.

[0065] The core 38 is formed, for example, by an inlay method, i.e., depositing a layer of core material having a thickness sufficient to fill cavities 20 and 34, and then chemically mechanically polishing the layer to remove it from cavities 20 and 34. For example, chemical mechanical polishing is a method that allows selective etching of the material of the core 38 onto layers 18 and 24.

[0066] As a variation, the core may completely fill cavity 34 but not completely fill cavity 20. For example, the outer portion of cavity 20 may not be filled with core 38.

[0067] Vias can be formed without forming the stack 22 of layers. A photolithography step must then be added to remove a portion of layer 36 located at the bottom of cavity 36. The lateral dimension of cavity 34 must be large enough to allow for the formation of a photomask.

[0068] The advantages of the described embodiments are that they allow for better control over the shape factor of the vias, particularly in forming vias with smaller horizontal dimensions and deeper vias.

[0069] Another advantage of the described embodiments is that they require fewer steps, especially fewer photolithography steps.

[0070] Another advantage of this embodiment is the self-alignment of the vias and connecting tracks. This allows for a reduction in the size of the interconnect network during its fabrication.

[0071] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations can be combined, and other variations will occur to those skilled in the art.

[0072] Finally, based on the functional indications given above, the actual implementation of the described embodiments and variations is within the capabilities of those skilled in the art.

Claims

1. A manufacturing method, comprising: a) A first cavity is formed in a first stack of layers, wherein the first stack of layers includes at least one conductive or semiconductor layer and a first layer, and the first cavity in the first stack of layers partially passes through the at least one conductive or semiconductor layer; b) A second stack of layers is formed on the upper surface of the first stack of layers and on the walls and bottom of the first cavity, the second stack of layers including an etch stop layer covered by a first insulating layer; c) Etching a second cavity through a first stack of the layers and a second stack of the layers, the second cavity extending between the bottom of the first cavity and the first layer; d) Forming a second insulating layer that covers the second stack of the layers and the walls and bottom of the second cavity; e) Anisotropically etch the second insulating layer to form an insulating sheath on the wall of the second cavity, wherein the anisotropic etching selectively etches the material of the second insulating layer over the material of the etch stop layer; as well as f) Fill the second cavity with a conductive material to form a conductive core that passes through the first stack of the layers to reach the insulating conductive via of the first layer.

2. The method according to claim 1, wherein step f) further includes filling the first cavity with a conductive material.

3. The method according to claim 1, wherein the first layer is made of a conductive material or a semiconductor material.

4. The method of claim 1, wherein step c) includes defining the position of the second cavity by photolithography prior to etching.

5. The method of claim 1, wherein the materials of the first insulating layer and the second insulating layer are selectively etched over the material of the first layer.

6. The method of claim 1, wherein the first insulating layer and the second insulating layer are made of silicon oxide, and wherein the at least one conductive or semiconductor layer is made of silicon.

7. The method of claim 1, further comprising removing the etch stop layer between step e) and step f).

8. The method of claim 1, wherein the etch stop layer is made of a material that can be selectively etched over the material of the first layer.

9. The method of claim 1, wherein the etch stop layer is made of amorphous carbon.

10. The method of claim 1, wherein the first stack of the layers has a thickness greater than or equal to 6 μm.

11. The method of claim 1, wherein the first stack of the layers includes at least one insulating layer between the first layer and the at least one conductive or semiconductor layer.

12. The method of claim 1, wherein the second stack includes another insulating layer located between the etch stop layer and the first stack.

13. The method of claim 12, wherein the material of the etch stop layer can be selectively etched over the other insulating layer.

14. The method of claim 1, wherein the first stack of layers comprises at least one layer made of an insulating material or a conductive or semiconductor material, the at least one layer being located between the at least one conductive or semiconductor layer and a second stack of layers.

15. A method for manufacturing an insulating conductive via, comprising: A first stack of layers is formed on a substrate conductive or semiconductor layer, the first stack of layers comprising a conductive or semiconductor layer; Forming a first cavity that partially extends through the first stack of the conductive or semiconductor layers; A second stack of layers is formed on top of the first stack of layers and within the first cavity; The second stack of the layers includes an etch stop layer covered with an insulating layer; A mask is formed on the second stack of the insulating layer of the layer, the mask having an opening aligned with the first cavity but having a smaller size than the first cavity; The second cavity is etched using the opening in the mask, the second cavity extending completely through the second stack of the layers and further extending completely through the remaining portion of the conductive or semiconductor layer through the first stack of the layers to reach the substrate conductive or semiconductor layer; An insulating bushing is conformally deposited within the second cavity; The insulating bushing is anisotropically etched, wherein the anisotropic etching selectively etches the material of the insulating bushing over the material of the etch stop layer; as well as The second cavity is filled with a conductive core.

16. The method of claim 15, further comprising removing the second stack of the etch stop layer after anisotropic etching and before filling the second cavity.

17. The method of claim 15, wherein the etch stop layer is made of a material that can be selectively etched over the conductive or semiconductor layer of the substrate.

18. The method of claim 15, wherein the etch stop layer is made of amorphous carbon.

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