A method of manufacturing a semiconductor device

Abstract

The application discloses a semiconductor device manufacturing method, and relates to the technical field of semiconductors, which aims to reduce the manufacturing difficulty of a three-dimensional stacked complementary transistor and improve the working performance of the three-dimensional stacked complementary transistor. The semiconductor device manufacturing method comprises the following steps: performing a patterning treatment on a semiconductor substrate to form a fin structure on the semiconductor substrate. The fin structure comprises a first fin part, a second fin part and a third fin part arranged in sequence along the thickness direction of the semiconductor substrate. A shallow trench isolation layer is formed on the semiconductor substrate. An ion implantation process is adopted to perform a doping treatment on the second fin part at a first implantation angle. An ion implantation process is adopted to perform a doping treatment on the third fin part at a second implantation angle. A back-etching treatment is performed on the shallow trench isolation layer to expose the second fin part. A first ring gate transistor is formed based on the second fin part, and a second ring gate transistor is formed based on the third fin part. The first ring gate transistor and the second ring gate transistor constitute a three-dimensional stacked complementary transistor.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and particularly relates to a manufacturing method of semiconductor device. BACKGROUND

[0002] The three-dimensional stacked complementary transistor comprises vertically stacked N-type transistor and P-type transistor, eliminates the lateral spacing of N-type transistor and P-type transistor, which allows further increasing the effective channel width, thereby improving the working performance and integration of the semiconductor device.

[0003] However, the existing manufacturing method of three-dimensional stacked complementary transistor has high requirement on processing technology, which leads to great difficulty in manufacturing the three-dimensional stacked complementary transistor, and is not conducive to improving the working performance of the three-dimensional stacked complementary transistor. SUMMARY

[0004] The present application relates to the technical field of semiconductor, and particularly relates to a manufacturing method of semiconductor device.

[0005] In order to achieve the above-mentioned purpose, the present application provides a manufacturing method of semiconductor device, which comprises:

[0006] The semiconductor substrate is subjected to a patterning process to form a fin structure on the semiconductor substrate. The fin structure comprises a first fin portion, a second fin portion and a third fin portion arranged in sequence along the thickness direction of the semiconductor substrate. There is a notch structure inwardly recessed along the width direction of the fin structure at least between the first fin portion and the second fin portion, and between the second fin portion and the third fin portion.

[0007] A shallow trench isolation layer is formed on the semiconductor substrate. The top height of the shallow trench isolation layer is greater than or equal to the top height of the second fin portion and less than or equal to the top height of the third fin portion.

[0008] The second fin portion is subjected to a doping process by using an ion implantation process and at a first implantation angle.

[0009] The third fin portion is subjected to a doping process by using an ion implantation process and at a second implantation angle. The second implantation angle is different from the first implantation angle.

[0010] The shallow trench isolation layer is subjected to a back etching process to expose the second fin portion. The remaining part of the shallow trench isolation layer forms a shallow trench isolation structure.

[0011] A first ring gate transistor is formed based on the second fin portion, and a second ring gate transistor is formed based on the third fin portion. The first ring gate transistor and the second ring gate transistor constitute a three-dimensional stacked complementary transistor.

[0012] Compared with the prior art, the manufacturing method of the semiconductor device provided by the application is characterized in that the second fin for manufacturing the first ring-gate transistor and the third fin for manufacturing the second ring-gate transistor are obtained by patterning the semiconductor substrate, and both of them belong to the semiconductor substrate. In other words, in the actual manufacturing process, the manufacturing method provided by the application can form the second fin and the third fin without using epitaxy and bonding processes, thereby solving the problem that it is difficult to obtain a three-dimensional complementary transistor that meets the requirements in the stress distribution and stress matching between thin films in the monolithic method for manufacturing the three-dimensional complementary transistor, and solving the problem that the bonding scheme is difficult to align in the sequential method for manufacturing the three-dimensional complementary transistor, reducing the manufacturing difficulty of the three-dimensional complementary transistor, and further improving the working performance of the three-dimensional complementary transistor.

[0013] In addition, after the shallow trench isolation layer is formed, the ion implantation process is used to dope the second fin by scattering impurities in the shallow trench isolation layer at a first implantation angle. Moreover, the second fin and the third fin are doped with impurities of opposite conductive types by changing the implantation angle of the ion implantation process to a second implantation angle, thereby further reducing the manufacturing difficulty of the three-dimensional complementary transistor. After the shallow trench isolation layer is etched back, a shallow trench isolation structure for isolating different active regions of the semiconductor substrate is formed, and there is no need to form a corresponding mask layer for doping the second fin and the third fin with impurities of different conductive types, thereby simplifying the manufacturing process of the three-dimensional complementary transistor. BRIEF DESCRIPTION OF DRAWINGS

[0014] The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application. In the drawings:

[0015] Figure 1 A flow chart of the manufacturing method of the semiconductor device provided by the embodiment of the application;

[0016] Figure 2 A structure schematic of the manufacturing method of the semiconductor device provided by the embodiment of the application in the process of manufacturing the semiconductor device Figure 1 ;

[0017] Figure 3 A structure schematic of the manufacturing method of the semiconductor device provided by the embodiment of the application in the process of manufacturing the semiconductor device Figure 2 ;

[0018] Figure 4Fig. 1 is a schematic diagram of a structure in a process of manufacturing a semiconductor device according to an embodiment of the present application. Figure 3 ;

[0019] Figure 4 Fig. 2 is a schematic diagram of a structure in a process of manufacturing a semiconductor device according to an embodiment of the present application. Figure 5 ;

[0020] Figure 5 Fig. 3 is a schematic diagram of a structure in a process of manufacturing a semiconductor device according to an embodiment of the present application. Figure 6 ;

[0021] Figure 6 Fig. 4 is a schematic diagram of a structure in a process of manufacturing a semiconductor device according to an embodiment of the present application. Figure 7 ;

[0022] Figure 7 Fig. 5 is a schematic diagram of a structure in a process of manufacturing a semiconductor device according to an embodiment of the present application. Figure 8 ;

[0023] Figure 8 Fig. 6 is a schematic diagram of a structure in a process of manufacturing a semiconductor device according to an embodiment of the present application. Figure 9 ;

[0024] Figure 9 Fig. 7 is a schematic diagram of a structure in a process of manufacturing a semiconductor device according to an embodiment of the present application. Figure 10 ;

[0025] Figure 10 Fig. 8 is a schematic diagram of a structure in a process of manufacturing a semiconductor device according to an embodiment of the present application. Figure 11 ;

[0026] Figure 11 Fig. 9 is a schematic diagram of a structure in a process of manufacturing a semiconductor device according to an embodiment of the present application. Figure 12 ;

[0027] Figure 12 Fig. 10 is a schematic diagram of a structure in a process of manufacturing a semiconductor device according to an embodiment of the present application. Figure 13 ;

[0028] Figure 13 Fig. 11 is a schematic diagram of a structure in a process of manufacturing a semiconductor device according to an embodiment of the present application. Figure 14 ;

[0029] Figure 14 Fig. 8 is a schematic diagram of a structure in a process of manufacturing a semiconductor device according to an embodiment of the present application. Figure 15 Four;

[0030] Figure 15 Fig. 8 is a schematic diagram of a structure in a process of manufacturing a semiconductor device according to an embodiment of the present application. Figure 16 Five;

[0031] Figure 16 Fig. 8 is a schematic diagram of a structure in a process of manufacturing a semiconductor device according to an embodiment of the present application. Figure 17 Six;

[0032] Figure 17 Fig. 8 is a schematic diagram of a structure in a process of manufacturing a semiconductor device according to an embodiment of the present application. Figure 18 Seven;

[0033] Figure 18 Fig. 8 is a schematic diagram of a structure in a process of manufacturing a semiconductor device according to an embodiment of the present application. Figure 19 Eight.

[0034] The reference numerals: 11 is a semiconductor substrate, 12 is a first channel pre-formation structure, 13 is a passivation layer, 14 is a notch structure, 15 is a fin structure, 16 is a first fin portion, 17 is a second fin portion, 18 is a third fin portion, 19 is a shallow trench isolation layer, 20 is a shallow trench isolation structure, 21 is a first semiconductor region, 22 is a second semiconductor region, 23 is a third semiconductor region, 24 is a sacrificial oxide layer, 25 is a second channel pre-formation structure, 26 is an oxide capping layer, 27 is a sacrificial gate, 28 is a sidewall, 29 is a source region, 30 is a drain region, 31 is an isolation layer, 32 is a dielectric layer, 33 is a channel region, 34 is a nanostructure, and 35 is a gate stack structure. DETAILED DESCRIPTION

[0035] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood, however, that the description which follows is merely exemplary and is not intended to limit the scope of the present disclosure. Further, in the following description, description of well-known structures and techniques is omitted to avoid obscuring the concept of the present disclosure.

[0036] Various structural diagrams according to embodiments of the present disclosure are shown in the drawings. These diagrams are not drawn to scale in which certain details are exaggerated for clarity of presentation and may have been omitted. The shapes and relative sizes of the various regions, layers, and elements illustrated in the figures are exemplary only and can vary in actual implementation depending on manufacturing techniques and tolerances. The same reference numbers in different drawings represent the same or similar elements.

[0037] In the context of the present disclosure, when a layer / element is said to be located "on" another layer / element, the layer / element can be directly on the other layer / element, or there can be an intervening layer / element therebetween. In addition, if a layer / element is located "on" another layer / element in one orientation, it can be located "under" the other layer / element when the orientation is reversed. In order to make the technical problems to be solved by the present application, technical solutions and beneficial effects more clear, the present application will be further described in detail below in conjunction with the drawings and embodiments. It should be understood that the specific embodiments described herein are merely intended to explain the present application and not to limit the present application.

[0038] In addition, the terms "first", "second", etc. are used only for the purpose of description and should not be understood as indicating or implying relative importance or an implied indication of the number of technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise explicitly specified and limited. The meaning of "several" is one or more, unless otherwise explicitly specified and limited.

[0039] In the description of the present application, it should be noted that, unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connecting" should be understood broadly, for example, it can be fixed connection, or detachable connection, or integrally connected; it can be mechanical connection, or electrical connection; it can be directly connected, or indirectly connected through intermediate medium, it can be the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0040] The three-dimensional stacked complementary transistor includes vertically stacked N-type transistors and P-type transistors, eliminates the lateral spacing of N-type transistors and P-type transistors, which allows further increasing the effective channel width, thereby facilitating the improvement of the working performance and integration of semiconductor devices.

[0041] However, the existing manufacturing method of the three-dimensional stacked complementary transistor has high requirements on the processing technology, which leads to high difficulty in manufacturing the three-dimensional stacked complementary transistor, and is not conducive to improving the working performance of the three-dimensional stacked complementary transistor. Among them, the existing manufacturing method of the three-dimensional stacked complementary transistor mainly has the following two integration schemes:

[0042] The first kind: a monolithic way is used to manufacture the three-dimensional stacked complementary transistor. Specifically, taking the N-type transistor and the P-type transistor as both ring gate transistors and the P-type transistor being located above the N-type transistor as an example, the process of manufacturing the three-dimensional stacked complementary transistor by using the existing manufacturing method is described: first, a fin structure is formed on a semiconductor substrate. The fin structure includes at least two layers of stacks. Each layer of stack includes a sacrificial layer and a channel layer located on the sacrificial layer, and the materials of the sacrificial layer and the channel layer are both semiconductor materials. Then, a sacrificial gate and a side wall are formed across part of the fin structure. The fin structure is selectively etched with the sacrificial gate and the side wall as a mask to remove the part of the fin structure exposed outside the sacrificial gate and the side wall. Then, a first semiconductor material for manufacturing the source region and the drain region included in the N-type transistor is formed on the semiconductor substrate. At this time, because the remaining parts of the sacrificial layer and the channel layer corresponding to the N-type transistor and the P-type transistor are exposed after being etched, the remaining parts of the sacrificial layer and the channel layer can all serve as seed layers for epitaxial growth of the first semiconductor material, so the first semiconductor material is formed not only on both sides of the remaining parts of the sacrificial layer and the channel layer corresponding to the N-type transistor, but also on both sides of the remaining parts of the sacrificial layer and the channel layer corresponding to the P-type transistor. Then, the first semiconductor material located on both sides of the remaining parts of the sacrificial layer and the channel layer corresponding to the P-type transistor needs to be removed, and the remaining part of the first semiconductor material forms the source region and the drain region included in the N-type transistor. Then, an epitaxial isolation layer is formed on the source region and the drain region included in the N-type transistor and covering the surface away from the substrate; and a source region and a drain region of the P-type transistor are formed on the epitaxial isolation layer by using an epitaxial growth process. Finally, the sacrificial gate and the part of the sacrificial layer located in the gate formation region are removed; and a gate stack structure is formed around the outer periphery of the channel region to obtain the three-dimensional stacked complementary transistor.

[0043] The second kind: a sequential way is used to manufacture the three-dimensional stacked complementary transistor. This way is to form a transistor of a bottom layer according to the manufacturing process of a conventional semiconductor device, and after forming the corresponding contact electrode of the transistor of the bottom layer, a wafer transfer method is used to cover a semiconductor layer on the top of the transistor of the bottom layer by using a wafer-to-wafer bonding technology. Then, the transistor of a top layer is integrated based on the semiconductor layer, the top gate and the bottom gate are connected, and the three-dimensional stacked complementary transistor is obtained.

[0044] From the manufacturing process of the first mode, in the first mode of manufacturing the three-dimensional complementary transistor, the channel layer and the sacrificial layer of the semiconductor material are formed by epitaxy. The epitaxial material needs to consider the stress distribution and stress matching between thin films, which brings great technical challenges to the manufacturing of the three-dimensional complementary transistor. The bonding scheme in the second mode of manufacturing the three-dimensional complementary transistor has technical challenges such as alignment, and the process requirements are also higher, which makes the manufacturing of the three-dimensional complementary transistor more difficult and is not conducive to improving the working performance of the three-dimensional complementary transistor.

[0045] To solve the above technical problems, an embodiment of the present application provides a semiconductor device manufacturing method. In the semiconductor device manufacturing method provided by the embodiment of the present application, the second fin for manufacturing the first ring gate transistor and the third fin for manufacturing the second ring gate transistor are obtained by patterning the semiconductor substrate. And by changing the injection angle of the ion implantation process, the second fin and the third fin can be doped with impurities of opposite conductivity types, respectively, thereby reducing the difficulty of manufacturing the three-dimensional complementary transistor.

[0046] As shown in Figure 19 , an embodiment of the present application provides a semiconductor device manufacturing method. Specifically, the semiconductor device manufactured by the manufacturing method includes a three-dimensional complementary transistor. As shown in Figure 1 , the three-dimensional complementary transistor includes a semiconductor substrate 11, a first ring gate transistor formed on the semiconductor substrate 11, and a second ring gate transistor formed above the first ring gate transistor. It can be understood that the conductivity types of the first ring gate transistor and the second ring gate transistor are opposite. The conductivity type of the first ring gate transistor can be N-type, and the conductivity type of the second ring gate transistor is P-type. Alternatively, the conductivity type of the first ring gate transistor can also be P-type, and the conductivity type of the second ring gate transistor is N-type.

[0047] From the aspect of device type, the first ring gate transistor can be a junctionless ring gate transistor. At this time, the doping type of the impurities in the source region, the drain region and the channel region included in the first ring gate transistor is the same. Alternatively, the first ring gate transistor can also be a junction ring gate transistor. At this time, the doping type of the source region and the drain region included in the first ring gate transistor is opposite to the doping type of the channel region included in the first ring gate transistor.

[0048] As for the above-mentioned second ring gate transistor, the second ring gate transistor can be a junctionless ring gate transistor. At this time, the doping type of the impurities in the source region, the drain region and the channel region included in the second ring gate transistor is the same. Alternatively, the second ring gate transistor can also be a junction ring gate transistor. At this time, the doping type of the source region and the drain region included in the second ring gate transistor is opposite to the doping type of the channel region included in the second ring gate transistor.

[0049] Preferably, the first ring gate transistor and the second ring gate transistor are both junctionless ring gate transistors. In this case, the source region, the drain region and the channel region of the first ring gate transistor can be doped simultaneously, and the source region, the drain region and the channel region of the second ring gate transistor can be doped simultaneously, further simplifying the manufacturing process of the three-dimensional stacked complementary transistor.

[0050] From the structural aspect, as shown in Figure 19 and Figure 18 , the channel region 33 of the first ring gate transistor includes at least one layer of nanostructures 34. Each layer of nanostructures 34 has a gap between the semiconductor substrate 11. When the channel region 33 of the first ring gate transistor includes at least two layers of nanostructures 34, all the nanostructures 34 of the channel region 33 of the first ring gate transistor are spaced apart along the thickness direction of the semiconductor substrate 11.

[0051] As for the second ring gate transistor, the channel region of the second ring gate transistor includes at least one layer of nanostructures. Each layer of nanostructures has a gap between the nanostructures at the top layer in the first ring gate transistor. When the channel region of the second ring gate transistor includes at least two layers of nanostructures, all the nanostructures of the channel region of the second ring gate transistor are spaced apart along the thickness direction of the semiconductor substrate. In addition, the number of layers of nanostructures in the second ring gate transistor can be the same as or different from the number of layers of nanostructures in the first ring gate transistor.

[0052] Based on the above, the manufacturing process of the semiconductor device will be described below according to the perspective view or sectional view of the operation shown in Figure 19 . Specifically, the manufacturing method of the semiconductor device includes the following steps:

[0053] First, as shown in Figures 2 to 19 , the semiconductor substrate 11 is subjected to a patterning process to form a fin structure 15 on the semiconductor substrate 11. The fin structure 15 includes a first fin portion 16, a second fin portion 17 and a third fin portion 18 arranged in sequence along the thickness direction of the semiconductor substrate 11. There is a recess structure 14 inwardly recessed along the width direction of the fin structure 15 at least between the first fin portion 16 and the second fin portion 17, and between the second fin portion 17 and the third fin portion 18.

[0054] Specifically, the above-mentioned semiconductor substrate can be a semiconductor substrate such as a silicon substrate, a germanium-silicon substrate or a germanium substrate. The thickness of the semiconductor substrate can be determined according to the aspect ratio of the structure of the first ring gate transistor and the second ring gate transistor.

[0055] Furthermore, the second fin of the aforementioned fin structure is used to fabricate the first ring-gate transistor, and the third fin is used to fabricate the second ring-gate transistor. Additionally, the aforementioned notch structure is used to form gaps between adjacent nanostructures and gaps between the underlying nanostructure and the semiconductor substrate. Therefore, the specific structures of the second and third fins can be determined based on the channel regions included in the first and second ring-gate transistors, respectively.

[0056] Specifically, such as Figure 7 As shown, both the second fin 17 and the third fin 18 include at least one layer of first channel preformed structure 12. Each first channel preformed structure 12 is adjacent to at least one notch structure 14.

[0057] In this configuration, each layer of the first channel pre-formed structure included in the second fin is used to form at least one corresponding layer of nanostructure included in the first ring-gate transistor; therefore, the number of layers of the first channel pre-formed structure included in the second fin is equal to the number of layers of nanostructure included in the first ring-gate transistor. Similarly, each layer of the first channel pre-formed structure included in the third fin is used to form at least one corresponding layer of nanostructure included in the second ring-gate transistor; therefore, the number of layers of the second channel pre-formed structure included in the third fin is equal to the number of layers of nanostructure included in the second ring-gate transistor.

[0058] Secondly, such as Figure 7 As shown, among all the first channel preformed structures 12 included in the second fin portion 17 and the third fin portion 18, the bottom of the first channel preformed structure 12 located at the top layer contacts the corresponding notch structure 14, the top of the first channel preformed structure 12 located at the bottom layer contacts the corresponding notch structure 14, and the top and bottom of the remaining first channel preformed structures 12 respectively contact the corresponding two notches structure 14.

[0059] It is understandable that, such as Figure 7 As shown, when the channel region of the first gate-ring transistor includes at least two layers of nanostructures spaced apart along the thickness direction of the semiconductor substrate 11, the second fin 17 has at least one recessed structure 14 recessed inward along the width direction of the fin structure 15. The at least one recessed structure 14 of the second fin 17 divides the remaining portion of the second fin 17 into at least two layers of first channel preformed structures 12. The number of layers of first channel preformed structures 12 included in the second fin 17 is equal to the number of layers of nanostructures included in the channel region of the first gate-ring transistor.

[0060] like Figure 7As shown, in the case that the channel region included in the second ring-gate transistor has at least two layers of nanostructures distributed along the thickness direction of the semiconductor substrate 11, the third fin portion 18 has at least one notch structure 14 recessed inwardly along the width direction of the fin structure 15. The at least one notch structure 14 of the third fin portion 18 divides the remaining part of the third fin portion 18 into at least two layers of first channel pre-formed structures 12. The number of layers of the first channel pre-formed structures 12 included in the third fin portion 18 is equal to the number of layers of nanostructures of the channel region included in the second ring-gate transistor.

[0061] Furthermore, the embodiments of the present application do not make specific limitation on the topography of each notch structure. Exemplarily, as shown in Figure 7 As shown, the notch structure 14 can be an arc-shaped notch structure.

[0062] In an example, as shown in Figure 7 As shown, in the case that both the second fin portion 17 and the third fin portion 18 include the at least one layer of first channel pre-formed structures 12, the above-mentioned patterning process of the semiconductor substrate 11 can include the steps of: as shown in Figure 7 As shown, performing first anisotropic etching on the semiconductor substrate 11 to form corresponding first channel pre-formed structures 12 on the semiconductor substrate 11. Next, as shown in Figure 2 As shown, forming a passivation layer 13 on the outer periphery of the formed structure on the semiconductor substrate 11. The formed structure includes the first channel pre-formed structures 12. Next, as shown in Figure 3 As shown, performing isotropic etching on the semiconductor substrate 11 under the protection of the passivation layer 13 to form notch structures 14 under the corresponding first channel pre-formed structures 12. As shown in Figure 4 and Figure 5 As shown, repeating the above-mentioned operations until the second fin portion and the third fin portion are formed on the semiconductor substrate 11. Finally, as shown in Figure 6 As shown, performing second anisotropic etching on the semiconductor substrate 11 to form a first fin portion 16 under the notch structure 14 of the bottom layer, thereby obtaining a fin structure 15.

[0063] In actual application, as shown in Figure 7 As shown, a mask layer can be formed on the semiconductor substrate 11 by using photolithography and etching processes; and under the masking effect of the mask layer, first anisotropic etching is performed on the semiconductor substrate 11 by using dry etching processes. Since anisotropic etching presents different etching rates for different crystallographic planes, it is beneficial to form first channel pre-formed structures 12 with vertical profiles. Next, oxidation treatment is performed on the formed structure to form an oxidation layer covering the surface of the semiconductor substrate and the outer periphery of the formed structure on the semiconductor substrate; as shown in Figure 2As shown, a portion of the oxide layer covering the surface of the semiconductor substrate 11 is removed using processes such as dry etching, leaving the remaining portion of the oxide layer to form a passivation layer 13. Specifically, the passivation layer 13 can be formed on both sides of the existing structure on the semiconductor substrate 11 along its width direction. Next, as... Figure 3 As shown, under the protection of the passivation layer 13, isotropic etching continues downwards on the semiconductor substrate 11 to form a notch structure 14 below the corresponding first channel pre-formed structure 12. The isotropic etching process can be determined based on the morphology of the notch structure 14 and the actual application scenario. For example, a dry etching process can be used to isotropically etch the semiconductor substrate 11. Then, the number of repetitions of the above operation is determined based on the number of notch structures 14 layers included in the fin structure 15. For example, as... Figure 4 As shown, when the fin structure 15 includes four layers of notch structures 14, the above operation needs to be performed four times. Finally, as Figures 2 to 7 As shown, under the action of the mask layer and passivation layer 13, the semiconductor substrate 11 continues to be etched downwards in a second anisotropic etching process to form a first fin 16 below the notch structure 14 located at the bottom layer, thereby obtaining a fin-shaped structure 15. The height of the first fin 16 can be determined according to the thickness of the shallow trench isolation structure subsequently formed, and is not specifically limited here.

[0064] It is worth noting that, such as Figure 7 As shown, the second fin 17 for manufacturing the first gate ring transistor and the third fin 18 for manufacturing the second gate ring transistor are both obtained by patterning the semiconductor substrate 11, and both are part of the semiconductor substrate 11. In other words, in the actual manufacturing process, the manufacturing method provided by the embodiments of the present invention can form the above-mentioned second fin 17 and third fin 18 without using epitaxial and bonding processes. This solves the problem in the existing monolithic method of manufacturing three-dimensional stacked complementary transistors that it is difficult to obtain a three-dimensional stacked complementary transistor that meets the requirements in order to achieve stress distribution and stress matching between thin films. At the same time, it also solves the problem in the existing sequential method of manufacturing three-dimensional stacked complementary transistors that it is difficult to achieve alignment in the bonding scheme, reducing the manufacturing difficulty of three-dimensional stacked complementary transistors and thus improving the working performance of three-dimensional stacked complementary transistors.

[0065] In the actual manufacturing process, after the above-mentioned fin-like structure is formed, such as Figures 2 to 7 As shown, a shallow trench isolation layer 19 is formed on the semiconductor substrate 11. The top height of the shallow trench isolation layer 19 is greater than or equal to the top height of the second fin 17 and less than or equal to the top height of the third fin 18.

[0066] Specifically, the material of the shallow trench isolation layer can be insulating materials such as silicon oxide or silicon nitride. The specific thickness of the shallow trench isolation layer can be determined according to the height of the first fin and the second fin, as well as the actual application scenario, as long as it can be applied to the manufacturing method of the semiconductor device provided in the embodiments of the present invention.

[0067] Next, the second fin is doped using an ion implantation process at a first implantation angle. Then, the third fin is doped using an ion implantation process at a second implantation angle. The second implantation angle differs from the first implantation angle.

[0068] In the actual manufacturing process, the order in which the second and third fins are doped in the manufacturing method provided in this embodiment of the invention is not specifically limited. The second fin may be doped first, followed by the third fin. Alternatively, the third fin may be doped first, followed by the second fin.

[0069] In addition, the size of the first injection angle and the second injection angle can be set according to the size of each part of the fin structure and the actual application scenario, and no specific limitation is made here.

[0070] For example, the first injection angle can be greater than 10° and less than or equal to 45°. For instance, the first injection angle can be 11°, 20°, 30°, 40°, or 45°, etc. In this case, such as... Figure 8 As shown, the second fin 17 is located below the third fin 18. Therefore, when the first injection angle is within the aforementioned range, it can prevent the third fin 18 from being doped with a high concentration of impurities of the opposite conductivity type due to a small first injection angle, thus preventing the difficulty of doping the third fin 18 and further reducing the manufacturing difficulty of the semiconductor device. At the same time, it can also prevent the corresponding impurities from being difficult to dope into the second fin 17 due to a large first injection angle, thereby reducing the manufacturing difficulty of the semiconductor device.

[0071] For example, the second injection angle is greater than or equal to 0° and less than or equal to 10°. For instance, the second injection angle can be 0°, 2°, 4°, 6°, 8°, or 10°, etc. The beneficial effects in this case are similar to those of the first injection angle being greater than 10° and less than or equal to 45°, and will not be elaborated further here.

[0072] It should be noted that when the first gate ring transistor is a junctionless gate ring transistor, and the source, drain, and channel regions of the first gate ring transistor are integrally formed, after doping the second fin, the corresponding portion of the second fin can correspondingly form the source, drain, and channel regions of the first gate ring transistor. In other cases, the above doping process only completes the doping of the channel region of the first gate ring transistor.

[0073] Furthermore, when the second gate ring transistor is a junctionless gate ring transistor, and the source, drain, and channel regions of the second gate ring transistor are integrally formed, after doping the third fin, the corresponding portion of the third fin can correspondingly form the source, drain, and channel regions of the second gate ring transistor. In other cases, the above doping process only completes the doping of the channel region of the second gate ring transistor.

[0074] Next, as Figure 7 As shown, dry etching or wet etching processes can be used to etch back the shallow trench isolation layer to expose the second fin 17. The remaining portion of the shallow trench isolation layer forms the shallow trench isolation structure 20.

[0075] It is worth noting that, as can be seen from the above manufacturing process, after forming the shallow trench isolation layer, the second fin is doped by ion implantation at a first implantation angle through the scattering of impurities in the shallow trench isolation layer. Furthermore, by simply changing the implantation angle of the ion implantation process and using different second implantation angles to dope the third fin, it is possible to dope the second and third fins with impurities of opposite conductivity types, further reducing the manufacturing difficulty of the three-dimensional stacked complementary transistor. Simultaneously, after etching back the shallow trench isolation layer, a shallow trench isolation structure can be formed to isolate different active regions of the semiconductor substrate, eliminating the need to form additional mask layers for doping the second and third fins with impurities of different conductivity types, thus simplifying the manufacturing process of the three-dimensional stacked complementary transistor.

[0076] like Figure 9 As shown, a first ring-gate transistor is formed based on a second fin, and a second ring-gate transistor is formed based on a third fin. The first ring-gate transistor and the second ring-gate transistor constitute a three-dimensional stacked complementary transistor.

[0077] In practical applications, such as Figure 19 As shown, when both the second fin 17 and the third fin 18 include the aforementioned first channel preformed structure 12, each first channel preformed structure 12 is adjacent to at least one notch structure 14. Furthermore, as... Figure 9As shown, along the length direction of the fin structure, each layer of the first channel pre-formed structure 12 has a first semiconductor region 21, a second semiconductor region 22, and a third semiconductor region 23 between the first semiconductor region 21 and the second semiconductor region 22. Based on this, the above-mentioned forming the first ring gate transistor based on the second fin portion 17 and forming the second ring gate transistor based on the third fin portion 18 can include the steps of: as shown, Figure 10 As shown, the second fin portion and the third fin portion are subjected to an oxidation treatment so that the part of the fin structure corresponding to the notched structure 14 forms a sacrificial oxide layer 24. And each layer of the first channel pre-formed structure forms a corresponding layer of the second channel pre-formed structure 25, and an oxide covering layer 26 is formed on the surface of the second channel pre-formed structure 25. Among them, the part of each layer of the second channel pre-formed structure 25 located in the third semiconductor region is the corresponding layer of nanostructure possessed by the channel region included in the first ring gate transistor or the second ring gate transistor.

[0078] Specifically, the specific conditions of the oxidation treatment can be determined according to actual needs, as long as the part of the fin structure corresponding to the notched structure can form a sacrificial oxide layer. In addition, as shown, Figure 11 As shown, each sacrificial oxide layer 24 is used to support at least one layer of the second channel pre-formed structure 25 located above itself. Based on this, the specifications of the corresponding sacrificial oxide layer 24 can be determined according to the specifications of the second channel pre-formed structure 25 to ensure that the structure formed after the oxidation treatment has good structural stability, thereby improving the yield of the three-dimensional stacked complementary transistor.

[0079] For example, along the thickness direction of the semiconductor substrate, the height of the above-mentioned sacrificial oxide layer can be greater than or equal to 10 nm and less than or equal to 30 nm. For example: along the thickness direction of the semiconductor substrate, the height of the above-mentioned sacrificial oxide layer can be 10 nm, 15 nm, 20 nm, 25 nm or 30 nm, etc.

[0080] In addition, if the source region and the drain region included in the first ring gate transistor and the second ring gate transistor are formed separately from the channel region included in itself, after the oxidation treatment of the second fin portion and the third fin portion, the above-mentioned semiconductor device manufacturing method includes the steps of: as shown, Figure 11 As shown, deposition and etching processes can be used to form a sacrificial gate 27 and a sidewall 28 across the second fin portion and the third fin portion respectively corresponding to the third semiconductor region. The sidewall 28 is formed at least on both sides of the sacrificial gate 27 along the length direction of itself. Next, as shown, Figure 12 As shown, dry etching or wet etching processes can be used to remove the part of each layer of the second channel pre-formed structure, each layer of the sacrificial oxide layer, and the oxide covering layer respectively corresponding to the first semiconductor region and the second semiconductor region. Then, as shown, Figure 13As shown, deposition or epitaxy can be used to form the source region 29 and the drain region 30 on both sides of the channel region included in the first ring gate transistor. Next, as shown, Figure 14 As shown, deposition and etching can be used to form the isolation layer 31 covering the source region 29 and the drain region 30 included in the first ring gate transistor. Then, as shown, Figure 15 As shown, deposition or epitaxy can be used to form the source region 29 and the drain region 30 on both sides of the channel region included in the second ring gate transistor on the isolation layer 31. Next, as shown, Figure 16 As shown, dry etching or wet etching can be used to remove the sacrificial gate, and remove the portion of each layer of the sacrificial oxide layer and the oxide covering layer corresponding to the third semiconductor region, to expose the channel region 33 included in the first ring gate transistor and the second ring gate transistor, respectively.

[0081] It should be noted that, as shown, Figure 18 After the channel region 33 included in the first ring gate transistor and the second ring gate transistor is exposed, the portion of each layer of the sacrificial oxide layer and the oxide covering layer located below the sidewall 28 can be retained. At this time, the portion of each layer of the sacrificial oxide layer and the oxide covering layer remaining below the sidewall 28 can serve as an inner sidewall, which can be formed without additional operations while limiting the length of the gate stack structure, further simplifying the manufacturing process of the three-dimensional stacked complementary transistor. Specifically, the width of the portion of each layer of the sacrificial oxide layer and the oxide covering layer located below the sidewall 28 can be less than or equal to the width of the sidewall 28.

[0082] In some cases, as shown, Figure 18 After the source region 29 and the drain region 30 included in the second ring gate transistor are formed, and before the sacrificial gate 27 is removed, deposition and planarization can be used to form a dielectric layer 32 covering the semiconductor substrate 11, to protect the source region 29 and the drain region 30 included in the second ring gate transistor from being affected in subsequent operations, improving the formation quality of the second ring gate transistor. Specifically, the top of the dielectric layer 32 is flush with the top of the sacrificial gate 27. The material of the dielectric layer 32 can be silicon oxide or silicon nitride, or other insulating materials.

[0083] Finally, as shown, Figure 17 Figure 19 Atomic layer deposition can be used to form the gate stack structure 35 included in the first ring gate transistor and the second ring gate transistor, respectively.

[0084] Specifically, the gate stack structure included in the first and second ring gate transistors can each include a gate dielectric layer formed on the outer periphery of the corresponding nanostructure, and a gate electrode formed on the corresponding gate dielectric layer. The material of the gate dielectric layer can be an insulating material such as HfO2, ZrO2, TiO2, or Al2O3. The material of the gate electrode can be a conductive material such as TiN, TaN, or TiSiN.

[0085] In addition, the materials of the gate stack structures included in the first and second ring gate transistors can be the same or different.

[0086] In the case where the materials of the gate dielectric layers included in the first and second ring gate transistors are the same, and the materials and / or thicknesses of the gate electrodes included in the first and second ring gate transistors are different, the formation of the gate stack structures included in the first and second ring gate transistors can include the steps of: first, forming a gate dielectric layer that surrounds the outer periphery of the channel region included in the first and second ring gate transistors. Next, forming the gate electrode included in the first ring gate transistor only on the gate dielectric layer located on the outer periphery of the channel region included in the first ring gate transistor. Next, forming the gate electrode included in the second ring gate transistor on the gate dielectric layer located on the outer periphery of the channel region included in the second ring gate transistor. The material of the gate electrode included in the second ring gate transistor is different from the material of the gate electrode included in the first ring gate transistor.

[0087] In actual manufacturing processes, the gate dielectric layer can be formed using atomic layer deposition or other processes. Then, a gate electrode material that is the same as the material of the gate electrode included in the first ring gate transistor is formed on all of the gate dielectric layers. An etching process is used to etch back the gate electrode material, leaving only the portion of the gate electrode material located on the outer periphery of the channel region included in the first ring gate transistor, thereby obtaining the gate electrode included in the first ring gate transistor. Finally, a deposition process can be used to form the gate electrode included in the second ring gate transistor, thereby obtaining the second ring gate transistor.

[0088] In the above description, the patterning, etching, and other technical details of each layer are not described in detail. However, those skilled in the art will understand that various technical means can be used to form layers, regions, and the like with the desired shape. In addition, those skilled in the art can design methods that are not exactly the same as the methods described above in order to form the same structure. In addition, although each embodiment is described above, this does not mean that the measures in each embodiment cannot be used advantageously in combination.

[0089] The above describes embodiments of the present disclosure. However, these embodiments are merely for illustrative purposes, and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Those skilled in the art can make various substitutions and modifications without departing from the scope of the present disclosure, and all such substitutions and modifications shall fall within the scope of the present disclosure.

Claims

1. A method of manufacturing a semiconductor device, characterized by, The method comprises: patterning a semiconductor substrate to form a fin structure on the semiconductor substrate; the fin structure comprises a first fin portion, a second fin portion and a third fin portion arranged in sequence along the thickness direction of the semiconductor substrate; at least between the first fin portion and the second fin portion and between the second fin portion and the third fin portion, there is a notch structure recessed inward along the width direction of the fin structure; forming a shallow trench isolation layer on the semiconductor substrate; the top height of the shallow trench isolation layer is greater than or equal to the top height of the second fin portion and less than or equal to the top height of the third fin portion; using an ion implantation process and a first implantation angle to dope the second fin portion; using an ion implantation process and a second implantation angle to dope the third fin portion; the second implantation angle is different from the first implantation angle; the second fin portion and the third fin portion are respectively doped with impurities of opposite conductivity types; etching back the shallow trench isolation layer to expose the second fin portion; the remaining part of the shallow trench isolation layer forms a shallow trench isolation structure; forming a first ring gate transistor based on the second fin portion and a second ring gate transistor based on the third fin portion; the first ring gate transistor and the second ring gate transistor constitute a three-dimensional stacked complementary transistor.

2. The method of manufacturing a semiconductor device according to claim 1, wherein The second fin portion and the third fin portion each comprise at least one first channel pre-formation structure; each first channel pre-formation structure is adjacent to at least one notch structure; The method of patterning a semiconductor substrate comprises: performing first anisotropic etching on the semiconductor substrate to form corresponding first channel pre-formation structures on the semiconductor substrate; forming a passivation layer on the periphery of the formed structures on the semiconductor substrate; the formed structures include the first channel pre-formation structures; under the protection of the passivation layer, performing isotropic etching on the semiconductor substrate to form the notch structures below the corresponding first channel pre-formation structures; repeating the above-mentioned first anisotropic etching, forming the passivation layer and the isotropic etching until the second fin portion and the third fin portion are formed on the semiconductor substrate; performing second anisotropic etching on the semiconductor substrate to form the first fin portion below the notch structures in the bottom layer, thereby obtaining the fin structure.

3. The method of manufacturing a semiconductor device according to Claim 1 or 2, wherein In the case where the channel region included in the first ring gate transistor has at least two layers of nanostructures spaced apart along the thickness direction of the semiconductor substrate, the second fin portion has at least one notch structure recessed inward along the width direction of the fin structure; the at least one notch structure of the second fin portion divides the remaining part of the second fin portion into at least two first channel pre-formation structures; the number of first channel pre-formation structures included in the second fin portion is equal to the number of nanostructures included in the channel region of the first ring gate transistor; and / or, In a case where the channel region included in the second ring gate transistor has at least two layers of nanostructures distributed at intervals along the thickness direction of the semiconductor substrate, the third fin portion has at least one of the notch structures recessed inward along the width direction of the fin structure; the at least one of the notch structures of the third fin portion divides the remaining part of the third fin portion into at least two layers of first channel pre-formed structures; the number of layers of the first channel pre-formed structures included in the third fin portion is equal to the number of layers of nanostructures of the channel region included in the second ring gate transistor.

4. The method of manufacturing a semiconductor device according to Claim 1 or 2, wherein The notch structure is an arc-shaped notch structure.

5. The method of manufacturing a semiconductor device according to claim 2, wherein The isotropic etching of the semiconductor substrate is performed by using a dry etching process.

6. The method of manufacturing a semiconductor device according to claim 1 or 2, wherein The first implantation angle is greater than 10° and less than or equal to 45°; and / or, The second implantation angle is greater than or equal to 0° and less than or equal to 10°.

7. The method of manufacturing a semiconductor device according to Claim 1, wherein The second fin portion and the third fin portion each include at least one layer of first channel pre-formed structures; each of the first channel pre-formed structures is adjacent to at least one of the notch structures; along the length direction of the fin structure, each layer of the first channel pre-formed structures has a first semiconductor region, a second semiconductor region, and a third semiconductor region between the first semiconductor region and the second semiconductor region; The forming of the first ring gate transistor based on the second fin portion and the forming of the second ring gate transistor based on the third fin portion include: Performing an oxidation treatment on the second fin portion and the third fin portion, so that the part of the fin structure corresponding to the notch structure forms a sacrificial oxide layer; and so that each layer of the first channel pre-formed structures forms a corresponding layer of second channel pre-formed structures and an oxide covering layer on the surface of the second channel pre-formed structures; wherein The part of each layer of the second channel pre-formed structures located in the third semiconductor region is a corresponding layer of nanostructures of the channel region included in the first ring gate transistor or the second ring gate transistor.

8. The method of manufacturing a semiconductor device according to claim 7, wherein The height of the sacrificial oxide layer along the thickness direction of the semiconductor substrate is greater than or equal to 10 nm and less than or equal to 30 nm.

9. The method of manufacturing a semiconductor device according to Claim 7, wherein After the oxidation treatment on the second fin portion and the third fin portion, the semiconductor device manufacturing method includes: forming a sacrificial gate and a side wall across the third semiconductor region corresponding to the second fin portion and the third fin portion respectively; the side wall is formed at least on both sides of the sacrificial gate along the length direction of the sacrificial gate; removing the part of each layer of the second channel pre-formed structures, each layer of the sacrificial oxide layer, and the oxide covering layer corresponding to the first semiconductor region and the second semiconductor region respectively; forming source regions and drain regions located on both sides of the channel region included in the first ring gate transistor; forming an isolation layer covering the source regions and the drain regions included in the first ring gate transistor; forming source regions and drain regions located on both sides of the channel region included in the second ring gate transistor on the isolation layer; removing the sacrificial gate, and removing the part of each layer of the sacrificial oxide layer and the oxide covering layer corresponding to the third semiconductor region, to expose the channel region included in the first ring gate transistor and the second ring gate transistor respectively; forming the gate stack structure included in the first and second ring gate transistors, respectively.

10. The method of manufacturing a semiconductor device according to Claim 9, wherein forming the gate stack structure included in the first and second ring gate transistors, respectively. forming a gate dielectric layer surrounding the channel region included in the first and second ring gate transistors, respectively; forming the gate included in the first ring gate transistor only on the gate dielectric layer surrounding the channel region included in the first ring gate transistor; forming the gate included in the second ring gate transistor on the gate dielectric layer surrounding the channel region included in the second ring gate transistor, wherein the material of the gate included in the second ring gate transistor is different from the material of the gate included in the first ring gate transistor.

11. The method of manufacturing a semiconductor device according to Claim 1, wherein the first and second ring gate transistors are both junctionless ring gate transistors.

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