Semiconductor element and method for manufacturing the same

Abstract

The present disclosure provides a semiconductor element and a method for manufacturing the semiconductor element. The semiconductor element includes a first wafer, the first wafer including a first substrate and a plurality of first alignment marks disposed on the first substrate and parallel to each other; and a second wafer disposed on the first wafer and including a plurality of second alignment marks disposed above the plurality of first alignment marks. The plurality of second alignment marks are arranged parallel to the plurality of first alignment marks and are adjacent to the plurality of first alignment marks when viewed from above. The plurality of first alignment marks and the plurality of second alignment marks include a fluorescent material.

Description

Technical Field

[0001] This application claims priority to and the benefits of U.S. patent application Ser. No. 17 / 541,754, filed December 3, 2021, the contents of which are incorporated herein by reference in their entirety.

[0002] The present disclosure provides a semiconductor element and a manufacturing method thereof, and more particularly relates to a semiconductor element with an alignment mark and a manufacturing method thereof. Background Art

[0003] Semiconductor components are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor component size continues to shrink to meet the growing demand for computing power. However, various challenges have emerged and are increasing during this scaling process. Consequently, achieving improvements in quality, yield, performance, and reliability, while reducing complexity, remains a challenge.

[0004] The above description of “prior art” merely provides background technology, does not acknowledge that the above description of “prior art” reveals the subject matter of the present disclosure, does not set the prior art of the present disclosure, and any description of the above “prior art” should not be regarded as any part of this case. Summary of the Invention

[0005] One embodiment of the present disclosure provides a semiconductor device, comprising a first wafer, the first wafer comprising a first substrate and a plurality of first alignment marks disposed on the first substrate and parallel to each other; and a second wafer, the second wafer disposed on the first wafer and comprising a plurality of second alignment marks disposed above the plurality of first alignment marks. The plurality of second alignment marks are arranged parallel to the plurality of first alignment marks and are adjacent to the plurality of first alignment marks when viewed from above. The plurality of first alignment marks and the plurality of second alignment marks comprise a fluorescent material. The plurality of first alignment marks and the plurality of second alignment marks are collectively configured to form a first group of alignment marks.

[0006] Another embodiment of the present disclosure provides a semiconductor device comprising a substrate; a dielectric stack disposed on the substrate; two conductive features disposed in the dielectric stack; a decoupling unit disposed in the dielectric stack between the two second conductive features and having a bottle-shaped cross-sectional profile; and an alignment mark disposed on the decoupling unit. The alignment mark comprises a fluorescent material.

[0007] Another embodiment of the present disclosure provides a method for fabricating a semiconductor device, comprising: providing a first substrate; forming a plurality of mutually parallel first alignment marks on the first substrate, wherein the first substrate and the plurality of first alignment marks are collectively configured into a first wafer; providing a second chip including a plurality of mutually parallel second alignment marks; and bonding the second wafer to the first wafer. The plurality of second alignment marks are arranged parallel to the plurality of first alignment marks and are adjacent to the plurality of first alignment marks when viewed from above. The plurality of first alignment marks and the plurality of second alignment marks include a fluorescent material.

[0008] Another embodiment of the present disclosure provides a method for fabricating a semiconductor device, comprising: providing a substrate; forming a first dielectric layer on the substrate; forming a second dielectric layer on the first dielectric layer; forming two second conductive features on the second dielectric layer; forming an intermediate dielectric layer on the second dielectric layer and surrounding the two second conductive features; performing an expansion etching process to form an expanded opening in the intermediate dielectric layer; forming a decoupling unit in the expanded opening; and forming an alignment mark on the decoupling unit. The alignment mark comprises a fluorescent material.

[0009] Due to the disclosed semiconductor device design, multiple alignment marks comprising fluorescent materials can improve optical identification during the wafer bonding process. Furthermore, the complementary design allows the multiple first alignment marks and the multiple second alignment marks to serve as a reference for each other during the bonding process. Consequently, the yield and reliability of semiconductor devices can be improved.

[0010] The above has provided a fairly broad overview of the technical features and advantages of the present disclosure, allowing for a better understanding of the detailed description of the present disclosure below. Other technical features and advantages that are the subject of the claims of the present disclosure will be described below. It should be understood by those skilled in the art that the concepts and specific embodiments disclosed below can be readily utilized to modify or design other structures or processes to achieve the same purposes as those of the present disclosure. It should also be understood by those skilled in the art that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined by the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] A more complete understanding of the disclosure of the present invention may be obtained by referring to the detailed description and the claims in conjunction with the drawings, in which like reference numerals refer to like elements.

[0012] Figure 1 is a flow chart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0013] Figures 2 to 5is a cross-sectional view illustrating a partial manufacturing process of a semiconductor device according to an embodiment of the present disclosure.

[0014] Figure 6 FIG. 1 is a top view illustrating a middle semiconductor element according to an embodiment of the present disclosure.

[0015] Figure 7 and Figure 8 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present disclosure along Figure 6 Part of the preparation process is captured along line A-A'.

[0016] Figure 9 FIG. 1 is a top view illustrating a middle semiconductor element according to an embodiment of the present disclosure.

[0017] Figure 10 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present disclosure along Figure 9 Part of the preparation process is captured along line A-A'.

[0018] Figure 11 FIG. 1 is a top view illustrating a middle semiconductor element according to an embodiment of the present disclosure.

[0019] Figure 12 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present disclosure along Figure 11 Part of the preparation process is captured along line A-A'.

[0020] Figure 13 FIG. 1 is a top view illustrating a semiconductor device according to another embodiment of the present disclosure.

[0021] Figure 14 is a flow chart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0022] Figures 15 to 25 is a cross-sectional view illustrating a partial manufacturing process of a semiconductor device according to another embodiment of the present disclosure.

[0023] Figure 26 is a cross-sectional view illustrating a semiconductor device according to another embodiment of the present disclosure.

[0024] The description of the accompanying drawings is as follows:

[0025] 1A: Semiconductor components

[0026] 1B: Semiconductor components

[0027] 1C: Semiconductor components

[0028] 1D: Semiconductor components

[0029] 1S: First set of alignment marks

[0030] 2S: Second set of alignment marks

[0031] 3S: The third set of alignment marks

[0032] 4S: The fourth set of alignment marks

[0033] 5S: The fifth set of alignment marks

[0034] 10: Preparation method

[0035] 20: Preparation method

[0036] 100: First Wafer

[0037] 101: First Base

[0038] 103: First conductive feature

[0039] 105: First alignment mark

[0040] 107: First bottom lining

[0041] 109: First top lining

[0042] 200: Second wafer

[0043] 201: Second base

[0044] 203: Second conductive feature

[0045] 205: Second alignment mark

[0046] 207: Second bottom lining

[0047] 209: Second top lining

[0048] 301: Third base

[0049] 303: First dielectric layer

[0050] 305: Second dielectric layer

[0051] 307: Intermediate dielectric layer

[0052] 307E: Enlarged opening

[0053] 307O: Opening

[0054] 309: Three dielectric layers

[0055] 311: Fourth dielectric layer

[0056] 311O: Marking opening

[0057] 313: Second conductive feature

[0058] 315: Bottom barrier layer

[0059] 315SW: Sidewall

[0060] 317: Middle conductive layer

[0061] 317SW: Sidewall

[0062] 319: Top barrier layer

[0063] 319SW: Sidewall

[0064] 321: Spacer barrier

[0065] 323: Decoupling unit

[0066] 323BS: bottom surface

[0067] 323SW: Sidewall

[0068] 323V: Valley bottom

[0069] 325: Third alignment mark

[0070] 325BS: bottom surface

[0071] 325SW: Sidewall

[0072] 325TS: Top surface

[0073] 501: First Material

[0074] 503: Second Material

[0075] 505: Third Material

[0076] 507: Fourth Material

[0077] 509: Fifth Material

[0078] 511: Insulation layer

[0079] 601: First mask layer

[0080] 603: Second mask layer

[0081] 605: The third mask layer

[0082] 607: Fourth mask layer

[0083] DS: Dielectric Stack

[0084] S: Direction

[0085] S11: Steps

[0086] S13: Steps

[0087] S15: Steps

[0088] S17: Steps

[0089] S19: Steps

[0090] S21: Steps

[0091] S23: Steps

[0092] S25: Steps

[0093] T1: thickness

[0094] T2: Thickness

[0095] T3: Thickness

[0096] T4: Thickness

[0097] T5: Thickness

[0098] T6: Thickness

[0099] T7: Thickness

[0100] W1: width

[0101] W2: width

[0102] W3: Width

[0103] W4: Width

[0104] W5: width

[0105] X: Direction

[0106] Y: direction

[0107] Z: Direction DETAILED DESCRIPTION

[0108] The following disclosure provides many different embodiments or examples for implementing different features of the present disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the size of an element is not limited to the disclosed ranges or values, but may depend on process conditions and / or the desired properties of the element. In addition, the following description of forming a first feature "above" or "on" a second feature may include embodiments in which the first and second features are formed to be in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, thereby making it possible for the first and second features not to be in direct contact. For the sake of brevity and clarity, some features may be arbitrarily drawn at different scales. In the accompanying drawings, some layers / features may be omitted for simplicity.

[0109] Furthermore, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures. These spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. The elements may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0110] It will be understood that when an element or layer is referred to as being “connected to” or “coupled to” another element or layer, it can be directly connected or coupled to the other element or layer or intervening elements or layers may be present.

[0111] It should be understood that although the terms first, second, etc. can be used to describe various elements, these elements should not be limited by the terms. Unless otherwise specified, the terms are used only to distinguish one element from another. Thus, for example, the first element, first component, or first part discussed below can be referred to as the second element, second component, or second part without departing from the teachings of the present disclosure.

[0112] Unless the context indicates otherwise, terms such as "same," "equal," "planar," or "coplanar" used herein when referring to an orientation, layout, position, shape, size, quantity, or other measure do not necessarily mean exactly the same orientation, layout, position, shape, size, quantity, or other measure, but rather mean nearly the same orientation, layout, position, shape, size, quantity, or other measure, within an acceptable range of variation that may occur, such as due to manufacturing processes. The term "substantially" may be used to reflect this meaning. For example, items described as "substantially the same," "substantially equal," or "substantially coplanar" may be exactly the same, equal, or planar, or they may be the same, equal, or planar within an acceptable range of variation that may occur, such as due to manufacturing processes.

[0113] In the present disclosure, a semiconductor element generally refers to an element that can function by utilizing semiconductor characteristics, and electro-optical elements, light-emitting display elements, semiconductor circuits, and electronic elements are all included in the category of semiconductor elements.

[0114] It should be understood that in the description of the present disclosure, up (or above) corresponds to the direction of the arrow of direction Z, and down (or below) corresponds to the opposite direction of the arrow of direction Z.

[0115] It should be understood that, in the description of the present disclosure, the terms "forming," "formed," and "form" may refer to and include any method of establishing, structuring, patterning, implanting, or depositing an element, dopant, or material. Examples of formation methods may include, but are not limited to, atomic layer deposition, chemical vapor deposition, physical vapor deposition, sputtering, co-sputtering, spin coating, diffusion, deposition, growth, implantation, lithography, dry etching, and wet etching.

[0116] It should be understood that in the description of the present disclosure, the functions or steps indicated may occur in a different order than that indicated in the figures. For example, two figures shown in succession may in fact be performed simultaneously, or may sometimes be performed in an opposite order, depending on the functions or steps involved.

[0117] Figure 1 1 is a flow chart illustrating a method 10 for manufacturing a semiconductor device according to an embodiment of the present disclosure. Figures 2 to 5 1 is a cross-sectional view illustrating a partial manufacturing process of a semiconductor device 1A according to an embodiment of the present disclosure. Figure 6 FIG. 1 is a top view illustrating a middle semiconductor element according to an embodiment of the present disclosure. Figure 7 and Figure 8 is a cross-sectional view illustrating a semiconductor device 1A according to an embodiment of the present disclosure along Figure 6 It should be understood that for the sake of clarity, some elements of the semiconductor device 1A are omitted in the top view.

[0118] Reference Figures 1 to 3 In step S11 , a first substrate 101 may be provided, and a plurality of first conductive features 103 may be formed on the first substrate 101 .

[0119] Reference Figure 2 The first substrate 101 may include a bulk semiconductor substrate entirely composed of at least one semiconductor material, a plurality of device elements (not shown for clarity), a plurality of dielectric layers (not shown for clarity), and a plurality of conductive features (not shown for clarity). The bulk semiconductor substrate may be fabricated using, for example, an elementary semiconductor such as silicon or germanium; a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or other III-V compound semiconductors or II-VI compound semiconductors; or a combination thereof.

[0120] In some embodiments, the first substrate 101 may include a semiconductor-on-insulator (SOI) structure, including, from bottom to top, a processing substrate, an insulator layer, and an uppermost semiconductor material layer. The processing substrate and the uppermost semiconductor material layer may be made of the same material as the bulk semiconductor substrate described above. The insulator layer may be a crystalline or amorphous dielectric material, such as an oxide and / or a nitride. For example, the insulating layer may be a dielectric oxide, such as silicon oxide. For another example, the insulator layer may be a dielectric nitride, such as silicon nitride or boron nitride. For another example, the insulator layer may include a stack of dielectric oxide and dielectric nitride, such as a stack of silicon oxide and silicon nitride or boron nitride in any order. The thickness of the insulator layer may be in the range of 10 nanometers (nm) to 200 nanometers.

[0121] It should be understood that in the description of the present disclosure, the term "approximately" modifies the amount of an ingredient, composition, or reactant of the present disclosure to refer to variations in the numerical amount that may occur, for example, due to typical measurement and liquid handling procedures used to make concentrates or solutions. In addition, variations may occur due to inadvertent errors in measurement procedures, differences in the manufacture, source, or purity of the ingredients used to make the composition or perform the method, etc. In one embodiment, the term "approximately" means within 10% of the disclosed value. In another embodiment, the term "approximately" means within 5% of the disclosed value. In yet another embodiment, the term "approximately" means within 10, 9, 8, 7, 6, 5, 4, 3, 2, or 1% of the disclosed value.

[0122] Reference Figure 2 , multiple element units can be formed on a bulk semiconductor substrate or an uppermost semiconductor material layer. Some portions of the multiple element units can be formed in the bulk semiconductor substrate or an uppermost semiconductor material layer. The multiple element units can be transistors, such as complementary metal oxide semiconductor (CMOS) transistors, metal oxide semiconductor field effect transistors (MOSFETs), fin field effect transistors (FinFETs), etc., or a combination thereof.

[0123] Reference Figure 2, multiple dielectric layers can be formed on a bulk semiconductor substrate or the topmost semiconductor material layer and cover multiple device units. In some embodiments, the manufacturing technology of the multiple dielectric layers can be, for example, silicon oxide, borophosphosilicate glass, undoped silicate glass, fluorinated silicate glass, low dielectric constant (low-k) material, etc., or a combination thereof. The term "(low-k)" used in this disclosure refers to a dielectric material with a dielectric constant less than that of silicon dioxide. The dielectric constant of the low-k material can be less than 3.0 or even less than 2.5. In some embodiments, the dielectric constant of the low-k material can be less than 2.0. The manufacturing technology of the multiple dielectric layers can be by a deposition process, such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD) or a similar process. A planarization process can be performed after the deposition process to remove excess material and provide a substantially flat surface for subsequent process steps.

[0124] Reference Figure 2 , the multiple conductive features may include interconnect layers, conductive vias, and conductive pads. The interconnect layers may be separated from each other and may be arranged horizontally in the multiple dielectric layers along the Z direction. In this embodiment, the topmost interconnect layer may be designated as a conductive pad. The conductive vias may connect adjacent interconnect layers, adjacent component units and interconnect layers, and adjacent conductive pads and interconnect layers along the Z direction. In some embodiments, the conductive vias may improve heat dissipation and provide structural support. In some embodiments, the fabrication technology of the multiple conductive features may be, for example, tungsten (W), cobalt (Co), zirconium (Zr), tantalum (Ta), titanium (Ti), aluminum (Al), ruthenium (Ru), copper (Cu), metal carbides (such as tantalum carbide (TaC), titanium carbide (TiC), tantalum magnesium carbide (TaMgC)), metal nitrides (such as titanium nitride (TiN)), transition metal aluminides, or combinations thereof. The multiple conductive features may be formed in the process of forming the multiple dielectric layers.

[0125] In some embodiments, multiple component units and multiple conductive features can collectively configure a functional unit of the first substrate 101. In the present disclosure, a functional unit generally refers to a circuit associated with a function that has been divided into an independent unit. In some embodiments, a functional unit can be a typical highly complex circuit, such as a processor core, a memory controller, or an accelerator unit. In other embodiments, the complexity and functionality of a functional unit can be more or less complex.

[0126] Reference Figure 2 A first material layer 501 can be formed on the first substrate 101. In some embodiments, the first material 501 can be, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, a metal carbide (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), a metal nitride (e.g., titanium nitride), a transition metal aluminide, or a combination thereof. The first material layer 501 can be formed by, for example, physical vapor deposition, sputtering, chemical vapor deposition, or other suitable deposition processes.

[0127] Reference Figure 2 A first mask layer 601 may be formed on the first material layer 501. The first mask layer 601 may be a photoresist layer and may include a pattern of a plurality of first conductive features 103.

[0128] Reference Figure 3 , an etching process, such as an anisotropic dry etching process, may be performed to remove a portion of the first material 501 and simultaneously form a plurality of first conductive features 103 on the first substrate 101. In the etching process, an etching rate ratio of the first material 501 to the first substrate 101 may be in a range of about 100:1 to about 1.05:1, in a range of about 15:1 to about 2:1, or in a range of about 10:1 to about 2:1. After the etching process, the first mask layer 601 may be removed. In some embodiments, the plurality of first conductive features 103 may be electrically coupled to a plurality of element units, but the present disclosure is not limited thereto. In some embodiments, the plurality of first conductive features 103 may be configured as a test circuit.

[0129] Reference Figure 1 and Figure 4 In step S13 , a first bottom liner 107 may be formed to cover the first substrate 101 and the plurality of first conductive features 103 .

[0130] Reference Figure 4, the first bottom liner 107 can be conformally formed to cover the first substrate 101 and the plurality of first conductive features 103. In some embodiments, the manufacturing technology of the first bottom liner 107 can be by, for example, atomic layer deposition. Generally speaking, atomic layer deposition supplies two (or more) different source gases alternately to a process object (e.g., the first substrate 101 and the plurality of first conductive features 103) under predetermined process conditions, thereby causing chemical species to be adsorbed on the process object at the level of a single atomic layer and deposited on the process object through surface reaction. For example, the first and second source gases are alternately supplied to the process object so as to flow along the surface, thereby causing molecules contained in the first source gas to be adsorbed to the surface, and molecules contained in the second source gas react with the adsorbed molecules from the first source gas to form a thin film with a thickness of a monomolecular layer. The above process steps are repeatedly performed, so that a high-quality thin film can be formed on the process object.

[0131] In some embodiments, the first bottom liner 107 may be fabricated using a process such as silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or a combination thereof. It should be understood that, in the present disclosure, silicon oxynitride refers to a substance containing silicon, nitrogen, and oxygen, wherein the proportion of oxygen is greater than the proportion of nitrogen. Silicon nitride oxide refers to a substance containing silicon, oxygen, and nitrogen, wherein the proportion of nitrogen is greater than the proportion of oxygen.

[0132] It should be understood that Figure 4 The first substrate 107 completely covering the plurality of first conductive features 103 and the first base 101 is only for illustration purposes, and some portions of the plurality of first conductive features 103 may be exposed to facilitate electrical coupling with other elements.

[0133] Reference Figure 1 and Figures 5 to 7 In step S15 , a plurality of first alignment marks 105 may be formed on the first bottom liner 107 and between the plurality of first conductive features 103 .

[0134] Reference Figure 5 Insulating layer 511 may be formed on first bottom liner 107 and completely fill the spaces between adjacent first conductive features 103. Insulating layer 511 may include a fluorescent material. In some embodiments, the fluorescent material may be azobenzene. In some embodiments, insulating layer 511 may be formed using techniques such as chemical vapor deposition.

[0135] Reference Figure 6 and Figure 7, a planarization process, such as chemical mechanical polishing, can be performed until the first bottom liner 107 is exposed to remove excess material, provide a substantially flat surface for subsequent processing steps, and simultaneously convert the insulating layer 511 into a plurality of first alignment marks 105. From a cross-sectional perspective, the plurality of first conductive features 103 can horizontally surround the plurality of first alignment marks 105, and the plurality of first alignment marks 105 can be parallel to each other. In a top-down perspective, the plurality of first alignment marks 105 arranged in the upper left region can extend along the Y direction and be parallel to each other. The plurality of first alignment marks 105 arranged in the upper right region can extend along the X direction and be parallel to each other. The plurality of first alignment marks 105 arranged in the lower left region can extend along the X direction and be parallel to each other. The plurality of first alignment marks 105 arranged in the lower right region can extend along the Y direction and be parallel to each other.

[0136] The plurality of first alignment marks 105 comprising fluorescent material can improve optical recognition capability in a subsequent wafer bonding process.

[0137] Reference Figure 1 and Figure 8 In step S17 , a first top liner 109 may be formed on the first bottom liner 107 and the plurality of first alignment marks 105 .

[0138] Reference Figure 8 , the first top liner 109 can be conformally formed on the first bottom liner 107 and the plurality of first alignment marks 105. In some embodiments, the manufacturing technology of the first top liner 109 can be, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, etc., or a combination thereof. In some embodiments, the manufacturing technology of the first top liner 109 can be, for example, atomic layer deposition. The first top liner 109 can serve as a protective layer to prevent the fluorescent material in the plurality of first alignment marks 105 from being damaged in subsequent semiconductor processes. In addition, the first top liner 109 can also serve as a barrier layer to prevent the fluorescent material in the plurality of first alignment marks 105 from diffusing out and contaminating adjacent units.

[0139] The first substrate 101, the plurality of first conductive features 103, the plurality of first alignment marks 105, the first bottom liner 107, and the first top liner 109 are collectively configured as a first wafer 100. The first wafer 100 may be configured as a logic chip or a memory chip.

[0140] Figure 9 FIG. 1 is a top view illustrating a middle semiconductor element according to an embodiment of the present disclosure. Figure 10 is a cross-sectional view illustrating a semiconductor device 1A according to an embodiment of the present disclosure along Figure 9 Part of the preparation process is captured along line A-A'. Figure 11FIG. 1 is a top view illustrating a middle semiconductor element according to an embodiment of the present disclosure. Figure 12 is a cross-sectional view illustrating a semiconductor device 1A according to an embodiment of the present disclosure along Figure 11 Part of the preparation process is captured along line A-A'.

[0141] Reference Figure 1 and Figures 9 to 12 In step S19 , a second wafer 200 may be provided and bonded to the first top liner 109 to form the semiconductor device 1A.

[0142] Reference Figure 9 and Figure 10 The second wafer 200 may include a second substrate 201, a plurality of second conductive features 203, a plurality of second alignment marks 205, a second bottom liner 207, and a second top liner 209. The second substrate 201, the plurality of second conductive features 203, the plurality of second alignment marks 205, the second bottom liner 207, and the second top liner 209 may be formed by a process similar to Figures 2 to 8 The first substrate 101, the plurality of first conductive features 103, the plurality of first alignment marks 105, the first bottom liner 107 and the first top liner 109 are formed separately and correspondingly by the processes described in the foregoing, and are not repeated here.

[0143] In some embodiments, the plurality of second alignment marks 205 may include a fluorescent material. The fluorescent material may be, for example, azobenzene. The plurality of second alignment marks 205 including the fluorescent material may improve optical recognition capability in a subsequent wafer bonding process.

[0144] In some embodiments, from a cross-sectional perspective, the plurality of second conductive features 203 can horizontally surround the plurality of second alignment marks 205, and the plurality of second alignment marks 205 can be parallel to each other. From a top-down perspective, the plurality of second alignment marks 205 disposed in the upper left region can extend along the Y direction and be parallel to each other. The plurality of second alignment marks 205 disposed in the upper right region can extend along the X direction and be parallel to each other. The plurality of second alignment marks 205 disposed in the lower left region can extend along the X direction and be parallel to each other. The plurality of second alignment marks 205 disposed in the lower right region can extend along the Y direction and be parallel to each other.

[0145] In some embodiments, the second wafer 200 may be configured as memory chips.

[0146] Reference Figure 11 and Figure 12, the second wafer 200 can be flipped and bonded to the first wafer 100. In some embodiments, the bonding technology of the second wafer 200 and the first wafer 100 can be oxide bonding, for example, the first top liner 109 formed of oxide and the second top liner 209 formed of oxide.

[0147] When viewed from above, the first alignment marks 105 and the second alignment marks 205 can be arranged to complement each other. That is, the first alignment marks 105 and the second alignment marks 205 do not overlap. This complementary design allows the first alignment marks 105 and the second alignment marks 205 to serve as references for each other during the bonding process. Consequently, the yield and reliability of the semiconductor device 1A can be improved.

[0148] In some embodiments, the plurality of first alignment marks 105 and the plurality of second alignment marks 205 disposed in the upper left region may be referred to as a first group of alignment marks 1S. The alignment marks of the first group of alignment marks 1S (i.e., the first alignment marks 105 and the second alignment marks 205) may extend along the X direction and be parallel to each other.

[0149] In some embodiments, the plurality of first alignment marks 105 and the plurality of second alignment marks 205 disposed in the upper right region may be referred to as a second group of alignment marks 2S. The second group of alignment marks 2S may be spaced apart from the first group of alignment marks 1S along the X-direction. The alignment marks of the second group of alignment marks 2S may extend along the X-direction and be parallel to each other.

[0150] In some embodiments, the plurality of first alignment marks 105 and the plurality of second alignment marks 205 disposed in the lower left region may be referred to as a third group of alignment marks 3S. The third group of alignment marks 3S may be spaced apart from the first group of alignment marks 1S along the Y direction. The alignment marks of the third group of alignment marks 3S may extend along the X direction and be parallel to each other.

[0151] In some embodiments, the plurality of first alignment marks 105 and the plurality of second alignment marks 205 disposed in the lower right region may be referred to as a fourth group of alignment marks 4S. The fourth group of alignment marks 4S may be spaced apart from the first group of alignment marks 1S along a direction S. The direction S may be inclined relative to both the X and Y directions. The alignment marks of the fourth group of alignment marks 4S may extend along the Y direction and be parallel to one another.

[0152] Figure 13 FIG1 is a top view illustrating a semiconductor device 1B according to another embodiment of the present disclosure.

[0153] Reference Figure 13 , the semiconductor element 1B may have Figure 11 13 and 14 are similar in structure. Figure 11Identical or similar elements are designated by similar reference characters, and repeated descriptions are omitted. Semiconductor element 1B may include a fifth set of alignment marks 5S. The fifth set of alignment marks 5S may be spaced apart from the first set of alignment marks 1S along a direction S. The alignment marks of the fifth set of alignment marks 5S (i.e., first alignment mark 105 and second alignment mark 205) may extend along a direction X and be parallel to each other.

[0154] Figure 14 FIG. 2 is a flow chart illustrating a method 20 for manufacturing a semiconductor device 1C according to another embodiment of the present disclosure. Figures 15 to 25 1 is a cross-sectional view illustrating a partial manufacturing process of a semiconductor device 1C according to another embodiment of the present disclosure.

[0155] Reference Figures 14 to 18 In step S21 , a third substrate 301 may be provided, a first dielectric layer 303 may be formed on the third substrate 301 , a second dielectric layer 305 may be formed on the first dielectric layer 303 , and a plurality of second conductive features 313 may be formed on the second dielectric layer 305 .

[0156] Reference Figure 15 , the third substrate 301 may be made of a material similar to Figure 2 The first substrate 101 is formed by the process described in the foregoing, and its description is not repeated here.

[0157] Reference Figure 15 In some embodiments, the first dielectric layer 303 can be formed using a technique such as fluorosilicate glass, borophosphosilicate glass, a spin-on low-K dielectric layer, a chemical vapor deposition low-K dielectric layer, or a combination thereof. In some embodiments, the first dielectric layer 303 can include a self-planarizing material, such as spin-on glass or a spin-on low-K dielectric material, such as SiLK™. The use of a self-planarizing dielectric material can avoid the need for a subsequent planarization step. In some embodiments, the first dielectric layer 303 can be formed using a deposition process, including, for example, chemical vapor deposition, plasma-enhanced chemical vapor deposition, evaporation, or spin coating.

[0158] Reference Figure 15In some embodiments, the second dielectric layer 305 can be, for example, silicon nitride, silicon oxide nitride, silicon oxynitride, or a combination thereof. The second dielectric layer 305 can be fabricated by, for example, chemical vapor deposition, plasma enhanced chemical vapor deposition, or other applicable deposition processes. In some embodiments, the second dielectric layer 305 can serve as a barrier layer to prevent moisture from entering the underlying layers (e.g., the first dielectric layer 303 and the third substrate 301). In some embodiments, the thickness T1 of the first dielectric layer 303 is greater than the thickness T2 of the second dielectric layer 305.

[0159] Reference Figure 15 A layer of second material 503 may be formed on second dielectric layer 305. Second material 503 may be, for example, titanium, titanium nitride, tantalum, tantalum nitride, or the like. The second material 503 layer may be formed by, for example, chemical vapor deposition, physical vapor deposition, sputtering, or a similar process. A layer of third material 505 may be formed on second material 503 layer. Third material 505 may be, for example, copper, a copper alloy, silver, gold, tungsten, aluminum, nickel, or a similar material. The third material 505 layer may be formed by, for example, physical vapor deposition, sputtering, or a similar process. A layer of fourth material 507 may be formed on third material 505 layer. In some embodiments, fourth material 507 and second material 503 may comprise the same material. In some embodiments, fourth material 507 may be, for example, titanium, titanium nitride, tantalum, tantalum nitride, or a similar material. The fourth material 507 layer may be formed by, for example, chemical vapor deposition, physical vapor deposition, sputtering, or a similar process.

[0160] Reference Figure 15 A second mask layer 603 may be formed on the fourth material layer 507. The second mask layer 603 may be a photoresist layer and may include a pattern of a plurality of second conductive features 313.

[0161] Reference Figure 16 An etching process, such as an anisotropic dry etching process, may be performed to remove a portion of the second material 503, the third material 505, and the fourth material 507. After the etching process, the remaining second material 503 may be referred to as a plurality of bottom barrier layers 315, the remaining third material 505 may be referred to as a plurality of intermediate conductive layers 317, and the remaining fourth material 507 may be referred to as a plurality of top barrier layers 319. In some embodiments, the etching process may be a multi-step etching process and may be anisotropic.

[0162] For simplicity, clarity, and ease of description, only one bottom barrier layer 315, one middle conductive layer 317, and one top barrier layer 319 are described. In some embodiments, the thickness T3 of the bottom barrier layer 315 and the thickness T4 of the top barrier layer 319 can be substantially the same. In some embodiments, the thickness T3 of the bottom barrier layer 315 can be greater than the thickness T4 of the top barrier layer 319. In some embodiments, the thickness T5 of the middle conductive layer 317 can be greater than the thickness T3 of the bottom barrier layer 315 or the thickness T4 of the top barrier layer 319.

[0163] Reference Figure 17 , the fifth material 509 layer can be Figure 16 The fifth material 509 is conformally formed on the middle semiconductor element shown. The fifth material 509 can be, for example, titanium, titanium nitride, tantalum, tantalum nitride, or the like. The fifth material 509 layer can be formed by, for example, atomic layer deposition, chemical vapor deposition, physical vapor deposition, sputtering, or the like. In some embodiments, the fifth material 509 and the top barrier layer 319 can comprise the same material.

[0164] Reference Figure 18 An etching process, such as an anisotropic dry etching process, may be performed to remove a portion of the fifth material 509. After the etching process, the remaining fifth material 509 may be referred to as a plurality of spacer barrier layers 321. The plurality of spacer barrier layers 321 may be formed to cover the sidewalls 319SW of the top barrier layer 319, the sidewalls 317SW of the middle conductive layer 317, and the sidewalls 315SW of the bottom barrier layer 315.

[0165] The plurality of spacer barrier layers 321 , the plurality of top barrier layers 319 , the plurality of middle conductive layers 317 , and the plurality of bottom barrier layers 315 are collectively configured as a plurality of second conductive features 313 .

[0166] Reference Figure 14 and Figures 19 to 22 In step S23 , an intermediate dielectric layer 307 may be formed on the second dielectric layer 305 and around the plurality of second conductive features 313 , and a plurality of decoupling units 323 may be formed in the intermediate dielectric layer 307 .

[0167] Reference Figure 19, an intermediate dielectric layer 307 can be formed on the second dielectric layer 305 and cover the plurality of second conductive features 313. A planarization process, such as chemical mechanical polishing, can be performed until the top surfaces of the plurality of second conductive features 313 are exposed to remove excess material and provide a substantially flat surface for subsequent processing steps. In some embodiments, the intermediate dielectric layer 307 can be formed using a material having a different etch rate than the second dielectric layer 305. In some embodiments, the intermediate dielectric layer 307 can be formed using a material such as silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, fluorosilicate glass, borophosphosilicate glass, or a combination thereof. In some embodiments, the intermediate dielectric layer 307 can be formed using a deposition process such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, or other suitable deposition processes.

[0168] It should be understood that in the description of this disclosure, the surface of an element (or feature) disposed at the highest vertical level along the Z direction is referred to as the top surface of the element (or feature). The surface of an element (or feature) disposed at the lowest vertical level along the Z direction is referred to as the bottom surface of the element (or feature).

[0169] Reference Figure 19 , a third mask layer 605 may be formed on the intermediate dielectric layer 307 . In some embodiments, the third mask layer 605 may be a photoresist layer and may include a pattern of a plurality of decoupling units 323 .

[0170] Reference Figure 20 An anisotropic etching process may be performed to remove a portion of the intermediate dielectric layer 307 while forming a plurality of openings 307O. In some embodiments, the anisotropic etching process may be an anisotropic dry etching process. In some embodiments, in the anisotropic etching process, an etching rate ratio of the intermediate dielectric layer 307 to the second dielectric layer 305 may be in a range of approximately 100:1 to approximately 1.05:1, in a range of approximately 15:1 to approximately 2:1, or in a range of approximately 10:1 to approximately 2:1.

[0171] Reference Figure 21 , an expansion etching process may be performed to expand the plurality of openings 307O into a plurality of expanded openings 307E. In some embodiments, the expansion etching process may be an isotropic etching process. In some embodiments, the expansion etching process may be a wet etching process. In some embodiments, during the expansion etching process, an etching rate ratio of the intermediate dielectric layer 307 to the second dielectric layer 305 may be in a range of approximately 100:1 to approximately 1.05:1, in a range of approximately 15:1 to approximately 2:1, or in a range of approximately 10:1 to approximately 2:1. In some embodiments, the sidewalls of the plurality of expanded openings 307E may be curved.

[0172] Reference Figure 22 , the third mask layer 605 may be removed, an insulating material may be deposited to completely fill the plurality of enlarged openings 307E, and then a planarization process, such as chemical mechanical polishing, may be performed until the top surfaces of the plurality of second conductive features 313 are exposed to remove excess material, provide a substantially flat surface for subsequent processing steps, and simultaneously form the plurality of decoupling units 323. In some embodiments, the plurality of decoupling units 323 may have a bottle-shaped cross-sectional profile.

[0173] In some embodiments, the insulating material may be, for example, a porous low-K material.

[0174] In some embodiments, the insulating material may be an energy-removable material. The energy-removable material may include, for example, a thermally decomposable material, a photon-decomposable material, an electron beam-decomposable material, or a combination thereof. For example, the energy-removable material may include a base material and a decomposable porogen that is sacrificially removed upon exposure to an energy source. The base material may include a methylsilsesquioxane-based material. The decomposable porogen may include a porogenous organic compound that provides porosity to the base material of the energy-removable material. After the planarization process, an energy treatment may be performed by applying an energy source. The energy source may include heat, light, or a combination thereof. When heat is used as the energy source, the temperature of the energy treatment may be in the range of approximately 800°C to approximately 900°C. When light is used as the energy source, ultraviolet light may be used. The energy treatment may remove the decomposable porogen from the energy-removable material to create voids (pores), while the base material remains in place. The voids (pores) may reduce the dielectric constant of the plurality of decoupling units 323.

[0175] Reference Figure 22 , multiple decoupling units 323 can be respectively and correspondingly formed between adjacent pairs of the multiple second conductive features 313. In some embodiments, the multiple decoupling units 323 having a low dielectric constant can implement a decoupling function. In some embodiments, the multiple decoupling units 323 can reduce the parasitic capacitance of the multiple second conductive features 313.

[0176] Reference Figure 14 and Figures 23 to 25 In step S25 , a third dielectric layer 309 may be formed on the intermediate dielectric layer 307 , a fourth dielectric layer 311 may be formed on the third dielectric layer 309 , and a plurality of third alignment marks 325 may be formed on the plurality of decoupling units 323 .

[0177] Reference Figure 23In some embodiments, the third dielectric layer 309 may be formed using a fabrication technique such as fluorosilicate glass, borophosphosilicate glass, a spin-on low-k dielectric layer, a chemical vapor deposition low-k dielectric layer, or a combination thereof. In some embodiments, the third dielectric layer 309 may include a self-planarizing material such as spin-on glass or a spin-on low-k dielectric material such as SiLK. TM The use of a self-planarizing dielectric material can avoid the need for a subsequent planarization step. In some embodiments, the third dielectric layer 309 can be formed using a deposition process including, for example, chemical vapor deposition, plasma-enhanced chemical vapor deposition, evaporation, or spin coating. In some embodiments, the third dielectric layer 309 can be formed using the same material as the first dielectric layer 303.

[0178] Reference Figure 23 In some embodiments, the fourth dielectric layer 311 can be, for example, silicon nitride, silicon oxide nitride, silicon oxynitride, or a combination thereof. The fourth dielectric layer 311 can be fabricated by, for example, chemical vapor deposition, plasma enhanced chemical vapor deposition, or other applicable deposition processes. In some embodiments, the fourth dielectric layer 311 can serve as a barrier layer to prevent moisture from entering the underlying layers (e.g., the third dielectric layer 309 and the intermediate dielectric layer 307). In some embodiments, the thickness T6 of the third dielectric layer 309 is greater than the thickness T7 of the fourth dielectric layer 311.

[0179] Reference Figure 23 The first dielectric layer 303 , the second dielectric layer 305 , the intermediate dielectric layer 307 , the third dielectric layer 309 and the fourth dielectric layer 311 may be collectively configured into a dielectric stack DS.

[0180] Reference Figure 23 A fourth mask layer 607 may be formed on the dielectric stack DS. The fourth mask layer 607 may be a photoresist layer and may include a pattern of a plurality of third alignment marks 325 .

[0181] Reference Figure 24 An etching process, such as an anisotropic dry etching process, may be performed to remove a portion of the fourth dielectric layer 311, a portion of the third dielectric layer 309, and a portion of the decoupling units 323 to form a plurality of mark openings 311O. Sidewalls of the plurality of mark openings 311O may be tapered.

[0182] Reference Figure 25, an insulating layer can be formed to completely fill the plurality of mark openings 311O. The insulating layer may include a fluorescent material. In some embodiments, the fluorescent material may be azobenzene. In some embodiments, the insulating layer may be formed by, for example, chemical vapor deposition. A planarization process, such as chemical mechanical polishing, may be performed until the fourth dielectric layer 311 is exposed to remove excess material, provide a substantially flat surface for subsequent processing steps, and simultaneously convert the insulating layer into a plurality of third alignment marks 325. Since the contours of the plurality of third alignment marks 325 are determined by the plurality of mark openings 311O, the sidewalls 325SW of the plurality of third alignment marks 325 may be tapered.

[0183] For the sake of simplicity, clarity and convenience of description, only one decoupling unit 323 and one third arrangement mark 325 are described.

[0184] In some embodiments, the width W1 between the two valleys 323V of the sidewall 323SW of the decoupling unit 323 can be greater than the width W2 of the top surface 325TS of the third alignment mark 325. In some embodiments, the width W2 of the top surface 325TS of the third alignment mark 325 can be greater than the width W3 of the interface between the third alignment mark 325 and the third dielectric layer 309. In some embodiments, the width W3 of the interface between the third alignment mark 325 and the third dielectric layer 307 can be greater than the width W4 of the bottom surface 325BS of the third alignment mark 325. In some embodiments, the width W3 of the third alignment mark 325 at the interface between the third dielectric layer 307 and the third dielectric layer 309 can be greater than the width W5 of the bottom surface 323BS of the decoupling unit 323. In some embodiments, a width ratio between width W1 and width W5 may be in a range of about 1.5:1 to about 1.1:1 or in a range of about 1.3:1 to about 1.1:1.

[0185] The plurality of third alignment marks 325 comprising fluorescent material can improve optical recognition capability in a subsequent wafer bonding process.

[0186] Figure 26 is a cross-sectional view illustrating a semiconductor device 1D according to another embodiment of the present disclosure.

[0187] Reference Figure 26 , the semiconductor element 1D may have Figure 25 A similar structure is shown in . Figure 26 Zhongyu Figure 25 The same or similar elements have been marked with like reference symbols, and repeated descriptions have been omitted.

[0188] In the semiconductor element 1D, the bottom surface 325BS of the third alignment key 325 may be disposed on the decoupling unit 323 instead of extending to the decoupling unit 323 .

[0189] One embodiment of the present disclosure provides a semiconductor device, comprising a first wafer, the first wafer comprising a first substrate and a plurality of first alignment marks disposed on the first substrate and parallel to each other; and a second wafer, the second wafer disposed on the first wafer and comprising a plurality of second alignment marks disposed above the plurality of first alignment marks. The plurality of second alignment marks are arranged parallel to the plurality of first alignment marks and are adjacent to the plurality of first alignment marks when viewed from above. The plurality of first alignment marks and the plurality of second alignment marks comprise a fluorescent material. The plurality of first alignment marks and the plurality of second alignment marks are collectively configured to form a first group of alignment marks.

[0190] Another embodiment of the present disclosure provides a semiconductor device comprising a substrate; a dielectric stack disposed on the substrate; two conductive features disposed in the dielectric stack; a decoupling unit disposed in the dielectric stack between the two second conductive features and having a bottle-shaped cross-sectional profile; and an alignment mark disposed on the decoupling unit. The alignment mark comprises a fluorescent material.

[0191] Another embodiment of the present disclosure provides a method for fabricating a semiconductor device, comprising: providing a first substrate; forming a plurality of mutually parallel first alignment marks on the first substrate, wherein the first substrate and the plurality of first alignment marks together form a first wafer; providing a second chip including a plurality of mutually parallel second alignment marks; and bonding the second wafer to the first wafer. The plurality of second alignment marks are arranged parallel to the plurality of first alignment marks and are adjacent to the plurality of first alignment marks when viewed from above. The plurality of first alignment marks and the plurality of second alignment marks include a fluorescent material.

[0192] Another embodiment of the present disclosure provides a method for fabricating a semiconductor device, comprising: providing a substrate; forming a first dielectric layer on the substrate; forming a second dielectric layer on the first dielectric layer; forming two second conductive features on the second dielectric layer; forming an intermediate dielectric layer on the second dielectric layer and surrounding the two second conductive features; performing an expansion etching process to form an expanded opening in the intermediate dielectric layer; forming a decoupling unit in the expanded opening; and forming an alignment mark on the decoupling unit. The alignment mark comprises a fluorescent material.

[0193] Due to the design of the semiconductor device disclosed herein, the multiple alignment marks 105, 205, and 325 comprising a fluorescent material can improve optical recognition during the wafer bonding process. Furthermore, the complementary design allows the multiple first alignment marks 105 and the multiple second alignment marks 205 to serve as a reference for each other during the bonding process. Consequently, the yield and reliability of the semiconductor device 1A can be improved.

[0194] Although the present disclosure and its advantages have been described in detail, it should be understood that some changes, substitutions, and alterations may be made without departing from the spirit and scope of the present disclosure as defined by the claims. For example, many of the processes described above may be implemented in different ways, and may be replaced by other processes or combinations thereof.

[0195] Furthermore, the scope of the present disclosure is not limited to the specific embodiments of the processes, machines, manufacture, compositions of matter, means, methods, and steps described in the specification. Those skilled in the art will appreciate from the disclosure of this disclosure that existing or future developed processes, machines, manufacture, compositions of matter, means, methods, or steps that function the same as or achieve substantially the same results as the corresponding embodiments described herein may be used in accordance with the present disclosure. Accordingly, such processes, machines, manufacture, compositions of matter, means, methods, or steps are intended to be encompassed by the claims of this disclosure.

Claims

1. A semiconductor device comprising: A first wafer comprising: a first substrate; and a plurality of first alignment marks disposed on the first substrate and parallel to each other; and a second wafer, disposed on the first wafer, comprising: a plurality of second alignment marks disposed above the plurality of first alignment marks; wherein the plurality of second alignment marks are arranged in parallel with the plurality of first alignment marks and are adjacent to the plurality of first alignment marks in a top view; wherein the plurality of first alignment marks and the plurality of second alignment marks comprise a fluorescent material; The plurality of first alignment marks and the plurality of second alignment marks are collectively configured as a first group of alignment marks. 2 . The semiconductor device as claimed in claim 1 , wherein the fluorescent material comprises azobenzene.

3. The semiconductor device according to claim 2, further comprising a second set of alignment marks separated from the first set of alignment marks along a first direction; The first group of alignment marks extends along a second direction perpendicular to the first direction, and the second group of alignment marks extends along the first direction.

4. The semiconductor device according to claim 3, further comprising a third set of alignment marks separated from the first set of alignment marks along the second direction; The third group of alignment marks extends along the first direction.

5. The semiconductor device as claimed in claim 4, further comprising a fourth set of alignment marks, the fourth set of alignment marks being separated from the first set of alignment marks along a direction inclined to each of the first direction and the second direction; wherein the fourth set of alignment marks extends along the second direction.

6. The semiconductor device according to claim 4, further comprising a fifth set of alignment marks, the fifth set of alignment marks being separated from the first set of alignment marks along a direction inclined to each of the first direction and the second direction; The fifth set of alignment marks extends along the first direction. 7 . The semiconductor device of claim 2 , wherein the first wafer comprises a plurality of first conductive features disposed to horizontally surround the plurality of first alignment marks. 8 . The semiconductor device of claim 7 , wherein the first wafer comprises a first bottom liner disposed between the plurality of first conductive features and the plurality of first alignment marks. 9 . The semiconductor device as claimed in claim 8 , wherein the first wafer comprises a first top liner disposed on the plurality of first alignment marks and the first bottom liner. 10 . The semiconductor device as claimed in claim 9 , wherein the second wafer comprises a second top liner disposed between the plurality of second alignment marks and the first top liner. 11 . The semiconductor device of claim 10 , wherein the second wafer comprises a plurality of second conductive features horizontally surrounding the plurality of second alignment marks and the second top liner. 12 . The semiconductor device of claim 11 , wherein the second wafer comprises a second bottom liner disposed between the second alignment marks and the second conductive features, and between the second conductive features and the second top liner. 13 . The semiconductor device as claimed in claim 2 , wherein the first wafer is configured as a logic chip, and the second wafer is configured as a memory chip. 14 . The semiconductor device as claimed in claim 2 , wherein the first wafer is configured as a memory chip, and the second wafer is configured as a memory chip.

15. A method for preparing a semiconductor element, comprising: providing a first substrate; forming a plurality of first alignment marks parallel to each other on the first substrate, wherein the first substrate and the plurality of first alignment marks are collectively configured into a first wafer; Providing a second wafer including a plurality of second alignment marks parallel to each other; as well as bonding the second wafer to the first wafer; wherein the plurality of second alignment marks are arranged in parallel with the plurality of first alignment marks and are adjacent to the plurality of first alignment marks in a top view; The plurality of first alignment marks and the plurality of second alignment marks include a fluorescent material. 16 . The method for fabricating a semiconductor device as claimed in claim 15 , wherein the fluorescent material comprises azobenzene.

17. The method for manufacturing a semiconductor device according to claim 16, further comprising: forming a plurality of first conductive features on the first substrate; conformally forming a first bottom liner covering the first substrate and the plurality of first conductive features; forming the plurality of first alignment marks on the first bottom liner and between the plurality of first conductive features; as well as forming a first top liner covering the first bottom liner and the plurality of first alignment marks; The first substrate, the plurality of first conductive features, the plurality of first alignment marks, the first bottom liner and the first top liner are collectively configured to form the first wafer.

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