A trench gate power device and silicide gate manufacturing method

Abstract

The application discloses a trench gate power device and a silicide gate manufacturing method, which comprises a device body, a front metal layer, a metalized drain and a plurality of trench gates, wherein: the top of the device body is covered with the front metal layer, the top of the device body is recessed with a plurality of gate trenches, the area between each adjacent gate trench is a semiconductor platform area, and the semiconductor platform area is connected with a metal source; each trench gate comprises a gate dielectric layer and a gate conductive layer, the gate conductive layer is located in the gate trench, the top of the gate conductive layer is lower than the upper surface of the semiconductor platform area, and the part of the gate trench which is higher than the gate conductive layer forms a dielectric groove; the top of the gate conductive layer is covered with a first dielectric, the first dielectric is connected with a metal gate, and a diffusion layer is formed at the joint of the first dielectric and the gate conductive layer. The trench gate power device and the silicide gate manufacturing method provided by the application can reduce the gate square resistance of the trench gate device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, specifically to a trench gate power device and a method for manufacturing a silicide gate. Background Technology

[0002] During the switching process of trench gate devices, the higher the gate resistance, the slower the switching speed. Therefore, chip design aims to minimize the gate resistance. Furthermore, trench gate devices are composed of tens of thousands or even millions of cells connected in parallel. Time delays exist at different points on the chip due to the gate resistance. Reducing the gate resistance allows for more synchronized turn-on and turn-off times among the individual cells.

[0003] In related technologies, the main way to reduce gate resistance is to increase the gate bus. The gate bus uses metal traces and adds multiple gate metal feed lines to reduce gate resistance. This is a layout-based method to reduce gate resistance, which is widely used in large chips, such as chips with an area exceeding 100 square millimeters. Typically, three or even four or more gate metal feed lines are used. To reduce the resistance of the metal feed lines, their width is also very wide, usually greater than 50μm, or even exceeding 100μm. The metal thickness is also very thick, usually 4μm or more. However, excessively wide and numerous metal feed lines lead to wasted active area. Furthermore, simply using metal feed lines is insufficient; it is also necessary to reduce the sheet resistance of the gate polysilicon. Summary of the Invention

[0004] The purpose of this invention is to overcome the above-mentioned technical deficiencies and provide a trench gate power device to solve the problem of high sheet resistance of polysilicon gate in trench gate devices in the prior art.

[0005] To achieve the above technical objectives, the technical solution of the present invention is as follows: A trench gate power device, comprising: a device body, a front metal layer, a metallized drain, and a plurality of trench gates, wherein: the top of the device body covers the front metal layer, the front metal layer includes a metal gate and a metal source, the bottom of the device body is connected to the metallized drain, a plurality of gate trenches are recessed at the top of the device body, the region between each adjacent gate trench is a semiconductor platform region, the semiconductor platform region is connected to the metal source; each trench gate includes a gate dielectric layer and a gate conductive layer, the gate conductive layer is located in the gate trench, and the top of the gate conductive layer is lower than the upper surface of the semiconductor platform region, the portion of the gate trench above the gate conductive layer forms a dielectric trench, the gate dielectric layer fills the gap between the gate trench and the gate conductive layer; the top of the gate conductive layer is covered with a first dielectric, the first dielectric is connected to the metal gate, and a diffusion layer is formed at the junction of the first dielectric and the gate conductive layer.

[0006] Preferably, a partition gap is formed between the first medium and the sidewall of the medium tank.

[0007] Preferably, the device body is divided from top to bottom into a semiconductor platform region, a first conductivity type channel region, a second conductivity type drift region, and a semiconductor substrate.

[0008] Preferably, a buffer layer is further disposed between the second conductivity type drift region and the semiconductor substrate, and the doping concentration of the buffer layer is the same as that of the second conductivity type drift region.

[0009] Preferably, the semiconductor platform region includes a plurality of first heavily doped half regions and a plurality of second heavily doped half regions, with a first heavily doped half region disposed on each side of the gate trench, and each second heavily doped half region located between two adjacent first heavily doped half regions.

[0010] Preferably, the first conductivity type is P-type and the second conductivity type is N-type; or, the first conductivity type is N-type and the second conductivity type is P-type.

[0011] Preferably, the first medium also covers the semiconductor platform region.

[0012] Preferably, the gate dielectric layer is a gate oxide layer, and the gate conductive layer is a polysilicon gate.

[0013] The present invention also provides a method for manufacturing a silicide gate for a trench gate power device, comprising the following steps:

[0014] S1, perform self-aligned back etching of the gate conductive layer, and etch the top surface of the gate conductive layer in the gate trench back to a level below the first surface to form a dielectric trench, the dielectric trench having a first depth;

[0015] S2, depositing an intermediate medium in the medium tank and then etching back to form a sidewall composed of the intermediate medium on the sidewall of the medium tank, the sidewall having a first thickness;

[0016] S3, depositing a first medium on the first surface side, such that the first medium is bonded to the gate conductive layer at the bottom of the sidewall, and forming a diffusion layer at the bonding point, wherein the first medium has a second thickness;

[0017] S4, the sidewall is removed by etching to form a partition gap.

[0018] Preferably, the semiconductor platform region of the trench gate power device is a silicon substrate, and step S3 further includes: the first dielectric is also deposited in the semiconductor platform region.

[0019] Preferably, the trench gate power device is an IGBT device, and the method for manufacturing the silicide gate of the trench gate power device further includes the following steps:

[0020] S5, the first medium deposited on the surface of the semiconductor platform region is removed by photolithography.

[0021] Preferably, the first depth is 0.20 μm to 0.30 μm.

[0022] Preferably, the sidewall is made of silicon nitride or silicon dioxide, and the first thickness is [missing information].

[0023] Preferably, the first medium is a metal, and the second thickness is...

[0024] Preferably, the reaction temperature for the first medium to bond with the gate conductive layer is 800℃~1000℃, and the reaction time is 25~35 minutes.

[0025] Preferably, the first dielectric and the gate conductive layer are bonded together using a rapid thermal annealing process, with an annealing temperature of 700℃~950℃ and a duration of 25~35 seconds.

[0026] Compared with the prior art, the beneficial effects of the present invention include: a plurality of gate trenches are recessed at the top of the device body, and a semiconductor platform region is formed between adjacent gate trenches. A gate dielectric layer and a gate conductive layer are formed in the gate trenches, and the top of the gate conductive layer is lower than the semiconductor platform region, so that the top of the gate conductive layer and the sidewall of the semiconductor platform region enclose a dielectric trench, which facilitates subsequent self-aligned etching. The top of the gate conductive layer is also covered with a first dielectric, and a diffusion layer is formed at the junction of the first dielectric and the gate conductive layer. The device body is covered with a front metal layer to form a metal gate and a metal source. The first dielectric is also connected to the metal gate. The resistivity of the diffusion layer is between that of the polysilicon gate and the metal gate. Therefore, compared with the traditional polysilicon gate, the sheet resistance of the gate polysilicon of the device is greatly reduced. Attached Figure Description

[0027] Figure 1 This is a flowchart of a method for manufacturing a silicide gate for a trench gate power device provided by the present invention;

[0028] Figure 2 This is a simplified structural diagram of a trench gate power device provided by the present invention;

[0029] Figure 3 This is a simplified structural diagram of a trench gate power device after the deposition of an intermediate dielectric, as provided by the present invention.

[0030] Figure 4 This is a simplified structural diagram of a trench gate power device after deposition of a first dielectric, as provided by the present invention.

[0031] Figure 5 This is a simplified structural diagram of a trench gate power device after removing the first dielectric in the semiconductor platform region, as provided by the present invention.

[0032] Reference numerals: 1-Device body, 2-Front-side metal layer, 3-Trench gate, 4-First dielectric, 5-Intermediate dielectric, 11-Gate trench, 12-Semiconductor platform region, 13-First conductivity type channel region, 14-Second conductivity type drift region, 15-Semiconductor substrate, 31-Gate dielectric layer, 32-Gate conductive layer, 33-Dielectric trench, 121-First heavily doped half-region, 122-Second heavily doped half-region. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0034] Please see Figure 1 and Figure 2This embodiment provides a trench gate power device, which includes: a device body 1, a front metal layer 2, a metallized drain, and multiple trench gates 3, wherein:

[0035] The top of the device body 1 is covered with a front metal layer 2, which includes a metal gate and a metal source. The bottom of the device body 1 is connected to a metallized drain. Multiple gate trenches 11 are recessed at the top of the device body 1. The area between each adjacent gate trench 11 is a semiconductor platform region 12, which is connected to the metal source.

[0036] In a preferred embodiment, the gate trench 11 is formed using a photolithography and etching process. If anisotropic etching is used, to ensure that the bottom of the gate trench 11 is as smooth as possible (because it needs to withstand a large electric field), the etching process should be adjusted to isotropic etching near the end of the anisotropic etching process. Alternatively, oxidation can be performed after etching to make the top as smooth as possible. Therefore, the width of the opening (i.e., the top) of the finally formed gate trench 11 is usually greater than 0.2 μm.

[0037] In a preferred embodiment, the front metal layer 2 is patterned to form the metal gate and metal source, which can greatly shorten the manufacturing cycle and improve production efficiency. The material of the front metal layer 2 is usually aluminum, with a thickness of about 4 micrometers. By increasing the thickness of the source metal, the source resistance can be reduced, and the heat capacity of the trench gate power device can also be increased, which helps to dissipate heat during transients.

[0038] Each trench gate 3 includes a gate dielectric layer 31 and a gate conductive layer 32. The gate conductive layer 32 is located within the gate trench 11, and the top of the gate conductive layer 32 is lower than the upper surface of the semiconductor platform region 12. The portion of the gate trench 11 above the gate conductive layer 32 forms a dielectric trench 33. The gate dielectric layer 31 fills the gap between the gate trench 11 and the gate conductive layer 32. The gate conductive layer 32 is made of silicon substrate and is doped with different elements depending on the type of trench gate power device. For example, if the trench gate power device is an N-type trench gate, then the gate conductive layer 32 is heavily N-type doped; if the trench gate power device is a P-type trench gate, then the gate conductive layer 32 is heavily P-type doped.

[0039] The top of the gate conductive layer 32 is covered with a first dielectric 4. In a preferred embodiment, the first dielectric 4 is a metal, such as titanium. The first dielectric 4 reacts with the silicon substrate of the gate conductive layer 32 to generate a metal silicide diffusion layer. This metal silicide diffusion layer is connected to the front metal layer 2, which can effectively reduce the connection resistance between the front metal layer 2 and the gate conductive layer 32.

[0040] In a preferred embodiment, a gap is formed between the first dielectric 4 and the sidewall of the dielectric trench 33 to prevent the first dielectric 4 from conducting with the semiconductor substrate 15. The first dielectric 45 is connected to the metal gate, and the semiconductor platform region 12 of the dielectric trench 33 is connected to the metal source. Therefore, the first dielectric 4 and the dielectric trench 33 cannot conduct. By setting a gap, the first dielectric 4 and the dielectric trench 33 are prevented from contacting and conducting.

[0041] In a preferred embodiment, the device body 1 is divided from top to bottom into a semiconductor platform region 12, a first conductivity type channel region 13, a second conductivity type drift region 14, and a semiconductor substrate 15. The semiconductor substrate 15 is connected to the drain. To reduce back diffusion of the semiconductor substrate 15, it is typically fabricated using heavily doped arsenic. However, since the lowest resistivity of heavily doped phosphorus substrates currently achieved is lower than that of heavily doped arsenic substrates, heavily doped phosphorus substrates are frequently used in applications where substrate resistance is relatively high, such as low-voltage devices below 40V. A thinner substrate not only provides better heat dissipation for the device but also significantly reduces substrate resistance. The selection of the second conductivity type drift region 14 determines the breakdown voltage of the device. Generally, the higher the breakdown voltage of the device, the thicker the second conductivity type drift region 14 and the lower the doping concentration of the second conductivity type drift region 14.

[0042] The first conductivity type channel region 13 is formed by channel ion implantation, which typically requires passing through a shielding oxide layer to prevent tunneling and thus prevent excessively deep implantation. The shielding oxide layer can be deposited or grown thermally. The channel ion implantation voltage for the first conductivity type channel region 13 is typically 60 keV to 150 keV, the implantation dose is between 5e¹²cm⁻² and 2e¹³cm⁻², and the implanted impurity is boron.

[0043] Preferably, for a 20V trench-gate MOSFET device, a highly doped phosphorus semiconductor substrate 15 is typically used. The resistivity of the semiconductor substrate 15 is 0.0011 Ω*cm, and the maximum thickness of the thinned semiconductor substrate 15 is 150 μm. The semiconductor substrate 15 is an N-type highly doped substrate with a bulk concentration of 1e19 / cm3 or higher. This high doping concentration is to reduce the resistance of the semiconductor substrate 15. The drain region is formed by the N-type highly doped semiconductor substrate 15, and a drain electrode composed of a back metal layer is formed on the back side of the semiconductor substrate 15. The trench gate 3 is formed in the second conductivity type drift region 14. The second conductivity type drift region 14 is a single-layer drift region with a resistivity of 0.15 Ω*cm and a thickness of 4 μm. The width of the gate trench 11 of the trench-gate MOSFET device is 0.2 μm.

[0044] It should be noted that a buffer layer is also provided between the second conductivity type drift region 14 and the semiconductor substrate 15. Its main purpose is to prevent impurity atoms from the highly doped semiconductor substrate 9 from diffusing into the second conductivity type drift region 14 due to the thermal process, thus increasing the doping concentration of the drift region and reducing the device's breakdown voltage. The doping concentration of the buffer layer is usually consistent with the doping concentration of the second conductivity type drift region 14.

[0045] More preferably, the semiconductor platform region 12 includes a plurality of first heavily doped half-regions 121 and a plurality of second heavily doped half-regions 122. A first heavily doped half-region 121 is disposed on each side of the gate trench 11, and each second heavily doped half-region 122 is located between two adjacent first heavily doped half-regions 121. The first heavily doped half-regions are doped with a first conductivity type, and the second heavily doped half-regions 122 are doped with a second conductivity type.

[0046] It should be noted that when the trench gate device is a P-channel type, the first conductivity type is P-type and the second conductivity type is N-type. When the trench gate device is an N-channel type, the first conductivity type is N-type and the second conductivity type is P-type. In a preferred embodiment, the first dielectric 4 also covers the semiconductor platform region 12. For silicon-based devices, covering the semiconductor platform region 12 with the first dielectric 4 will also form a metal silicide layer, which can reduce the source on-resistance. For IGBTs (Insulated Gate Bipolar Transistors), the formation of a metal silicide layer in the semiconductor platform region 12 will reduce the device's breakdown voltage. This metal silicide layer can be removed by photolithography. The same process can be achieved for other silicon-based devices, which will not be elaborated here.

[0047] In a preferred embodiment, the gate dielectric layer 31 can be a gate nitride layer or a gate oxide nitride layer. In this embodiment, a gate oxide layer is preferred. This gate oxide layer is formed using a thermal oxidation process. The thickness of the gate oxide layer determines the breakdown voltage that the device gate can withstand. The thickness of the gate oxide layer is also closely related to the threshold voltage of the device. Generally, the lower the threshold voltage required by the device, the thinner the gate oxide layer.

[0048] In summary, the trench gate power device provided by this invention has multiple gate trenches recessed at the top of the device body. A semiconductor plateau region is formed between adjacent gate trenches. A gate dielectric layer and a gate conductive layer are formed in the gate trenches, and the top of the gate conductive layer is lower than the semiconductor plateau region. This allows the top of the gate conductive layer to form a dielectric trench with the sidewall of the semiconductor plateau region, facilitating subsequent self-aligned etching. A first dielectric layer also covers the top of the gate conductive layer, and a diffusion layer is formed at the junction of the first dielectric layer and the gate conductive layer. The device body is covered with a front-side metal layer, forming a metal gate and a metal source. The first dielectric layer is also connected to the metal gate. The resistivity of the diffusion layer is between that of a polysilicon gate and a metal gate. Therefore, compared to a traditional polysilicon gate, the sheet resistance of the polysilicon gate of the device is significantly reduced.

[0049] The present invention also provides a method for manufacturing a silicide gate for a trench gate power device, comprising the following steps:

[0050] S1, perform self-aligned back etching of the gate conductive layer, and etch the top surface of the gate conductive layer in the gate trench back to a level below the first surface to form a dielectric trench with a first depth;

[0051] S2, please refer to Figure 3 An intermediate medium is deposited in a medium tank and then etched back to form a sidewall composed of the intermediate medium on the sidewall of the medium tank, the sidewall having a first thickness.

[0052] S3, please refer to Figure 4 A first dielectric is deposited on the first surface side, the first dielectric having a second thickness, such that the first dielectric is bonded to the gate conductive layer at the bottom of the sidewall and a diffusion layer is formed at the bonding point;

[0053] S4, the sidewalls are removed by etching to create partition gaps.

[0054] In a preferred embodiment, the semiconductor platform region of the trench gate power device is a silicon substrate. Step S3 further includes: a first dielectric is also deposited in the semiconductor platform region. Therefore, for silicon devices, covering the semiconductor platform region with the first dielectric will also form a metal silicide layer, which can reduce the source on-resistance.

[0055] Please see Figure 5 In a preferred embodiment, the trench gate power device is an IGBT device, and the method for manufacturing the silicide gate of the trench gate power device further includes the following steps:

[0056] S5, the first dielectric material deposited on the surface of the semiconductor platform region is removed by photolithography.

[0057] As a preferred embodiment, the first depth is 0.20 to 0.30 μm. Since the first dielectric needs to be deposited in the dielectric trench, the depth of the dielectric trench needs to be made deeper than the normal depth. The normal trench MOSFET depth is about 0.1 μm.

[0058] In a preferred embodiment, the intermediate medium may be a nitride, oxide, or oxynitride; in this embodiment, silicon nitride or silicon dioxide is preferred, and the first thickness of the sidewall is [missing information]. ( A unit of length ).

[0059] More preferably, the first thickness is

[0060] In a preferred embodiment, the first medium is made of a metal material, such as titanium, nickel, or cobalt. The gate conductive layer is generally a silicon substrate, and therefore can be bonded to the gate conductive layer to form a diffusion layer of a metal silicide. It should be noted that when using a substrate of other silicon elements, the gate conductive layer can also be bonded to the first medium to form a diffusion layer of the corresponding metal compound. The second thickness is...

[0061] More preferably, the second thickness is

[0062] In a preferred embodiment, the reaction temperature for bonding the first dielectric with the gate conductive layer is 800°C to 1000°C, and the reaction time is 25 to 35 minutes.

[0063] In a preferred embodiment, the first dielectric layer is bonded to the gate conductive layer using a rapid thermal annealing process, with an annealing temperature of 700°C to 950°C and a duration of 25 to 35 seconds.

[0064] In summary, the silicide gate manufacturing method provided by this invention involves depositing an intermediate dielectric in a dielectric trench after gate etching and source / drain implantation, and then etching back to form sidewalls. A first dielectric is then deposited in the dielectric trench. The intermediate dielectric and the first dielectric do not react, but the first dielectric reacts with the surface of the gate conductive layer and bonds to form a diffusion layer. The first dielectric is connected to the gate of the front metal layer. The resistance of the diffusion layer is between that of metal and single-crystal silicon. Therefore, compared to traditional single-crystal silicon gates, this method effectively reduces the sheet resistance of the gate polysilicon. Afterwards, etching removes unwanted intermediate dielectric, leaving a gap in the dielectric trench to prevent the gate from conducting with the source. Furthermore, multiple annealing processes can be used to form a silicide connection with even lower resistance, further reducing the sheet resistance of the gate polysilicon.

[0065] Although this application has been shown and described with respect to one or more implementations, equivalent variations and modifications will occur to those skilled in the art based on a reading and understanding of this specification and drawings. This application includes all such modifications and variations and is limited only by the scope of the appended claims. In particular, with respect to the various functions performed by the aforementioned components, the terminology used to describe such components is intended to correspond to any component (unless otherwise indicated) that performs the specified function of the component (e.g., is functionally equivalent to it), even if structurally not equivalent to the disclosed structure performing the functions in the exemplary implementations of this specification shown herein.

[0066] That is, the above are merely embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application’s specification and drawings, such as the combination of technical features between embodiments, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

[0067] Furthermore, it should be understood that in the description of this application, the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Additionally, for structural elements with the same or similar characteristics, this application may use the same or different reference numerals for identification. Moreover, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified. In this application, the word "exemplary" is used to mean "used as an example, illustration, or explanation." Any embodiment described as "exemplary" in this application is not necessarily to be construed as being more preferred or advantageous than other embodiments. This application has been provided above to enable any person skilled in the art to implement and use it. Various details have been set forth in the above description for purposes of explanation. It should be understood that those skilled in the art will recognize that this application can be implemented without using these specific details. In other embodiments, well-known structures and processes have not been described in detail to avoid obscuring the description of this application with unnecessary detail. Therefore, this application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed herein.

Claims

1. A trench gate power device, characterized in that, include: The device body consists of a front-side metal layer, a metallized drain, and multiple trench gates, among which: The top of the device body is covered by the front metal layer, which includes a metal gate and a metal source. The bottom of the device body is connected to the metallized drain. The top of the device body is recessed with multiple gate trenches. The area between each adjacent gate trench is a semiconductor platform region. The semiconductor platform region is connected to the metal source. The semiconductor platform region includes multiple first heavily doped half-regions and multiple second heavily doped half-regions with different doping types. A first heavily doped half-region is respectively disposed on both sides of the gate trench. Each second heavily doped half-region is located between two adjacent first heavily doped half-regions. Each of the trench gates includes a gate dielectric layer and a gate conductive layer, the gate conductive layer being located within the gate trench, and the top of the gate conductive layer being lower than the upper surface of the semiconductor platform region. The portion of the gate trench above the gate conductive layer forms a dielectric trench, and the gate dielectric layer fills the gap between the gate trench and the gate conductive layer. The top of the gate conductive layer is covered with a first dielectric, which is connected to the metal gate. A diffusion layer is formed at the junction of the first dielectric and the gate conductive layer, and a partition gap is formed between the first dielectric and the sidewall of the dielectric trench. The gate conductive layer is a polysilicon gate, and the resistivity of the diffusion layer is between that of the polysilicon gate and the metal gate.

2. The trench gate power device according to claim 1, characterized in that, The main body of the device is divided into the semiconductor platform region, the first conductivity type channel region, the second conductivity type drift region, and the semiconductor substrate from top to bottom.

3. A trench gate power device according to claim 2, characterized in that, The first conductivity type is P-type, and the second conductivity type is N-type; or, the first conductivity type is N-type, and the second conductivity type is P-type.

4. A trench gate power device according to claim 1, characterized in that, The first medium also covers the semiconductor platform region.

5. A trench gate power device according to claim 1, characterized in that, The gate dielectric layer is a gate oxide layer.

6. A method for manufacturing a silicide gate for a trench gate power device, characterized in that, Includes the following steps: S1, perform self-aligned back etching of the gate conductive layer, and etch the top surface of the gate conductive layer in the gate trench back to a level below the first surface to form a dielectric trench, the dielectric trench having a first depth; S2, depositing an intermediate medium in the medium tank and then etching back to form a sidewall composed of the intermediate medium on the sidewall of the medium tank, the sidewall having a first thickness; S3, depositing a first medium on the first surface side, such that the first medium is bonded to the gate conductive layer at the bottom of the sidewall, and forming a diffusion layer at the bonding point, wherein the first medium has a second thickness; S4, the sidewalls are removed by etching to form a partition gap, the first dielectric is connected to the metal gate, the gate conductive layer is a polysilicon gate, and the resistivity of the diffusion layer is between that of the polysilicon gate and the metal gate.

7. The method for manufacturing a silicide gate for a trench gate power device according to claim 6, characterized in that, The semiconductor platform region of the trench gate power device is a silicon substrate, and step S3 further includes: the first dielectric is also deposited in the semiconductor platform region.

8. The method for manufacturing the silicide gate of the trench gate power device according to claim 7, characterized in that, The trench gate power device is an IGBT device, and the method for manufacturing the silicide gate of the trench gate power device further includes the following steps: S5, the first medium deposited on the surface of the semiconductor platform region is removed by photolithography.

9. The method for manufacturing the silicide gate of the trench gate power device according to claim 6, characterized in that, The first depth is 0.20 μm to 0.30 μm.

10. The method for manufacturing the silicide gate of a trench gate power device according to claim 6, characterized in that, The sidewall is made of silicon nitride or silicon dioxide, and the first thickness is 500 Å to 2000 Å.

11. The method for manufacturing the silicide gate of a trench gate power device according to claim 6, characterized in that, The first medium is a metal, and the second thickness is 300 Å to 1500 Å.

12. The method for manufacturing the silicide gate of a trench gate power device according to claim 6, characterized in that, The reaction temperature for the first medium to bond with the gate conductive layer is 800℃~1000℃, and the reaction time is 25~35 minutes.

13. The method for manufacturing the silicide gate of the trench gate power device according to claim 6, characterized in that, The first dielectric is bonded to the gate conductive layer using a rapid thermal annealing process, with an annealing temperature of 700℃~950℃ and a duration of 25~35 seconds.

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