A circuit and method for ordering phases in a multi-phase clock signal
By designing a circuit with a series and parallel connection of a signal activation module, a CLOCK input module, a weak potential module, and an inverting module, and utilizing the on and off states of NMOS and PMOS transistors, the problem of not being able to distinguish multi-phase CLOCK signals in the prior art is solved. This achieves the sorting and clarification of phases, facilitating the subsequent frequency division process.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- JULI XINCHUANG (WUXI) TECH CO LTD
- Filing Date
- 2023-02-22
- Publication Date
- 2026-04-17
AI Technical Summary
In existing technologies, after frequency division of the CLOCK signal, it is impossible to distinguish different phases, which makes it impossible to effectively continue to the next step of frequency division.
A circuit was designed including a signal activation module, a CLOCK input module, a weak potential module, an inverting module, and a potential output terminal. By connecting these modules in series and parallel, and utilizing the on and off states of NMOS and PMOS transistors, the phase sequencing of multi-phase CLOCK signals can be achieved.
Phase sorting of multi-phase CLOCK signals was achieved, clarifying the order of each phase signal, which facilitates further frequency division processing.
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Figure CN116248089B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of clock frequency division technology, specifically relating to a circuit and method for phase sorting in multi-phase CLOCK signals. Background Technology
[0002] Currently, a single frequency for CLOCK signals is insufficient to meet the demands of integrated circuits. Most devices or circuits in integrated circuits can only function properly with CLOCK signals within a certain range of frequencies and phases. Therefore, integrated circuits require multiple CLOCK signals of different frequencies or phases. To meet the multi-frequency, multi-phase CLOCK signal requirements of integrated circuits, a multi-phase CLOCK signal with the highest frequency can be input into the integrated circuit. Then, by dividing the high-frequency multi-phase CLOCK signal, CLOCK signals of different frequencies or phases can be obtained.
[0003] However, in the existing technology, after performing frequency division on the CLOCK signal once to obtain a multi-phase CLOCK signal, it is impossible to distinguish the different phases, that is, it is impossible to distinguish which one is the first phase CLOCK signal, which one is the second phase CLOCK signal, or which one is the last phase CLOCK signal, which makes it impossible to effectively continue frequency division. Summary of the Invention
[0004] This invention provides a circuit and method for phase sorting in multi-phase CLOCK signals, aiming to solve the problem in the prior art that when performing frequency division of multi-phase CLOCK signals, it is impossible to distinguish which is the first phase CLOCK signal and which is the last phase CLOCK signal, resulting in the inability to effectively continue frequency division.
[0005] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:
[0006] In a first aspect, the present invention provides a circuit for phase sorting in a multi-phase CLOCK signal, comprising:
[0007] Signal activation module, CLOCK input module, weak potential module, inverting module, and potential output terminal;
[0008] The signal activation module and the CLOCK input module are connected in series; the CLOCK input module is connected in series with the weak potential module; the output terminal of the weak potential module is connected to the input terminal of the inverting module; the output terminal of the inverting module is connected to the potential output terminal.
[0009] When the signal activation module is not activated, the output terminal of the weak potential module is at a high potential, the input terminal of the inverting module is at a high potential, and the output terminal is at a low potential, and the potential output terminal outputs a low potential.
[0010] When the signal activation module is activated and the CLOCK input module receives the CLOCK signal, the output terminal of the weak potential module is at a low potential, the input terminal of the inverting module is at a low potential, and the output terminal is at a high potential, and the potential output terminal outputs a high potential.
[0011] A further embodiment: The CLOCK input module includes an NMOS transistor M0; the CLOCK input module receives the CLOCK signal through the gate of the NMOS transistor M0.
[0012] Based on the above scheme, the gate of the NMOS transistor M0 receives the CLOCK signal, which enables the gate to be loaded with voltage, thereby forming an electronic channel between the source and drain of the NMOS transistor M0, allowing current to flow from the drain to the source through the electronic channel, and the NMOS transistor M0 is turned on.
[0013] A further embodiment: The signal activation module includes an NMOS transistor M16; the gate of the NMOS transistor M16 receives a activation signal; the signal activation module is activated by the activation signal.
[0014] The NMOS transistor M16 is connected in series with the NMOS transistor M0.
[0015] Based on the above scheme, the gate of the NMOS transistor M16 receives a start signal, which applies a voltage to the gate and causes the current of the NMOS transistor M16 to flow from the drain to the source, thereby turning on the NMOS transistor M16.
[0016] A further embodiment: the weak potential module includes a PMOS transistor M23; the gate of the PMOS transistor M23 receives the start-up signal;
[0017] The PMOS transistor M23 is connected in series with the NMOS transistor M0.
[0018] Based on the above scheme, when the gate of the PMOS transistor M23 receives the start signal, the gate is applied a voltage that is greater than the threshold voltage of the PMOS transistor M23, so that the PMOS transistor M23 is in an off-state, thereby making the output of the weak potential module low potential.
[0019] A further solution: The potential at the output terminal of the weak potential module is pulled down to a low potential by the rising edge of the CLOCK signal received by the CLOCK input module.
[0020] A further embodiment: The inverting module includes a PMOS transistor M22 and an NMOS transistor M19;
[0021] The source of the PMOS transistor M22 is connected to the power supply voltage; the source of the NMOS transistor M19 is grounded; the drain of the PMOS transistor M22 is connected to the drain of the NMOS transistor M19, serving as the output terminal of the inverting module; the gate of the PMOS transistor M22 is connected to the gate of the NMOS transistor M19, serving as the input terminal of the inverting module.
[0022] The potential at the output terminal of the inverter module is opposite to the potential at the input terminal of the inverter module.
[0023] Based on the above scheme, when the input terminal of the inverting module is at a low potential, the PMOS transistor M22 in the inverting module is in the conducting state and the NMOS transistor M19 is in the non-conducting state. Since the source of the PMOS transistor M22 is connected to the power supply voltage, the output terminal of the inverting module is the power supply voltage, i.e., a high potential.
[0024] When the input terminal of the inverting module is at a high potential, the PMOS transistor M22 in the inverting module is in a non-conducting state, and the NMOS transistor M19 is in a conducting state. Since the source of the NMOS transistor M19 is grounded, the output terminal of the inverting module is at a low potential.
[0025] Further solutions include a retention module;
[0026] The holding module includes PMOS transistor M15, PMOS transistor M14, NMOS transistor M13 and NMOS transistor M12, and includes an input terminal and an output terminal;
[0027] The drain of PMOS transistor M15 is connected to the source of PMOS transistor M14, the drain of PMOS transistor M14 is connected to the drain of NMOS transistor M13, and the source of NMOS transistor M13 is connected to the drain of NMOS transistor M12, serving as the input terminal of the hold module. The gates of PMOS transistor M15, PMOS transistor M14, NMOS transistor M13, and NMOS transistor M12 are interconnected, serving as the output terminal of the hold module. The source of PMOS transistor M15 is connected to the power supply voltage; the source of NMOS transistor M12 is grounded.
[0028] The holding module is used to maintain the high or low potential output by the output terminal of the weak potential module.
[0029] Based on the above scheme, the holding module causes the voltage of the CLOCK input module to decrease when it receives the falling edge of the CLOCK signal, while the weak potential module still outputs a low potential.
[0030] A further solution: the holding module and the inverting module are connected in parallel in opposite directions.
[0031] A further solution: the potential output from the potential output terminal is consistent with the potential output from the inverting module.
[0032] Secondly, the present invention provides a method for phase sorting in a multi-phase CLOCK signal, characterized in that it is implemented based on several sets of circuits as described in any of the first aspects for phase sorting in a multi-phase CLOCK signal; the specific implementation steps include:
[0033] S100, the signal activation module in each group of circuits simultaneously receives the activation signal; the CLOCK input module in each group of circuits receives CLOCK signals of different phases respectively;
[0034] S200. When the weak potential module in each group of circuits encounters the first rising edge of the CLOCK signal, it is pulled down from a high potential to a low potential and outputs a low potential.
[0035] S300, the input terminal of the inverting module in each group of circuits is at a low potential, and the output terminal is at a high potential;
[0036] S400, the high potential is output at the potential output terminal in each group of the circuits;
[0037] S500: The high potential output terminals of several groups of the circuits are sorted in order according to the time when the high potential appears.
[0038] The beneficial effects of this invention are as follows:
[0039] This invention discloses a circuit and method for phase sorting in multi-phase CLOCK signals. Different phase CLOCK signals received by the CLOCK input modules in several groups of circuits pass through a weak potential module and an inverting module in each group of circuits. The potential output module then outputs a high potential, and the high potentials in the several groups of circuits are sequentially sorted according to the time of their occurrence. The first high potential is identified as the first phase CLOCK signal, thus clearly displaying each phase CLOCK signal and facilitating the next step of frequency division of a specific phase CLOCK signal.
[0040] In this invention, the signal activation module is activated, the CLOCK input module receives the CLOCK signal, and when the weak potential module encounters the first rising edge of the CLOCK signal, since the rising edge of the CLOCK signal is a high potential, the output potential of the weak potential module is pulled down to a low potential. After passing through the inverting module, the output potential is pulled up.
[0041] In addition, when the weak potential module encounters the first falling edge of the CLOCK signal, the potential at the output terminal of the weak potential module is pulled high because the falling edge of the CLOCK signal has a low potential. However, before the weak potential module can restore the low potential at the output terminal to a high potential, it is pulled low to a low potential by the next rising edge of the CLOCK signal. After passing through the inverting module, the potential output at the potential output terminal is finally maintained at a high potential.
[0042] In this configuration, the signal activation module is not activated, the CLOCK input module does not receive the CLOCK signal, the input of the weak potential module is low, and since the weak potential module is connected to the power supply voltage, the output of the weak potential module is high. The input of the inverting module is high, which grounds the inverting module, i.e., the output is low, thus causing the potential output terminal to continuously output a low potential. Attached Figure Description
[0043] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0044] Figure 1 This is a schematic diagram of a circuit structure for phase sorting in a multi-phase CLOCK signal according to the present invention;
[0045] Figure 2 This is a schematic diagram illustrating the effect of a circuit used for phase sorting in a multi-phase CLOCK signal according to the present invention.
[0046] Figure 3 This is a flowchart of a method for phase sorting in a multi-phase CLOCK signal according to the present invention. Detailed Implementation
[0047] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the protection scope of the present invention.
[0048] Example 1:
[0049] like Figure 1 As shown, this embodiment provides a circuit for phase sorting in a multi-phase CLOCK signal, including:
[0050] Signal activation module, CLOCK input module, weak potential module, inverting module, and potential output terminal;
[0051] The signal activation module and the CLOCK input module are connected in series; the CLOCK input module is connected in series with the weak potential module; the output terminal of the weak potential module is connected to the input terminal of the inverting module; the output terminal of the inverting module is connected to the potential output terminal.
[0052] When the signal activation module is not activated, the output terminal of the weak potential module is at a high potential, the input terminal of the inverting module is at a high potential, and the output terminal is at a low potential, and the potential output terminal outputs a low potential.
[0053] like Figure 2 As shown, when the signal activation module is activated and the CLOCK input module receives the CLOCK signal, the output terminal of the weak potential module is at a low potential, the input terminal of the inverting module is at a low potential, and the output terminal is at a high potential, and the potential output terminal outputs a high potential.
[0054] Specifically, such as Figure 1 As shown, the circuit for phase sorting in a multi-phase CLOCK signal in this embodiment also includes PMOS transistors M1, M20, M21, M17, and M18.
[0055] The gate and source of the PMOS transistor M1 are both connected to the power supply voltage vp, and the drain of the PMOS transistor M1 is connected to the drain of the NMOS transistor M0; the PMOS transistor M1 is connected in parallel with the PMOS transistor M23; the PMOS transistor M1 is used to stabilize the circuit of this example.
[0056] The PMOS transistor M21 and the NMOS transistor M17 are connected in series to form a second inverting module; the source of the PMOS transistor M21 is connected to the power supply voltage vp; the source of the NMOS transistor M17 is grounded gd; the drain of the PMOS transistor M21 is connected to the drain of the NMOS transistor M17, serving as the output terminal net21 of the second inverting module; the gate of the PMOS transistor M21 is connected to the gate of the NMOS transistor M17, serving as the input terminal net18 of the second inverting module; the potential of the output terminal net21 of the second inverting module is opposite to the potential of the input terminal net18 of the second inverting module.
[0057] The PMOS transistor M20 and the NMOS transistor M18 are connected in series to form a third inverting module; the source of the PMOS transistor M20 is connected to the power supply voltage vp; the source of the NMOS transistor M18 is grounded gd; the drain of the PMOS transistor M20 is connected to the drain of the NMOS transistor M18, serving as the output terminal of the third inverting module; the gate of the PMOS transistor M20 is connected to the gate of the NMOS transistor M18, serving as the input terminal net21 of the third inverting module; the potential of the output terminal of the third inverting module is opposite to the potential of the input terminal net21 of the third inverting module.
[0058] One of the improved solutions is as follows:
[0059] like Figure 1 As shown, the CLOCK input module includes an NMOS transistor M0; the CLOCK input module receives the CLOCK signal through the gate of the NMOS transistor M0.
[0060] The signal activation module includes an NMOS transistor M16; the gate of the NMOS transistor M16 receives a activation signal; the signal activation module is activated by the activation signal.
[0061] The NMOS transistor M16 is connected in series with the NMOS transistor M0.
[0062] Specifically, the source of the NMOS transistor M16 is grounded to gd, and the drain of the NMOS transistor M16 is connected to the source of the NMOS transistor M0; when the CLOCK signal of different phases is divided by frequency, the start signal is input.
[0063] The weak potential module includes a PMOS transistor M23; the gate of the PMOS transistor M23 receives the start signal;
[0064] The PMOS transistor M23 is connected in series with the NMOS transistor M0.
[0065] The potential at the output terminal of the weak potential module is pulled down to a low potential by the rising edge of the CLOCK signal received by the CLOCK input module.
[0066] Specifically, the source of the PMOS transistor M23 is connected to the power supply voltage vp; the drain of the PMOS transistor M23 is connected to the drain of the NMOS transistor M0; and the output terminal of the PMOS transistor M23 is net03.
[0067] The inverting module includes a PMOS transistor M22 and an NMOS transistor M19;
[0068] The source of the PMOS transistor M22 is connected to the power supply voltage vp; the source of the NMOS transistor M19 is grounded gd; the drain of the PMOS transistor M22 is connected to the drain of the NMOS transistor M19, serving as the output terminal net18 of the inverting module; the gate of the PMOS transistor M22 is connected to the gate of the NMOS transistor M19, serving as the input terminal net03 of the inverting module.
[0069] The potential at the output terminal of the inverter module is opposite to the potential at the input terminal of the inverter module.
[0070] Specifically, the inverting module composed of PMOS transistor M22 and NMOS transistor M19 is the first inverting module;
[0071] When the input terminal of the first inverter module is at a low potential, the PMOS transistor M22 in the first inverter module is in the on state and the NMOS transistor M19 is in the off state. Since the source of the PMOS transistor M22 is connected to the power supply voltage vp, the output terminal net18 of the first inverter module is the power supply voltage vp, i.e., a high potential.
[0072] When the input terminal of the first inverting module is at a high potential, the PMOS transistor M22 in the first inverting module is in a non-conducting state, and the NMOS transistor M19 is in a conducting state. Since the source of the NMOS transistor M19 is grounded to gd, the output terminal net18 of the first inverting module is at a low potential.
[0073] This embodiment of a circuit for phase sorting in a multi-phase CLOCK signal also includes a holding module;
[0074] The holding module includes PMOS transistor M15, PMOS transistor M14, NMOS transistor M13 and NMOS transistor M12, and includes an input terminal net03 and an output terminal net18.
[0075] The drain of PMOS transistor M15 is connected to the source of PMOS transistor M14, the drain of PMOS transistor M14 is connected to the drain of NMOS transistor M13, and the source of NMOS transistor M13 is connected to the drain of NMOS transistor M12, serving as the input terminal net03 of the hold module; the gates of PMOS transistor M15, PMOS transistor M14, NMOS transistor M13, and NMOS transistor M12 are interconnected, serving as the output terminal net18 of the hold module; the source of PMOS transistor M15 is connected to the power supply voltage vp; the source of NMOS transistor M12 is grounded gd.
[0076] The holding module is used to maintain the high or low potential output by the output terminal net03 of the weak potential module.
[0077] Specifically, when the PMOS transistor M23 encounters the rising edge of the CLOCK signal, the output terminal net03 of the PMOS transistor M23 is at a low potential. After passing through the first inverting module, the second inverting module and the third inverting module in sequence, the low potential is output as a high potential by the potential output terminal.
[0078] When the PMOS transistor M23 encounters the falling edge of the multi-phase CLOCK signal, it pulls up the low potential it output when it encountered the rising edge of the CLOCK signal. At this time, the holding module holds the low potential output by the net03 terminal of the PMOS transistor M23 when it encountered the rising edge of the CLOCK signal, making the PMOS transistor M23 pull up the low potential slowly. When the PMOS transistor M23 encounters the rising edge of the CLOCK signal again, it pulls the low potential back down.
[0079] like Figure 2 As shown, the potential output terminal outputs a high potential, which then fluctuates up and down.
[0080] The holding module and the inverting module are connected in parallel in opposite directions.
[0081] Specifically, in existing PMOS and NMOS transistor series connection methods, the gates of the PMOS and NMOS transistors are generally connected together as the input terminal. However, in the series connection method of the PMOS and NMOS transistors in the hold module of this embodiment, the gates of the PMOS transistor M15, the PMOS transistor M14, the NMOS transistor M13, and the NMOS transistor M12 are interconnected to serve as the output terminal net18 of the hold module.
[0082] The potential output from the potential output terminal is consistent with the potential output from the inverting module.
[0083] This embodiment includes several sets of the circuits described above; the phase of the CLOCK signal received by the CLOCK input module in each set of circuits is different.
[0084] Example 2:
[0085] Figure 3 As shown, this invention provides a method for phase sorting in multi-phase CLOCK signals, characterized in that it is implemented based on several sets of circuits for phase sorting in multi-phase CLOCK signals as described in any of Embodiment 1; the specific implementation steps include:
[0086] S100, the signal activation module in each group of circuits simultaneously receives the activation signal; the CLOCK input module in each group of circuits receives CLOCK signals of different phases respectively;
[0087] S200. When the weak potential module in each group of circuits encounters the first rising edge of the CLOCK signal, it is pulled down from a high potential to a low potential and outputs a low potential.
[0088] S300, the input terminal of the inverting module in each group of circuits is at a low potential, and the output terminal is at a high potential;
[0089] S400, the high potential is output at the potential output terminal in each group of the circuits;
[0090] S500: The high potential output terminals of several groups of the circuits are sorted in order according to the time when the high potential appears.
[0091] The following specific examples will further illustrate this embodiment:
[0092] Assuming there are six CLOCK signals with different phases, then six sets of circuits as described in Example 1 are required.
[0093] S100, the signal start modules in the six circuits simultaneously receive the start signal; and input the six CLOCK signals of different phases into the CLOCK input modules in the six circuits respectively; the CLOCK input module in each circuit receives a CLOCK signal of a different phase respectively;
[0094] S200: When the weak potential module in each circuit encounters the first rising edge of the CLOCK signal, it is pulled down from a high potential to a low potential and outputs a low potential.
[0095] S300, the input terminal of the inverting module in each circuit group is at a low potential, and the output terminal is at a high potential;
[0096] S400, the high potential is output at the potential output terminal in each group of circuits;
[0097] S500: The high potential output terminals of the six circuits are sorted in order according to the time when the high potential appears.
[0098] Determine which is the first-phase CLOCK signal and which is the sixth-phase CLOCK signal based on the sequence. For example... Figure 2As shown, a high potential appears at 4.2ns for the first phase CLOCK signal, at 4.21ns for the second phase CLOCK signal, at 4.22ns for the third phase CLOCK signal, at 4.23ns for the fourth phase CLOCK signal, at 4.24ns for the fifth phase CLOCK signal, and at 4.25ns for the sixth phase CLOCK signal.
[0099] This invention is not limited to the above-described optional embodiments. Anyone can derive other various forms of products under the guidance of this invention. However, regardless of any changes made in their shape or structure, any technical solution that falls within the scope of the claims of this invention shall be protected by this invention.
Claims
1. A circuit for ordering phases in a multi-phase CLOCK signal, characterized by, include: Signal activation module, CLOCK input module, weak potential module, inverting module, and potential output terminal; The signal activation module, the CLOCK input module, and the weak potential module are connected in series; the output terminal of the weak potential module is connected to the input terminal of the inverting module; the output terminal of the inverting module is connected to the potential output terminal. When the signal activation module is not activated, the output terminal of the weak potential module is at a high potential, the input terminal of the inverting module is at a high potential, and the output terminal is at a low potential, and the potential output terminal outputs a low potential. When the signal activation module is activated and the CLOCK input module receives the CLOCK signal, the output terminal of the weak potential module is at a low potential, the input terminal of the inverting module is at a low potential, and the output terminal is at a high potential, and the potential output terminal outputs a high potential. The specific implementation steps for phase sorting in multi-phase CLOCK signals include: S100, the signal activation module in each group of circuits simultaneously receives the activation signal; the CLOCK input module in each group of circuits receives CLOCK signals of different phases respectively; S200. When the weak potential module in each group of circuits encounters the first rising edge of the CLOCK signal, it is pulled down from a high potential to a low potential and outputs a low potential. S300, the input terminal of the inverting module in each group of circuits is at a low potential, and the output terminal is at a high potential; S400, the high potential is output at the potential output terminal in each group of the circuits; S500: The high potential output terminals of several groups of the circuits are sorted in order according to the time when the high potential appears.
2. A circuit for ordering phases in a multi-phase CLOCK signal as recited in claim 1, wherein: The CLOCK input module includes an NMOS transistor M0; the CLOCK input module receives the CLOCK signal through the gate of the NMOS transistor M0.
3. A circuit for ordering phases in a multi-phase CLOCK signal as recited in claim 2, wherein: The signal activation module includes an NMOS transistor M16; the gate of the NMOS transistor M16 receives a activation signal; the signal activation module is activated by the activation signal. The NMOS transistor M16 is connected in series with the NMOS transistor M0.
4. A circuit for ordering phases in a multi-phase CLOCK signal as recited in claim 3, wherein: The weak potential module includes a PMOS transistor M23; the gate of the PMOS transistor M23 receives the start signal; The PMOS transistor M23 is connected in series with the NMOS transistor M0.
5. The circuit for ordering phases in a multi-phase CLOCK signal of claim 1, wherein: The potential at the output terminal of the weak potential module is pulled down to a low potential by the rising edge of the CLOCK signal received by the CLOCK input module.
6. The circuit for ordering phases in a multi-phase CLOCK signal of claim 1, wherein: The inverting module includes a PMOS transistor M22 and an NMOS transistor M19; The source of the PMOS transistor M22 is connected to the power supply voltage; the source of the NMOS transistor M19 is grounded; the drain of the PMOS transistor M22 is connected to the drain of the NMOS transistor M19, serving as the output terminal of the inverting module; the gate of the PMOS transistor M22 is connected to the gate of the NMOS transistor M19, serving as the input terminal of the inverting module. The potential at the output terminal of the inverter module is opposite to the potential at the input terminal of the inverter module.
7. The circuit for ordering phases in a multi-phase CLOCK signal of claim 1, wherein: It also includes a holding module; The holding module includes PMOS transistor M15, PMOS transistor M14, NMOS transistor M13 and NMOS transistor M12, and includes an input terminal and an output terminal; The drain of PMOS transistor M15 is connected to the source of PMOS transistor M14, the drain of PMOS transistor M14 is connected to the drain of NMOS transistor M13, and the source of NMOS transistor M13 is connected to the drain of NMOS transistor M12, serving as the input terminal of the hold module. The gates of PMOS transistor M15, PMOS transistor M14, NMOS transistor M13, and NMOS transistor M12 are interconnected, serving as the output terminal of the hold module. The source of PMOS transistor M15 is connected to the power supply voltage; the source of NMOS transistor M12 is grounded. The holding module is used to maintain the high or low potential output by the output terminal of the weak potential module.
8. A circuit for phase sorting in a multi-phase CLOCK signal according to claim 7, characterized in that: The holding module and the inverting module are connected in parallel in opposite directions.
9. The circuit for ordering phases in a multi-phase CLOCK signal of claim 1, wherein: The potential output from the potential output terminal is consistent with the potential output from the inverting module.
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