A discrete method of SOGI-FLL with resonant frequency point compensation

Abstract

The application provides a SOGI-FLL discretization method with resonance frequency point compensation, comprising the following steps: step 1: collecting power grid voltage information and outputting the information into a SOGI module; step 2: discretizing the integrator of the SOGI module by using a backward Euler discretization method, discretizing the integrator by using the backward Euler in the direct gain and the feedback gain, setting an inherent unit delay in the output loop, and averaging the integration signal and the previous value before output to obtain a discretization form; step 3: detecting the frequency information of the voltage signal by using the error function of the error signal and the output quadrature component collected in the SOGI module and outputting the frequency loop FLL structure, and discretizing the integrator of the FLL by using the backward Euler discretization method; and step 4: compensating the frequency point calculated by the frequency loop to prevent the product in the system from causing the deviation of the resonance frequency. The application of the technical scheme can realize the discretization of the SOGI-FLL module with frequency compensation.

Description

Technical Field

[0001] This invention relates to the field of power electronics and control technology, and in particular to a SOGI-FLL discretization method with resonant frequency point compensation. Background Technology

[0002] Based on a generalized second-order integrator, the SOGI-FLL frequency-locked loop can filter the input voltage of the system and generate orthogonal components to calculate the system phase. The FLL module can calculate the system frequency based on the error signals input and output of the SOGI module and the output orthogonal components, achieving frequency locking effect and frequency adaptation over a wide frequency range. It is widely used in fields such as power grid synchronization and signal extraction.

[0003] To implement a frequency-locked loop (LLL) structure based on SOGI-FLL in a digital controller, the time-domain control algorithm needs to be discretized. Currently, the main methods are global discretization, SOGI transfer function discretization, and integrator discretization. Among these, global discretization can avoid errors caused by unit delay, but it is difficult to digitize high-order transfer functions. SOGI transfer function discretization and integrator discretization both have unavoidable errors after discretization in phase and orthogonality characteristics. Summary of the Invention

[0004] In view of this, the purpose of this invention is to provide a SOGI-FLL discretization method with resonant frequency compensation. This method uses the Euler backward integration method to discretize the integrators of the SOGI and FLL modules. The integrators are discretized using the backward Euler equation in both the direct gain and feedback gain, and a unit intrinsic delay is added. The integrator signal and the previous value are output using an average value. Furthermore, the calculation frequency of the FLL is compensated, thus achieving discretization of the SOGI-FLL module with frequency compensation.

[0005] To achieve the above objectives, the present invention adopts the following technical solution: a SOGI-FLL discretization method with resonant frequency point compensation, comprising the following steps:

[0006] Step 1: Collect grid voltage information V a Output to the SOGI module;

[0007] Step 2: Discretize the integrator of the SOGI module using backward Euler discretization. Discretize the integrator using backward Euler discretization between the direct gain and feedback gain, and set an inherent z-axis in the output loop. -1 A new discretization form is obtained by averaging the product signal and its previous value before output, with a unit delay;

[0008] Step 3: Use a frequency-locked loop (FLL) structure to acquire the input and output error signals ε in the SOGI module.v Orthogonal component q of the output v The error function of FLL is used to detect the frequency information ω of the voltage signal, and the integrator is discretized in the same way by backward Euler discretization.

[0009] Step 4: Compensate for the resonant frequency ω calculated by the frequency-locked loop to prevent the frequency from changing with the system's ωT. s The product of these factors leads to a deviation in the resonant frequency.

[0010] In a preferred embodiment, step 1 involves acquiring grid voltage information V. a The output is sent to the SOGI module, whose time-domain expression is:

[0011]

[0012]

[0013] Where v is the input signal of the system, v′ and qv′ are the outputs of the SOGI module and the quadrature signal, respectively, k is a gain coefficient of SOGI, and ω is the frequency information of the system.

[0014] In a preferred embodiment, the transfer function expressions of the direct output signal v′(z) and the quadrature output signal qv′(z) with respect to the input signal v(z) in step 2 are as follows:

[0015]

[0016]

[0017]

[0018] Among them, T s This represents the system's sampling period.

[0019] In a preferred embodiment, the error signal ε of the frequency-locked loop in step 3 v The transfer function in the time domain is expressed as:

[0020]

[0021] In a preferred embodiment, in step 4, the formula for replacing ω with ω′ in the system is:

[0022]

[0023] Compared with the prior art, the present invention has the following beneficial effects:

[0024] 1. The SOGI and FLL modules adopt a new integrator discretization method, which makes up for the errors in phase and orthogonality caused by the traditional integrator discretization method. Furthermore, the discretization is based on the transfer function block diagram, which is easier to understand. It achieves good results in amplitude and phase, and there is no risk of cumulative deviation.

[0025] 2. The output frequency of the frequency-locked loop is compensated by the frequency point compensation module to prevent frequency deviation from occurring as the integral accumulates. Attached Figure Description

[0026] Figure 1 This is a flowchart of the SOGI-FLL discretization algorithm with resonant frequency point compensation in a preferred embodiment of the present invention.

[0027] Figure 2 This is a control diagram of the SOGI-FLL discretization algorithm with resonant frequency point compensation in a preferred embodiment of the present invention.

[0028] Figure 3 This is a block diagram of the transfer function of SOGI in a preferred embodiment of the present invention.

[0029] Figure 4 This is a SOGI block diagram based on the backward Euler discretization method in a preferred embodiment of the present invention.

[0030] Figure 5 This is the BODE plot of the transfer function of the frequency-locked loop (FLL) in a preferred embodiment of the present invention.

[0031] Figure 6 This is a block diagram of FLL control and resonant frequency compensation based on the backward Euler discretization method in a preferred embodiment of the present invention.

[0032] Figure 7 This is a comparison diagram of the time domain and discrete domain outputs in a preferred embodiment of the present invention during frequency abrupt changes. Detailed Implementation

[0033] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0034] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0035] It should be noted that the terminology used herein is for the purpose of describing particular implementations only and is not intended to limit the exemplary implementations according to this application; as used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise; furthermore, it should be understood that when the terms “comprising” and / or “including” are used in this specification, they indicate the presence of features, steps, operations, devices, components and / or combinations thereof.

[0036] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and do not limit the scope of the invention.

[0037] like Figure 1-7 As shown, the SOGI-FLL discretization method with resonant frequency point compensation according to the present invention has the following control graph. Figure 2 As shown, it includes the following steps:

[0038] Step 1: Collect grid voltage information and input it into the SOGI module, such as... Figure 3 As shown, the time-domain expression of the SOGI module is:

[0039]

[0040]

[0041] Where v is the input signal of the system, v′ and qv′ are the outputs of the SOGI module and the quadrature signal, respectively, k is the gain coefficient of the SOGI transfer function, and ω is the frequency of the system.

[0042] Step 2: Discretize the integrator of the SOGI module using the backward Euler discretization method, such as... Figure 4 As shown, the direct gain and feedback gain are discretized using a backward Euler pair integrator, allowing the output information to be input into the DSP, and an inherent z-axis is set in the output loop. -1 A new discretization form is obtained by averaging the product signal and its preceding value before output, with a unit delay. Its transfer function expression in the discrete domain is as follows:

[0043]

[0044]

[0045]

[0046] Where T1(z) and T2(z) are the discrete-domain transfer functions of the outputs v(z) and qv′(z) with respect to the input v(z).

[0047] By applying its magnitude gain, phase gain, and orthogonality characteristics in the discrete domain, we can obtain:

[0048]

[0049] It can be seen that the discretization method based on the backward Euler integrator has good results in terms of amplitude, phase, and orthogonality.

[0050] Step 3: Use a frequency-locked loop (FLL) structure to process the input and output error signals ε acquired by the SOGI module. v Orthogonal component q of the output v The error function is used to detect the frequency information ω of the voltage signal, such as... Figure 5 As shown, the FLL integrator is discretized using a backward Euler discretization method; in step 3, the frequency-locked loop structure acquires the input and output error signals ε. v Orthogonal component q of the output v The error function ε' is used to detect the frequency information of the voltage signal. The error signal ε of the frequency-locked loop... v The transfer function in the time domain can be expressed as:

[0051]

[0052] Step 4: Compensate for the resonant frequency point calculated by the frequency-locked loop. The traditional discretization method is cos(ωT) s Substituting this into the denominator using a second-order Taylor series approximation will lead to a deviation in the resonant frequency as the product is repeatedly performed. Therefore, replacing ω with ω′ in the system gives the following formula:

[0053]

[0054] ω′ is the compensated grid voltage frequency.

[0055] The output comparison of SOGI-FLL in the time domain and discrete domain under the condition of frequency abrupt change is shown in the figure below. Figure 7 As shown, the x-axis represents time, and the y-axis represents the difference between the output response in the time domain and the discrete domain for the same grid voltage input signal. The system experiences a sudden change in grid frequency to 60Hz at 0.3s and a sudden decrease to the power frequency of 50Hz at 0.5s. The ratio of the direct output signal to the input signal in both the time and discrete domains is shown below. The ratio of quadrature output signal to input signal The frequency ratio ω′ is shown in the figure. When the frequency changes abruptly, ω′ has a small fluctuation, which can be stabilized quickly. In steady state, the error between the time domain and the discrete domain is 0, and the frequency locking effect in the discrete domain is the same as that in the continuous domain.

[0056] The control block diagram of the SOGI-FLL discretization algorithm with resonant frequency compensation applied in this invention is as follows: Figure 1 As shown, based on the SOGI-FLL frequency adaptive frequency locking loop, the integrators of the SOGI module and the FLL module are discretized by backward Euler, and a delay compensation module is added at the output end; and frequency compensation is performed on the output frequency of the frequency locking loop to prevent cumulative deviation.

[0057] Figure 4 This paper presents a new method for discretizing integrators, and... Figure 2 A comparison reveals that in the direct gain and feedback gain of the SOGI module, the integrator is discretized using a backward Euler, introducing an inherent delay into the system. Figure 2 , Figure 3 The comparison clearly demonstrates its discretization method based on integrators.

[0058] Figure 5 The Bode plot of the transfer function of the frequency-locked loop (FLL) shows that below the rated frequency of 50Hz, the error signal ε v With orthogonal component signal q v In phase, error signal ε after 50Hz v With orthogonal component signal q v The frequency error signal is out of phase. And when the frequency is less than 50Hz below the rated frequency, the average frequency error signal value is... The average value of the frequency error signal is always greater than 0 when the frequency is greater than the rated frequency by 50Hz. The output frequency is always less than 0. Therefore, a negative gain integral controller was used in the frequency-locked loop (FLL) to adjust the output frequency to be close to the rated frequency of 50Hz.

[0059] Figure 6 For the frequency adaptive FLL module, it is also discretized by backward Euler, and the calculated output frequency is compensated by frequency point to prevent frequency accumulation and deviation.

[0060] This invention, based on the traditional integrator discretization method, discretizes the integrator through backward Euler extraction in the direct gain and feedback gain according to a block diagram. This is easy to understand and eliminates the risk of accumulated bias. Discretizing the integrator through backward Euler extraction in the direct gain and feedback gain, and setting an inherent Z⁻¹ unit delay in the output circuit, and averaging the product signal and its preceding value before the output to obtain a new discretization form, and adding compensation at the resonant frequency point, achieves good results in amplitude, phase, and frequency locking, without the risk of accumulated bias.

[0061] The above embodiments are descriptions of specific implementations of the present invention, and not limitations thereof. Those skilled in the art can make various modifications and changes without departing from the spirit and scope of the present invention to obtain corresponding equivalent technical solutions. Therefore, all equivalent technical solutions should be included in the patent protection scope of the present invention.

Claims

1. A SOGI-FLL discretization method with resonant frequency compensation, characterized in that, Includes the following steps: Step 1: Collect power grid voltage information Output to the SOGI module; Step 2: Discretize the integrator of the SOGI module using backward Euler discretization. Discretize the integrator using backward Euler discretization between the direct gain and feedback gain, and set an inherent value in the output loop. A new discretization form is obtained by averaging the product signal and its previous value before output, with a unit delay; Step 3: Acquire the input and output error signals of the SOGI module using a frequency-locked loop (FLL) structure. Orthogonal components of the output The error function is used to detect the frequency information of the voltage signal. And the integrator is discretized using the same backward Euler discretization method as FLL; Step 4: Calculate the frequency points for the frequency-locked loop. Perform resonant frequency compensation to prevent the system from... The product of these factors leads to a deviation in the resonant frequency; In step 1, the grid voltage information is collected. The output is sent to the SOGI module, whose time-domain expression is: , ,in, The input signal of the system, , These represent the outputs of the SOGI module and the quadrature signal, respectively, where k is a gain coefficient of the SOGI module. For the system's frequency information; In step 2, the signal is directly output. and quadrature output signals For input signal The transfer function expression is: , , ,in, The sampling period of the system; In step 4, the system will... Replace with The formula is: 。 2. The SOGI-FLL discretization method with resonant frequency point compensation according to claim 1, characterized in that... The error signal of the frequency locking loop in step 3 The transfer function in the time domain is expressed as: 。

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