Signal receiving device and programmable gain amplifier with mode switching mechanism

Abstract

A programmable gain amplifier with a mode switching mechanism. The operational amplifier includes a first input terminal, a second input terminal and an output terminal, wherein the second input terminal is coupled to the ground terminal, and the output terminal generates an output signal. A variable resistor and a first switch are electrically connected in series between the first terminal and the second terminal, wherein the second terminal is coupled to the first input terminal. A first variable capacitor and a second switch are connected in series between the first terminal and the second terminal. A second variable capacitor and a third switch are connected in series between the first terminal and the ground terminal. A low-pass resistor and a low-pass capacitor are connected in parallel between the first input terminal and the output terminal. An input resistor is coupled between a signal input terminal and a first terminal, and receives an input signal from the signal input terminal. The first switch, the second switch and the third switch are switched according to a set of mode switching signals to form a path or a disconnection.

Description

Technical Field

[0001] The present invention relates to a signal amplification technology, and in particular to a signal receiving device and a programmable gain amplifier with a mode switching mechanism. Background Art

[0002] When a signal is transmitted through an intermediate medium in a communication system, signal degradation may occur due to insertion loss or return loss. To solve the degradation, a signal receiving device needs to be provided with a signal amplifier to compensate.

[0003] However, in the past, signal receiving devices often need to be equipped with multiple amplifiers to achieve different levels of gain amplification and signal processing in different bandwidth ranges in response to network communications with different connection speeds and bandwidths. Such a configuration will significantly increase the cost of hardware circuits. Summary of the invention

[0004] In view of the problems in the prior art, one of the objectives of the present invention is to provide a signal receiving device and a programmable gain amplifier with a mode switching mechanism thereof to improve the prior art.

[0005] The present invention includes a programmable gain amplifier with a mode switching mechanism, including: an operational amplifier, a variable resistor, a first switch, a first variable capacitor, a second switch, a second variable capacitor, a third switch, a low-pass resistor, a low-pass capacitor and an input resistor. The operational amplifier includes a first input terminal, a second input terminal and an output terminal, wherein the second input terminal is electrically coupled to the ground terminal, and the output terminal is configured to generate an output signal. The variable resistor and the first switch are electrically connected in series between the first terminal and the second terminal, wherein the second terminal is electrically coupled to the first input terminal. The first variable capacitor and the second switch are electrically connected in series between the first terminal and the second terminal. The second variable capacitor and the third switch are electrically connected in series between the first terminal and the ground terminal. The low-pass resistor and the low-pass capacitor are electrically connected in parallel between the first input terminal and the output terminal. The input resistor is electrically coupled between the signal input terminal and the first terminal, and is configured to receive an input signal from the signal input terminal. The first switch, the second switch and the third switch are configured to switch according to a set of mode switching signals to form a path or a disconnection.

[0006] The present invention also includes a signal receiving device, including: a programmable gain amplifier, an analog-to-digital conversion circuit and a digital signal processing circuit. The programmable gain amplifier includes: an operational amplifier, a variable resistor, a first switch, a first variable capacitor, a second switch, a second variable capacitor, a third switch, a low-pass resistor, a low-pass capacitor and an input resistor. The operational amplifier includes a first input terminal, a second input terminal and an output terminal, wherein the second input terminal is electrically coupled to the ground terminal, and the output terminal is configured to generate an output signal. The variable resistor and the first switch are electrically connected in series between the first terminal and the second terminal, wherein the second terminal is electrically coupled to the first input terminal; the first variable capacitor and the second switch are electrically connected in series between the first terminal and the second terminal. The second variable capacitor and the third switch are electrically connected in series between the first terminal and the ground terminal. The low-pass resistor and the low-pass capacitor are electrically connected in parallel between the first input terminal and the output terminal. The input resistor is electrically coupled between the signal input terminal and the first terminal, and is configured to receive an input signal from the signal input terminal. The analog-to-digital conversion circuit is configured to perform analog-to-digital conversion on the output signal. The digital signal processing circuit is electrically coupled to the output end through the analog-to-digital conversion circuit, and is configured to receive the output signal after analog-to-digital conversion. The digital signal processing circuit is also configured to generate a set of mode switching signals, so that the first switch, the second switch, and the third switch are configured to switch according to the set of mode switching signals to form a circuit or a disconnection.

[0007] The features, implementation and effects of the present invention are described in detail below with reference to the drawings as preferred embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A block diagram of a communication system according to an embodiment of the present invention is shown respectively;

[0009] Figure 2 A more detailed block diagram of a programmable gain amplifier according to an embodiment of the present invention is shown;

[0010] Figure 3A A block diagram showing a signal receiving device in a bandpass filtering mode according to an embodiment of the present invention;

[0011] Figure 3B A frequency response diagram showing a signal receiving device in a bandpass filtering mode according to an embodiment of the present invention;

[0012] Figure 4A A block diagram showing a signal receiving device in a low-pass filtering mode according to an embodiment of the present invention;

[0013] Figure 4B A frequency response diagram showing a signal receiving device in a low-pass filtering mode according to an embodiment of the present invention;

[0014] Figure 5A A block diagram showing a signal receiving device in a continuous time linear equalizer mode according to an embodiment of the present invention; and

[0015] Figure 5B FIG. 4 is a diagram showing a frequency response of a signal receiving device in a continuous time linear equalizer mode according to an embodiment of the present invention. DETAILED DESCRIPTION

[0016] One of the purposes of the present invention is to provide a signal receiving device and a programmable gain amplifier with a mode switching mechanism, which can switch between different modes with a single circuit according to network communications with different connection speeds and bandwidths, thereby achieving different degrees of gain amplification and different ranges of bandwidth processing, thereby significantly reducing the cost of hardware circuits.

[0017] Please refer to Figure 1 . Figure 1 A block diagram of a communication system 100 according to an embodiment of the present invention is shown. The communication system 100 includes a signal receiving device 110 , a signal transmitting device 120 , and a wiring 130 .

[0018] The signal receiving device 110 and the signal transmitting device 120 are electrically coupled to each other and communicate with each other via the wiring 130 , so that the signal receiving device 110 receives the input signal VIN generated by the signal transmitting device 120 through the wiring 130 .

[0019] The signal receiving device 110 includes a programmable gain amplifier 140 , an analog-to-digital conversion circuit 150 , and a digital signal processing circuit 160 .

[0020] The programmable gain amplifier 140 is configured to amplify and filter the input signal VIN and generate an output signal VOUT. The analog-to-digital conversion circuit 150 performs analog-to-digital conversion on the output signal VOUT, so that the digital signal processing circuit 160 receives the analog-to-digital converted output signal VOUTD.

[0021] Due to the different connection speeds and bandwidths of the network, the digital signal processing circuit 160 is configured to generate a set of mode switching signals MS1~MS3 for different operating modes, control the configuration of the programmable gain amplifier 140, and perform different gain amplification and different frequency band filtering on the input signal VIN.

[0022] In one embodiment, the mode switching signals MS1-MS3 are generated by the digital signal processing circuit 160 according to a handshake procedure with the signal transmitting device 120. The digital signal processing circuit 160 can determine the communication specification between the signal receiving device 110 and the signal transmitting device 120 according to the handshake procedure, and further determine the gain amplification and filtering required for the input signal VIN.

[0023] The structure of the programmable gain amplifier 140 will be described in detail below.

[0024] Please refer to Figure 2 . Figure 2 FIG. 1 is a block diagram showing a more detailed block diagram of a programmable gain amplifier 140 according to an embodiment of the present invention. The programmable gain amplifier 140 includes an operational amplifier OP, a variable resistor RA, a first switch SW1, a first variable capacitor CA1, a second switch SW2, a second variable capacitor CA2, a third switch SW3, a low-pass resistor RB, a low-pass capacitor CB, and an input resistor RIN.

[0025] The operational amplifier OP includes a first input terminal, a second input terminal, and an output terminal. Figure 2 In the embodiment, the first input terminal is an inverting input terminal and is marked with a symbol '-'. The second input terminal is a non-inverting input terminal and is marked with a symbol '+'. The output terminal is marked with a symbol 'o'. The second input terminal is electrically coupled to the ground terminal GND, and the output terminal is configured to generate an output signal VOUT.

[0026] The variable resistor RA and the first switch SW1 are electrically connected in series between the first terminal N1 and the second terminal N2 , wherein the second terminal N2 is electrically coupled to the first input terminal.

[0027] The first variable capacitor CA1 and the second switch SW2 are electrically connected in series between the first terminal N1 and the second terminal N2. The second variable capacitor CA2 and the third switch SW3 are electrically connected in series between the first terminal N1 and the ground terminal GND.

[0028] The low-pass resistor RB and the low-pass capacitor CB are electrically connected in parallel between the first input terminal and the output terminal.

[0029] The input resistor RIN is electrically coupled between the signal input terminal SIN and the first terminal N1 , and is configured to receive an input signal VIN from the signal input terminal SIN.

[0030] like Figure 2As shown, the mode switching signals MS1-MS3 are configured to control the first switch SW1, the second switch SW2 and the third switch SW3. The mode switching signal MS1 corresponds to controlling the first switch SW1, the mode switching signal MS2 corresponds to controlling the second switch SW2, and the mode switching signal MS3 corresponds to controlling the third switch SW3. The first switch SW1, the second switch SW2 and the third switch SW3 are configured to switch according to the mode switching signals MS1-MS3 to form a path or a disconnection.

[0031] Therefore, the gain and filter band relationship between the output signal VOUT and the input signal VIN are determined by the connection relationship and variable impedance values ​​of the variable resistor RA, the first variable capacitor CA1 and the second variable capacitor CA2 according to the mode switching signals MS1 - MS3 .

[0032] The following will describe the configuration of the programmable gain amplifier 140 in different modes.

[0033] Please also refer to Figure 3A and Figure 3B . Figure 3A A block diagram of the programmable gain amplifier 140 in a bandpass filtering mode is shown in one embodiment of the present invention. Figure 3B The frequency response diagram of the programmable gain amplifier 140 in the bandpass filtering mode in one embodiment of the present invention is shown. Figure 3B The horizontal axis represents the signal frequency (in Hertz), and the vertical axis represents the signal strength (in dB).

[0034] In one embodiment, the bandpass filter mode corresponds to the input signal VIN transmitted according to the frequency bands of 5 GHz and 2.5 GHz.

[0035] like Figure 3A As shown, in the bandpass filtering mode, the mode switching signals MS1-MS3 cause the first switch SW1 to be disconnected and the second switch SW2 and the third switch SW3 to be connected. Figure 3A Indicated by dotted line.

[0036] In this case, the first variable capacitor CA1 and the second variable capacitor CA2 form a high-pass filter, the low-pass resistor RB and the low-pass capacitor CB form a low-pass filter, and together form a band-pass filter. The variable impedance values ​​of the first variable capacitor CA1 and the second variable capacitor CA2 can determine the amount of current transmitted from the input signal VIN to the operational amplifier OP, thereby determining the gain.

[0037] like Figure 3B As shown in the figure, different lines correspond to the signal at different gains. Figure 3B In the signal at 10 6 Hz to 10 10 All frequency bands in Hertz can pass.

[0038] Please also refer to Figure 4A and Figure 4B . Figure 4A A block diagram of the programmable gain amplifier 140 in a low pass filter mode is shown in one embodiment of the present invention. Figure 4B The frequency response diagram of the programmable gain amplifier 140 in the low-pass filter mode in one embodiment of the present invention is shown. Figure 4B The horizontal axis represents the signal frequency (in Hertz), and the vertical axis represents the signal strength (in dB).

[0039] In one embodiment, the low-pass filter mode corresponds to the input signal VIN transmitted according to a frequency band below 1 GHz (eg, but not limited to 1 GHz, 100 MHz, 10 MHz).

[0040] In the low-pass filtering mode, the mode switching signals MS1-MS3 enable the first switch SW1 to form a circuit and the second switch SW2 and the third switch SW3 to form an open circuit. Figure 4A Indicated by dotted line.

[0041] In this case, the low-pass resistor RB and the low-pass capacitor CB form a low-pass filter. The gain of the programmable gain amplifier 140 is proportional to the ratio of the impedance value of the low-pass resistor RB to the sum of the impedance values ​​of the input resistor RIN and the variable resistor RA (expressed as RB / (RIN+RA)). The variable impedance value of the variable resistor RA determines the gain.

[0042] like Figure 4B As shown in the figure, different lines correspond to the signal at different gains. Figure 4B In the signal at 10 8 The frequency band below Hz is passable, but at 10 8 Frequency bands above Hz are attenuated.

[0043] Please also refer to Figure 5A and Figure 5B . Figure 5A A block diagram of a programmable gain amplifier 140 in a continuous time linear equalizer (CTLE) mode according to an embodiment of the present invention is shown. Figure 5BThe frequency response diagram of the programmable gain amplifier 140 in the continuous time linear equalizer mode is shown in one embodiment of the present invention. Figure 5B The horizontal axis represents the signal frequency (in Hertz), and the vertical axis represents the signal strength (in dB).

[0044] In one embodiment, the continuous time linear equalizer mode corresponds to an input signal VIN transmitted in a frequency band above 1 GHz and passing through a trace 130 having a length greater than a default value.

[0045] In the continuous time linear equalizer mode, the mode switching signals MS1-MS3 enable the first switch SW1 and the second switch SW2 to form a path, and the third switch SW3 to form an open circuit. Figure 5A Indicated by dotted line.

[0046] In this case, the low-pass resistor RB and the low-pass capacitor CB form a low-pass filter, and the first variable capacitor CA1 is connected in parallel with the variable resistor RA. Since the adjustable impedance value of the first variable capacitor CA1 is the inverse of the product of the frequency and the capacitance value, the higher the frequency, the smaller the adjustable impedance value, and thus the smaller the impedance value after being connected in parallel with the low-pass resistor RB. Therefore, the impedance value Z of the first variable capacitor CA1 after being connected in parallel with the low-pass resistor RB and then in series with the input resistor RIN is also smaller.

[0047] The gain of the programmable gain amplifier 140 is proportional to the ratio (expressed as RB / Z) between the impedance value of the low-pass resistor RB and the impedance value Z. The gain is determined by the variable impedance values ​​of the first variable capacitor CA1 and the variable resistor RA.

[0048] like Figure 5B As shown in the figure, different lines correspond to the signal at different gains. Figure 5B In the signal at 10 7 The frequency band below Hz can be passed, at 10 7 Hz to 10 8 The frequency band between Hz has a boost effect, but at 10 8 Frequency bands above Hz are attenuated.

[0049] In some technologies, when facing network communications with different connection speeds and bandwidths, the signal receiving device needs to be equipped with amplifiers with different characteristics to perform different degrees of gain amplification and different ranges of bandwidth processing on the signal. In this way, the cost of the hardware circuit will be greatly increased.

[0050] In contrast, the programmable gain amplifier with a mode switching mechanism of the present invention can switch between different modes with a single circuit according to network communications with different connection speeds and bandwidths, thereby achieving different degrees of gain amplification and different ranges of bandwidth processing, greatly reducing the cost of hardware circuits.

[0051] It should be noted that the above-mentioned implementations are merely examples, and those skilled in the art may make modifications to other embodiments without departing from the spirit of the present invention.

[0052] In summary, the signal receiving device and the programmable gain amplifier with a mode switching mechanism in the present invention can switch between different modes with a single circuit according to network communications with different connection speeds and bandwidths, thereby achieving different degrees of gain amplification and different ranges of bandwidth processing, greatly reducing the cost of hardware circuits.

[0053] Although the embodiments of the present case are described above, these embodiments are not intended to limit the present case. Ordinary technicians with common knowledge in the technical field may make changes to the technical features of the present case based on the explicit or implicit content of the present case. All these changes may fall within the scope of patent protection sought in the present case. In other words, the scope of patent protection in the present case shall be based on the scope of the patent application defined in this specification.

[0054] Description of reference numerals:

[0055] 100: Communication Systems

[0056] 110: Signal receiving device

[0057] 120: Signal transmission device

[0058] 130: Routing

[0059] 140: Programmable Gain Amplifier

[0060] 150: Analog to digital conversion circuit

[0061] 160: Digital signal processing circuit

[0062] CA1: First variable capacitor

[0063] CA2: Second variable capacitor

[0064] CB: Low pass capacitor

[0065] GND: Ground terminal

[0066] MS1~MS3: Mode switching signal

[0067] N1: First end

[0068] N2: Second end

[0069] OP: Operational Amplifier

[0070] RA: variable resistor

[0071] RB: Low pass resistor

[0072] RIN: Input resistor

[0073] SW1: First switch

[0074] SW2: Second switch

[0075] SW3: The third switch

[0076] VIN: Input signal

[0077] VOUT, VOUTD: output signal

Claims

1. A programmable gain amplifier with a mode switching mechanism, comprising: An operational amplifier, comprising a first input terminal, a second input terminal and an output terminal, wherein the second input terminal is electrically coupled to a ground terminal, and the output terminal is configured to generate an output signal; A variable resistor and a first switch are electrically connected in series between a first terminal and a second terminal, wherein the second terminal is electrically coupled to the first input terminal; A first variable capacitor and a second switch are electrically connected in series between the first end and the second end; A second variable capacitor and a third switch are electrically connected in series between the first terminal and the ground terminal; A low-pass resistor and a low-pass capacitor are electrically connected in parallel between the first input terminal and the output terminal; and An input resistor, electrically coupled between the signal input terminal and the first terminal, and configured to receive an input signal from the signal input terminal; The first switch, the second switch and the third switch are configured to switch according to a set of mode switching signals to form a connection or an open circuit.

2. The programmable gain amplifier according to claim 1, wherein the gain and filter band relationship between the output signal and the input signal are determined by the connection relationship and variable impedance value of the variable resistor, the first variable capacitor and the second variable capacitor according to the group of mode switching signals.

3. The programmable gain amplifier according to claim 1, wherein in the bandpass filtering mode, the group of mode switching signals causes the first switch to be disconnected and causes the second switch and the third switch to be connected; In the low-pass filtering mode, the group of mode switching signals enables the first switch to form a circuit, and enables the second switch and the third switch to form an open circuit; as well as In the continuous time linear equalizer mode, the set of mode switching signals enables the first switch and the second switch to form a connection, and enables the third switch to form an open circuit.

4. The programmable gain amplifier of claim 3, wherein the bandpass filter mode corresponds to the input signal transmitted according to a frequency band of 5 GHz and 2.5 GHz, the low-pass filter mode corresponds to the input signal transmitted according to a frequency band below 1 GHz, and the continuous-time linear equalizer mode corresponds to the input signal transmitted according to a frequency band above 1 GHz and passing through a routing length greater than a default value.

5. The programmable gain amplifier according to claim 1, wherein the input signal is generated by a signal transmission device, the output end is also electrically coupled to a digital signal processing circuit through an analog-to-digital conversion circuit, and the group of mode switching signals is generated by the digital signal processing circuit according to a handshake procedure performed with the signal transmission device.

6. A signal receiving device, comprising: Programmable Gain Amplifier, including: An operational amplifier, comprising a first input terminal, a second input terminal and an output terminal, wherein the second input terminal is electrically coupled to a ground terminal, and the output terminal is configured to generate an output signal; A variable resistor and a first switch are electrically connected in series between a first terminal and a second terminal, wherein the second terminal is electrically coupled to the first input terminal; A first variable capacitor and a second switch are electrically connected in series between the first end and the second end; A second variable capacitor and a third switch are electrically connected in series between the first terminal and the ground terminal; A low-pass resistor and a low-pass capacitor are electrically connected in parallel between the first input terminal and the output terminal; and An input resistor, electrically coupled between the signal input terminal and the first terminal, and configured to receive an input signal from the signal input terminal; an analog-to-digital conversion circuit configured to perform analog-to-digital conversion on the output signal; and A digital signal processing circuit is electrically coupled to the output terminal through the analog-to-digital conversion circuit and is configured to receive the output signal after analog-to-digital conversion; The digital signal processing circuit is further configured to generate a set of mode switching signals, so that the first switch, the second switch and the third switch are configured to switch according to the set of mode switching signals to form a circuit or an open circuit.

7. The signal receiving device according to claim 6, wherein the gain and filtering band relationship between the output signal and the input signal are determined by the connection relationship and variable impedance value of the variable resistor, the first variable capacitor and the second variable capacitor respectively according to the group of mode switching signals.

8. The signal receiving device according to claim 6, wherein in the bandpass filtering mode, the group of mode switching signals causes the first switch to be disconnected and causes the second switch and the third switch to be connected; In the low-pass filtering mode, the group of mode switching signals enables the first switch to form a circuit, and enables the second switch and the third switch to form an open circuit; as well as In the continuous time linear equalizer mode, the set of mode switching signals enables the first switch and the second switch to form a connection, and enables the third switch to form an open circuit.

9. The signal receiving device according to claim 8, wherein the bandpass filtering mode corresponds to the input signal transmitted according to the frequency bands of 5 GHz and 2.5 GHz, the low-pass filtering mode corresponds to the input signal transmitted according to the frequency band below 1 GHz, and the continuous-time linear equalizer mode corresponds to the input signal transmitted according to the frequency band above 1 GHz and the wiring length passed is greater than a default value.

10. The signal receiving device as claimed in claim 6, wherein the input signal is generated by a signal transmitting device, and the set of mode switching signals is generated by the digital signal processing circuit according to a handshake procedure performed with the signal transmitting device.

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