Semiconductor structure comprising an electrically conductive bonding interface and associated production method

Abstract

The invention relates to a semiconductor structure (100) comprising a useful layer (10) made of a single-crystal semiconductor material and extending along a main plane (x, y), a support substrate (30) made of a semiconductor material and extending parallel to the main plane (x, y), and an interface region (20) between the useful layer (10) and the support substrate (30), the structure (100) being characterized in that the interface region (20) comprises nodules (21): - which are electrically conductive, they comprising a metallic material forming an ohmic contact with the useful layer (10) and the support substrate (30); - which have a thickness along an axis (z) perpendicular to the main plane (x, y) less than or equal to 30 nm; - which are isolated or contiguous, the isolated nodules (21) being separated from each other by direct contact areas (22) of the useful layer (10) and of the support substrate (30). The invention also relates to a method for manufacturing this structure (100).

Description

Technical Field

[0001] This invention relates to the field of semiconductor materials for microelectronic components. Specifically, this invention relates to a structure comprising a single-crystal semiconductor layer and a semiconductor carrier substrate bonded at a conductive bonding interface. This invention also relates to a process for manufacturing such a structure. Background Technology

[0002] A common approach is to form semiconductor structures by transferring a thin, high-crystal-quality semiconductor working layer to a semiconductor carrier substrate with lower crystal quality. A well-known thin-layer transfer solution is Smart Cut. TM The process is based on implanting light ions and bonding directly at the bonding interface. In addition to the economic advantages associated with high-quality materials for thinning the working layer, semiconductor structures can also provide advantageous properties, such as those related to the thermal or electrical conductivity or mechanical compatibility of the carrier substrate.

[0003] For example, in the field of power electronics, it is also advantageous to establish electrical conduction between the active layer and the carrier substrate to form vertical components. For instance, in structures comprising an active layer made of single-crystal silicon carbide and a carrier substrate made of low-quality silicon carbide (whether single-crystal or polycrystalline), the bonding interface must exhibit the lowest possible resistivity, preferably below 1 mol·cm⁻¹. 2 or even below 0.1 mohm·cm 2 .

[0004] Some existing solutions propose performing direct semiconductor-to-semiconductor bonding between the working layer and the carrier substrate to establish vertical electrical conduction. However, achieving a high-quality interface via this bonding is difficult.

[0005] F. Mu et al. (ECS Transactions, 86(5)3-21, 2018) achieved direct bonding (SAB: "surface-activated bonding") by activating the surfaces to be assembled after argon bombardment: this pre-bonding treatment generates a very high density of side bonds, which promotes the formation of covalent bonds at the bonding interface, thus resulting in a high bonding energy. However, this method has the disadvantage of generating an amorphous layer at the bonding surface, which negatively affects the vertical electrical conduction between the thin layer and the carrier substrate. To overcome this problem, heavy doping of the surface has been proposed, particularly in the literature EP3168862.

[0006] Other solutions in the prior art propose forming conductive bonds based on a metal layer deposited on the surfaces to be bonded.

[0007] For example, Lettertre's publication ("Silicon carbide and related materials," Materials Science Forum, Vol. 389-393, April 2002) or document US7208392 describes the deposition of tungsten and silicon layers to form a conductive intermediate layer based on tungsten silicide (WSi2). One drawback of this method may stem from the formation of voids in the intermediate layer due to the shrinkage of the silicide relative to the initially deposited material: in particular, this can affect the quality of the surface semiconductor layer and the overall semiconductor structure, rendering it unusable for the target application. Additionally, it is difficult to reduce the resistivity of the bonding interface to the level required for some applications that demand very good vertical electrical conduction.

[0008] The subject of this invention

[0009] This invention relates to alternative solutions to existing technologies and aims to overcome, in whole or in part, the aforementioned disadvantages. In particular, it relates to a structure comprising a single-crystal semiconductor working layer and a semiconductor carrier substrate bonded at a conductive bonding interface. The invention also relates to a process for producing such a structure.

[0010] Brief Description of the Invention

[0011] This invention relates to a semiconductor structure, comprising: a working layer made of a single-crystal semiconductor material extending in a main plane; a carrier substrate made of a semiconductor material; and an interface region between the working layer and the carrier substrate, extending parallel to the main plane. The structure is characterized in that the interface region includes nodules.

[0012] - It is conductive, including metallic materials that form ohmic contacts with the working layer and the carrier substrate.

[0013] -It has a thickness of less than or equal to 30 nm along an axis perpendicular to the main plane.

[0014] - It can be discontinuous or joined, with discontinuous nodules separated from each other by the direct contact area between the working layer and the carrier substrate.

[0015] Other advantageous and non-limiting features according to the invention (alone or in any technically feasible combination):

[0016] The working layer and the carrier substrate are formed of the same semiconductor material and have the same doping type;

[0017] The semiconductor material for the working layer is selected from silicon carbide, silicon, gallium nitride, and germanium;

[0018] • The semiconductor material of the carrier substrate is selected from silicon carbide, silicon, gallium nitride and germanium, and has a single crystal, polycrystalline or amorphous structure;

[0019] • The metallic material of the nodules is selected from tungsten, titanium, nickel, aluminum, molybdenum, niobium, tantalum, cobalt, and copper;

[0020] • The coverage of nodules in the midplane of the interface region ranges from 1% to 70%;

[0021] • Nodules with a size less than 0.1 mohm·cm 2 Preferably, it is less than or equal to 0.01 mohm·cm 2 The resistivity is to obtain a value below 0.1 mohm·cm. 2 Preferably, it is less than or equal to 0.01 mohm·cm 2 The resistivity of the interface region;

[0022] The nodules have a thickness of less than or equal to 20 nm, or even less than or equal to 10 nm.

[0023] The present invention also relates to a power component manufactured on and / or in the working layer of the above-described semiconductor structure, the power component including at least one electrical contact on and / or in a carrier substrate at a horizontal position on the back side of the semiconductor substrate.

[0024] Finally, the present invention relates to a process for producing the above-described structure, comprising the following steps:

[0025] a) Provide a working layer made of single-crystal semiconductor material with free surfaces to be bonded.

[0026] b) Provide a carrier substrate made of semiconductor material with free surfaces to be bonded.

[0027] c) Deposit a film made of metallic material on the free surface of the working layer to be bonded and / or on the free surface of the carrier substrate to be bonded under a non-oxidizing controlled atmosphere. The film is capable of forming ohmic contacts with the working layer and the carrier substrate and has a thickness of less than or equal to 20 nm.

[0028] d) Forming an intermediate structure, including operations of directly bonding the free surfaces to be bonded to the working layer and the carrier substrate under a non-oxidizing controlled atmosphere, wherein the intermediate structure includes an encapsulation film derived from one or more films deposited in step c).

[0029] e) Anneal the intermediate structure at a temperature above or equal to the critical temperature so that the encapsulation film is segmented into conductive nodes that form ohmic contacts with the working layer and the carrier substrate, and an interface region is formed.

[0030] Other advantageous and non-limiting features according to the invention (alone or in any technically feasible combination):

[0031] The working layer and the carrier substrate are formed of the same semiconductor material and have the same doping type;

[0032] Step a) includes the operation of injecting a light material into a donor substrate to form a buried weakening plane that, together with the front side of the donor substrate, defines the working layer.

[0033] Step a) includes forming a donor substrate by epitaxially growing a donor layer on an initial substrate, and subsequently performing implantation into the donor layer;

[0034] Step d) includes separating at the level of the buried weakened plane after directly bonding to form a bonding assembly including a donor substrate and a carrier substrate, so as to form an intermediate structure including a working layer, an encapsulation film and a carrier substrate on the one hand, and the remainder of the donor substrate on the other hand.

[0035] • The manufacturing process includes a step c') of deoxidizing the free surfaces of the working layer to be bonded and / or the free surfaces of the carrier substrate to be bonded before the deposition step c).

[0036] • The deposition in step c) and the direct bonding in step d) are performed integrally in the same device;

[0037] • The thickness of the film deposited in step c) is less than or equal to 10 nm, or even less than or equal to 5 nm, or even less than or equal to 2 nm;

[0038] Steps c) and d) are performed in a vacuum;

[0039] • Deposition step c) is performed using sputtering technology at ambient temperature;

[0040] The semiconductor material for the working layer is selected from silicon carbide, silicon, gallium nitride, and germanium;

[0041] • The semiconductor material of the carrier substrate is selected from silicon carbide, silicon, gallium nitride and germanium, and has a single crystal, polycrystalline or amorphous structure;

[0042] The metallic materials for the membrane are selected from tungsten, titanium, nickel, aluminum, molybdenum, niobium, tantalum, cobalt, and copper;

[0043] Depending on the properties of the metal material of the encapsulation film and one or more semiconductor materials of the working layer and the carrier substrate, the critical temperature is between 500°C and 1800°C. Attached Figure Description

[0044] Other features and advantages of the invention will become apparent from the following detailed description of the invention, taken with reference to the accompanying drawings, in which:

[0045] Figure 1 The structure according to the present invention is presented;

[0046] Figures 2a to 2e The steps of the production process according to the present invention are presented;

[0047] Figures 3a to 3d Variations of the steps of the production process according to the present invention are presented;

[0048] Figure 4 The diagram shows a current curve as a function of applied voltage, measured using two electrodes formed on the structure according to the invention, with the current path passing through the interface region of the structure. Figure 4 The current / voltage curves of a block substrate and a bonding structure that does not conform to the present invention are also shown by comparison.

[0049] Figure 5 A graph is shown that correlates the resistivity of a nodule in the interface region of the structure according to the invention with the coverage of the nodule, so as to obtain various resistivity levels of the interface region.

[0050] Figure 6 The graph shows the current as a function of voltage, and the resistivity of the interface region varies with the thickness of the film made of metallic material deposited before the formation of the intermediate structure. Detailed Implementation

[0051] In the description, the same reference numerals in the figures can be used for the same type of elements. The figures are schematic representations and are not to scale for readability. In particular, the thickness of the layers along the z-axis is not proportional to the lateral dimensions along the x and y axes; the relative thickness of the layers relative to each other is not taken into account in the figures.

[0052] This invention relates to a semiconductor structure 100, which includes a working layer 10 made of a single-crystal semiconductor material, a carrier substrate 30 made of a semiconductor material, and an interface region 20 between the working layer 10 and the carrier substrate 30. Figure 1 Similar to working layer 10, interface area 20 extends parallel to the main plane (x,y).

[0053] Advantageously, and indeed in the field of microelectronics, the semiconductor structure 100 takes the form of a circular wafer with a diameter between 100 mm and 450 mm and a total thickness typically between 300 micrometers and 1000 micrometers. It will be understood that, in this case, the carrier substrate 30 and the working layer 10 also take this circular shape. The (circular) front side 100a and back side 100b of the wafer extend parallel to the principal plane (x, y).

[0054] Various types of semiconductor structures 100 that allow vertical electrical conduction between the working layer 10 and the carrier substrate 30 may be of interest for microelectronic applications: the properties of the materials constituting the working layer 10 and the carrier substrate 30 can therefore vary greatly.

[0055] For example, the semiconductor material of the working layer 10 can be selected from silicon carbide, silicon, gallium nitride, and germanium. Typically, manufacturing components on the working layer 10 requires that the layer 10 exhibit high crystal quality: it is therefore selected as a single crystal with a quality grade, type, and doping level that matches the target application.

[0056] As an example again, the semiconductor material of the carrier substrate 30 may be selected from silicon carbide, silicon, gallium nitride, and germanium. It preferably exhibits a lower quality level, particularly for economic reasons, and may be a single-crystal, polycrystalline, or amorphous structure. Its type and doping level are selected to suit the target application.

[0057] The interface region 20 of the semiconductor structure 100 according to the invention is characterized in that it includes conductive nodules 21. Each of these nodules 21 includes a metallic material capable of forming an ohmic contact with the working layer 10 and the carrier substrate 30. Not limited thereto, the metallic material of the nodule 21 may be selected from tungsten, titanium, nickel, aluminum, molybdenum, niobium, tantalum, cobalt, and copper. As is known to those skilled in the art, not all of these materials are capable of forming an ohmic contact with all of the semiconductor materials mentioned that are capable of forming the working layer 10 and / or the carrier substrate 30. The metallic material of the nodule 21 will therefore be selected according to the properties of the working layer 10 and the carrier substrate 30. Several specific examples will be further described below.

[0058] The nodules 21 of the interface region 20 also exhibit a low or even very low thickness along the axis z perpendicular to the principal plane (x,y): typically less than or equal to 30 nm, less than or equal to 20 nm, less than or equal to 10 nm, or even less than or equal to 5 nm.

[0059] The nodules 21 distributed in the interface region 20 are discontinuous or joined; the discontinuous nodules are separated from each other mainly through the regions 22 where the working layer 10 is in direct contact with the carrier substrate 30 (in other words, there is a direct bond between the semiconductor materials of the working layer 10 and the carrier substrate 30). These regions 22 will be referred to below as the direct contact regions 22.

[0060] Potentially, in some cases of the semiconductor structure 100, cavities of nanometer thickness may exist in these contact regions 22, but said cavities occupy less than 20% or less than 10% or even less than 5% of the area occupied by the contact region 22 in the principal plane (x,y). Their thickness is also less than the thickness of the nodule 21.

[0061] The semiconductor structure 100 according to the invention ensures excellent conductivity between the working layer 10 and the carrier substrate 30 via its interface region 20. In particular, nodules 21 distributed in the interface region 20 in a midplane P substantially parallel to the principal plane (x,y) establish ohmic contact with the working layer 10 and the carrier substrate 30, and are at least partially formed of a metallic material that is a very good electrical conductor. They thus allow for effective vertical electrical conduction.

[0062] Between the discontinuous nodules 21, the direct contact regions 22 may potentially allow electrical conduction, but this is less effective than with the nodules 21. However, these direct contact regions 22 ensure the mechanical continuity of the interface region 20 and provide excellent mechanical strength between the working layer 10 and the carrier substrate 30. The quality of the working layer 10 is therefore unaffected by potential voids or interface defects; it should be noted that, when present, the aforementioned cavities have dimensions and density that do not negatively impact the quality and mechanical strength of the working layer 10.

[0063] In the midplane P of the interface region 20, the coverage of nodules 10 is typically between 1% and 70%, preferably between 10% and 60%.

[0064] Preferably, nodule 21 exhibits a molecular weight of less than 0.1 mohm·cm. 2 or even less than or equal to 0.01 mohm·cm 2 The resistivity. Here, due to its very low thickness, ohm·cm is used for nodule 21 (or more generally, for interface region 20). 2 The resistivity.

[0065] The resistivity of nodule 21 includes the resistivity of the metallic material forming nodule 21, the specific contact resistance between nodule 21 and working layer 10, and the specific contact resistance between nodule 21 and carrier substrate 30. These contact resistances dominate the overall vertical resistance. Therefore, in ohm·cm... 2 It makes sense to express surface resistivity. Specific contact resistance can vary depending on the properties and / or doping of the respective materials of the working layer 10 and the carrier substrate 30. As an example, a substrate made of nickel (Ni) and silicon carbide (SiC) has a specific resistivity of 4E15 / cm. 3 The specific contact resistance of a junction characterized by an N-type doping level (nitrogen or phosphorus dopant) will be approximately 3 mΩ·cm. 2 For 1E19 / cm 3 The N-type doping level will be approximately 0.003 mΩ·cm. 2 .

[0066] Figure 5The graph shows the resistivity variation of the interface region 20 as a function of the resistivity of the nodal 21 and its coverage in the midplane P. As mentioned above, for power applications, the target resistivity of the interface region 20 is less than or equal to 1 mol·cm⁻¹. 2 or even less than or equal to 0.1 mohm·cm 2 .

[0067] According to an advantageous embodiment, the working layer 10 and the carrier substrate 30 are formed of the same semiconductor material and are characterized by the same doping type, so as to allow effective vertical electrical conduction between the components to be produced in and / or on the working layer 10 and the components and / or electrodes to be produced on the back side 30b of the carrier substrate 30 of the structure 100.

[0068] According to the first example, the semiconductor structure 100 according to the invention includes a working layer 10 made of high-quality single-crystal silicon carbide; high quality generally means having less than one microtube (MP) / cm. 2 Less than 500 thread type dislocations (TSD) / cm 2 Less than 5000 thread edge dislocations (TED) / cm 2 Less than 1000 base plane dislocations (BPD) / cm 2 And SiC with less than 1 layer fault (SF) / cm. SiC with a working layer of 10 has a fault density of 8 × 10⁻⁶. 18 / cm 3 Characterized by N-type doping. The semiconductor structure 100 also includes a carrier substrate 30, which is made of low-quality single-crystal or polycrystalline silicon carbide and characterized by N-type doping with a resistivity of approximately 20 mΩ·cm. The junctions 21 are made of tungsten (W); they may have a thickness of approximately 5 nm and a coverage between 15% and 25%. The resistivity of the interface region 20 of this structure 100 is approximately 0.05 mol·cm. 2 That is, less than or equal to 0.1 mohm·cm 2 .

[0069] According to a second example, the semiconductor structure 100 according to the present invention includes: a working layer 10, which is made of high-quality single-crystal silicon carbide, with a density of 1×10⁻⁶. 19 / cm 3 Characterized by P-type doping; and a carrier substrate 30, which is made of low-quality single-crystal or polycrystalline silicon carbide, with a density of 5 × 10⁻⁶. 19 / cm 3 Characterized by p-type doping. The nodules 21 of the interface region 20 are made of titanium (Ti); they have a thickness of approximately 6 nm and a coverage between 30% and 40%. The resistivity of the interface region 20 of this structure 100 is less than 1 mol·cm⁻¹. 2 .

[0070] According to a third example, the semiconductor structure 100 according to the present invention includes: a working layer 10, which is made of high-quality single-crystal silicon, with a density of 5 × 10⁻⁶. 19 / cm 3 Characterized by N-type doping; and a carrier substrate 30, which is made of low-quality single-crystal or polycrystalline silicon carbide, with a density of 5 × 10⁻⁶. 19 / cm 3 Characterized by N-type doping. Nodules 21 are made of aluminum (Al); they have a thickness of approximately 3 nm and a coverage between 5% and 15%. The resistivity of the interface region 20 of this structure 100 is less than 1 mol·cm⁻¹. 2 .

[0071] Of course, this list of examples is not exhaustive. While observing the above-described conditions of the interface region 20, many other semiconductor structures 100 according to the present invention can be produced based on various combinations of materials of the working layer 10, the nodule 21 and the carrier substrate 30.

[0072] In particular, power components can be manufactured on and / or in the working layer 10 of the semiconductor structure 100 according to the invention. Specifically, these components may include at least one electrical contact on and / or in the carrier substrate 30 at the level of the back surface 100b of the semiconductor structure 100. As a non-limiting example, these power components may include transistors, diodes, thyristors, or passive components (capacitors, inductors, etc.).

[0073] The present invention also relates to a process for producing the semiconductor structure 100 as described above.

[0074] The manufacturing process first includes step a) of providing a working layer 10 made of single-crystal semiconductor material. Figure 2a In step a), the working layer 10 has a free face 10a, which is intended to be joined in a later step of the process and is also referred to as the front face 10a; it also has a back face 10b opposite to its front face 10a.

[0075] According to an advantageous implementation, the working layer 10 is obtained from the transfer of the surface layer from the donor substrate 1, particularly the layer transfer based on the Smart Cut process.

[0076] Therefore, step a) may include the operation of injecting a light material (e.g., hydrogen, helium, or a combination of both) into the donor substrate 1 to form a buried weakening plane 11 that defines the working layer 10 together with the front side 10a of the donor substrate 1. Figure 3a ).

[0077] According to a variant of this implementation, step a) includes forming a donor substrate 1 by epitaxially growing a donor layer 1' on an initial substrate prior to implanting the light material. Figure 3bThis variant allows for the formation of a donor layer 1' that exhibits the structural and electrical properties required for the target application. In particular, excellent crystal quality can be obtained through epitaxy, and the in-situ doping of the donor layer 1' can be precisely controlled. Light material is then implanted into the donor layer 1' to form a buried weakening plane 11.

[0078] Alternatively, the working layer 10 provided in step a) can of course be formed using other known techniques for transferring thin layers.

[0079] The manufacturing process according to the present invention next includes step b) of providing a carrier substrate 30 made of semiconductor material. Figure 2b The carrier substrate 30 has a free surface 30a, which is intended to be bonded in a later step of the process and is also referred to as the front side 30a; it also has a back side 30b.

[0080] As mentioned above in the description of semiconductor structure 100, the working layer 10 may be formed of one or more materials selected from silicon carbide, silicon, gallium nitride and germanium; and the carrier substrate 30 may be formed of one or more materials selected from silicon carbide, silicon, gallium nitride and germanium, preferably having a lower quality, whether it is single crystal, polycrystalline or even amorphous.

[0081] According to one particular embodiment, the working layer 10 and the carrier substrate 30 are formed of the same semiconductor material and are characterized by the same doping type (N or P).

[0082] The manufacturing process then includes: step c), on the free surface 10a to be bonded of the working layer 10 or on the free surface 30a to be bonded of the carrier substrate 30, or as... Figure 2c As shown, a film 2 made of a metallic material is deposited on two free surfaces 10a and 30a to be joined. The metallic material is selected to be suitable for forming an ohmic contact with the working layer 10 and the carrier substrate 30. It can be selected from the following non-limiting list of materials according to the properties of the working layer 10 and the carrier substrate 30: tungsten, titanium, nickel, aluminum, molybdenum, niobium, tantalum, cobalt, and copper.

[0083] The thickness of film 2 is less than or equal to 20 nm, preferably less than or equal to 10 nm, or even less than or equal to 5 nm. For example, the deposited film 2 may have a thickness of approximately 0.5 nm, 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 8 nm, 10 nm or 15 nm.

[0084] It should be noted that when film 2 is deposited on the two free surfaces 10a and 30a, the total deposition thickness (i.e., the sum of the thicknesses of film 2 deposited on each of the free surfaces 10a and 30a) is preferably less than or equal to 20 nm, or even less than or equal to 10 nm. The total thickness of the deposited film 2 must be kept low in order to allow the film to be segmented into nodules 21 in later steps of the process.

[0085] Film 2 is deposited in a non-oxidizing controlled atmosphere. It is important for the metal film 2 to avoid any oxidation or degradation by contaminants from the surrounding atmosphere. Typically, the deposition in step c) takes place over approximately 10... -6 Performed in a high vacuum of Pa or lower.

[0086] Depending on the properties of the deposited film 2, the metal target is bombarded with neutral elements or non-destructive elements (Ar, Si, N, etc.) that are residual in the deposited metal, and step c is advantageously performed at ambient temperature or cryogenic temperature using sputtering deposition technology.

[0087] According to one particular implementation, the manufacturing process according to the invention includes a step c') of deoxidizing the free surfaces 10a to be bonded of the working layer 10 and / or the free surfaces 30a to be bonded of the carrier substrate 30 before the deposition step c). This step allows the removal of any native oxides present on the surfaces of the working layer 10 and / or the carrier substrate 30, which facilitates the formation of ohmic contacts with the metallic material in later steps of the process. Deoxidation can be performed by wet (e.g., by HF attack) or dry (dry etching or annealing in a reducing atmosphere) chemical treatment.

[0088] The manufacturing process then includes step d) of forming an intermediate structure 150, which involves directly bonding the free surfaces 10a and 30a of the working layer 10 and the carrier substrate 30 to be bonded at the bonding interface 15, respectively. Figure 2d ).

[0089] This direct bonding is preferably performed via molecular adhesion bonding, including placing the surfaces 10a and 30a to be bonded in contact under a non-oxidizing controlled atmosphere. This can be a direct bond between the working layer 10 and the film when the film 2 is deposited only on the working layer 10, or a direct bond between the carrier substrate 30 and the film when the film 2 is deposited only on the working layer 10, or a direct bond between the two films 2 when both films 2 are deposited on the working layer 10 and the carrier substrate 30.

[0090] Direct bonding is preferred at approximately 10 -6 Performed under a controlled atmosphere of Pa or less, especially under high vacuum.

[0091] Advantageously, the deposition in step c) and the direct bonding in step d) are performed one after another without interruption, in a vacuum, in situ, or in a multi-chamber apparatus. As an example, Canon's BV7000 atomic diffusion bonding apparatus is cited, in which metal deposition and direct bonding can be performed continuously while maintaining a controlled atmosphere.

[0092] Reference Figures 3a to 3dThe advantageous implementation shown includes step d) of direct bonding of the free surface 10a to be bonded of the working layer 10 to the free surface 30a to be bonded of the carrier substrate 30, resulting in a bonding assembly 200 comprising the donor substrate 1, the carrier substrate 30, and the bonding interface 15. Figure 3c Step d) further includes separation at the level of the buried weakening plane 11 to form, on the one hand, an intermediate structure 150 comprising the working layer 10, one or more films 2 and a carrier substrate 30, and on the other hand, the remaining portion of the donor substrate 1”. Figure 3d This separation can be performed during a heat treatment that allows cavities and microcracks caused by the injected material to grow in the buried weakening layer 11. Separation can also be performed by applying mechanical stress, or by a combination of thermal and mechanical stress, as is well known with reference to the Smart Cut process.

[0093] A sequence of separating surfaces 10b of the working layer 10 and / or separating surfaces 1”a of the remaining portion of the donor substrate 1” can be performed to clean, smooth, polish, or etch the working layer 10 in order to restore good surface quality, particularly in terms of roughness, defect density, and other contaminants.

[0094] Regardless of the implementation method of the process, upon completion of step d), the intermediate structure 150 has a front side 10b on the working layer 10 side, a back side 30b on the carrier substrate 30 side, and an encapsulation film 2' between the working layer 10 and the carrier substrate 30. Note that when the encapsulation film 2' is deposited only on one of the free surfaces 10a and 30a to be bonded, this film corresponds to film 2, or corresponds to two films 2 respectively deposited on the working layer 10 and the carrier substrate 30.

[0095] The manufacturing process according to the invention further includes: step e), annealing the intermediate structure 150 at a temperature above or equal to the critical temperature, so that the encapsulation film 2' is segmented into conductive nodules 21 and forms an interface region 20. Figure 2e Step e) results in the formation of semiconductor structure 100.

[0096] Here, the critical temperature refers to the temperature at which the contact between the metal of the encapsulation film 2' and the semiconductor of the working layer 10 and the carrier substrate 30 becomes an ohmic contact: for example, between 400°C and 650°C for Al / Si pairs, between 950°C and 1100°C for Ni / SiC pairs, and so on. Furthermore, the critical temperature must be high enough to allow the bonding of the direct contact areas 22 between the junctions 21.

[0097] Depending on the properties of the metallic material and the semiconductor structure 100, one or more semiconductor materials typically range from 500°C to 1800°C.

[0098] Above this critical temperature, the system, including the encapsulation film 2' and the semiconductor surfaces of the working layer 10 and the carrier substrate 30 that are in contact with the film 2', will optimize its surface energy by clustering the encapsulation film 2' into nodules 21 that establish ohmic contact with the semiconductor surface, and by creating direct contact regions 22 between the semiconductor surfaces of the working layer 10 and the carrier substrate 30, respectively.

[0099] Furthermore, because the encapsulation film 2' is extremely thin, metallic materials known to be stable only at low or medium temperatures can be used in the semiconductor structure 100 according to the invention, which is capable of undergoing processing at high temperatures (900°C-1100°C) or even very high temperatures (1200°C-1800°C). Specifically, since they cluster into small and very thin nodules 21, they do not cause degradation of the structure 100, particularly the working layer 10. For example, reference can be made to the case of nodules 21 made of nickel or titanium in the structure 100 comprising the working layer 10 made of SiC and the carrier substrate 30, which are intended to undergo epitaxy at temperatures between 1600°C and 1800°C.

[0100] The manufacturing process described thus enables the production of a semiconductor structure 100 that provides vertical electrical conduction between the working layer 10 and the carrier substrate 30 via the interface region 20. The very thin junctions 21 are primarily made of metal, thus exhibiting very low resistivity. Furthermore, the presence of direct contact regions 22 between the discontinuous junctions 21 avoids any problems with the mechanical strength or, more generally, the reliability of the working layer 10 and / or the components to be manufactured on or in this layer. Finally, since the invention is based on bonding via the metal film 2, the increase in interface resistivity associated with the direct bonding of semiconductor materials with different crystalline properties is not a problem for the vertical electrical conduction in the structure 100, as the junctions 21 ensure said conduction.

[0101] Exemplary implementation:

[0102] Donor substrate 1 is made of high-quality single-crystal 4H SiC and has a diameter of 150 mm. Donor substrate 1 is N-doped and has a resistivity of approximately 20 molhm·cm. (The last sentence appears to be incomplete and possibly refers to a measurement or measurement.) E Hydrogen ions are injected through its front side 1a (“C” side) at a dose of 16 / cm² and an energy of 95 keV. Thus, a buried weakening plane 11 is defined around the injection depth, which together with the front side 10a of the donor substrate 1 defines the working layer 10.

[0103] The carrier substrate 30 is made of low-quality single-crystal 4H SiC and has the same diameter as the donor substrate 1. It is N-doped and has a resistivity of approximately 20 molhm·cm.

[0104] The two substrates 1 and 30 undergo a cleaning sequence to remove particles and other surface contaminants. The sequence is preferably selected such that the surfaces of substrates 1 and 30 do not undergo oxidation (no native oxides are present).

[0105] Substrates 1 and 30 are introduced into the first deposition chamber integrated into the direct bonding apparatus. In a vacuum at 10... -6 At Pa and ambient temperature, a tungsten film 2 with a thickness of 0.5 nm is deposited on each of the front surfaces 10a and 30a (free surfaces to be bonded) of substrates 1 and 30 by sputtering.

[0106] By placing the films 2, which are respectively deposited on the donor substrate 1 and the carrier substrate 30, in direct contact, the substrates 1 and 30 are introduced into the second bonding chamber for bonding at their front surfaces 10a and 30a. The atmosphere in the bonding chamber is the same as that in the deposition chamber, which prevents any oxidation or passivation of the surface of the film 2.

[0107] After bonding, the bonding assembly 200 includes a donor substrate 1 connected to a carrier substrate 30 via a bonding interface 15 and an encapsulation film 2' formed by two films 2 deposited and buried between the two substrates 1 and 30. The encapsulation film 2' has a thickness of approximately 1 nm.

[0108] The component 200 is heat-treated at approximately 900°C for 30 minutes to induce separation at the buried weakened plane 11. An intermediate structure 150 is then obtained, comprising a 500 nm thick working layer 10 disposed on an encapsulation film 2', which itself is disposed on a carrier substrate 30. A cleaning and polishing sequence is applied to restore the defect density and roughness of the surface 10b of the working layer 10 to a satisfactory level.

[0109] Finally, the intermediate structure 150 is annealed at 1700°C for 30 minutes. A protective layer is pre-formed on the front surface 10b of the intermediate structure 150 (which is also the free surface 10b of the working layer 10 in the intermediate structure 150). Once this annealing is complete, the structure 100 according to the invention is obtained: a junction region 20 is formed, and tungsten nodules 21 separated by the direct contact region 20 between the working layer 10 and the carrier substrate 30 provide excellent vertical conductivity to the structure 100, almost identical to that of a bulk SiC substrate exhibiting a resistivity of 20 molhm·cm. This is in… Figure 4 The curve is obvious. Figure 4 The diagram shows the current curve as a function of voltage I(V) for a simple component comprising two metal contact electrodes. In the case of the structure 100 according to the invention, I(V) is measured at both electrodes, and the current path between the two electrodes passes through the interface region 20. The interface region 20 has a current density less than or equal to 0.1 mol·cm⁻¹. 2 The resistivity.

[0110] The nodules 21 in the structure 100 have a thickness of approximately 5 nm and an average diameter of approximately 20 nm. The coverage of nodules 21 in the midplane of the interface region 20 is approximately 20%.

[0111] Figure 4 The curves are shown for comparison, illustrating the I(V) curves of structures based on direct SiC / SiC bonding as "bondings not conforming to the present invention," wherein the bonding surface is heavily doped (nitrogen implantation), and the SiC substrate has the same resistivity as in structure 100 described above. The improvement in resistivity of the interface region provided by the present invention... Figure 4 It is clearly obvious in the text.

[0112] Under the same experimental conditions as described above, it has been observed that the resistivity of the interface region 20 can be further reduced for a packaging film 2' with a thickness of approximately 2 nm or even 3 nm. Figure 6 The effect of the thickness of the encapsulation film 2' in the range of 0.4 nm to 2 nm on the I(V) curve is shown: the I(V) curve of the encapsulation film 2' with a thickness of 2 nm is very close to that obtained using a bulk SiC substrate.

[0113] Of course, the present invention is not limited to the described embodiments and examples, and alternative embodiments may be introduced without departing from the scope of the invention as defined by the claims.

Claims

1. A semiconductor structure (100) comprising a working layer (10) made of a single-crystal semiconductor material extending on a principal plane (x,y), a carrier substrate (30) made of a semiconductor material, and an interface region (20) extending parallel to the principal plane (x,y) between the working layer (10) and the carrier substrate (30), characterized in that the interface region (20) comprises nodules (21): - The nodule (21) is conductive and includes a metallic material that forms an ohmic contact with the working layer (10) and the carrier substrate (30). - The nodule (21) has a thickness of less than or equal to 30 nm along the axis (z) perpendicular to the principal plane (x, y). - The nodules (21) are discontinuous or joined, and the discontinuous nodules (21) are separated from each other through the direct contact area (22) between the working layer (10) and the carrier substrate (30). - The nodule (21) is obtained from the segmentation of the encapsulation film (2') made of the metal material under annealing, prior to the annealing, the encapsulation film (2') extends continuously between the working layer (10) and the carrier substrate (30).

2. The semiconductor structure (100) according to claim 1, wherein, The working layer (10) and the carrier substrate (30) are formed of the same semiconductor material and have the same doping type.

3. The semiconductor structure (100) according to claim 1, wherein, The semiconductor material of the working layer (10) is selected from silicon carbide, silicon, gallium nitride and germanium.

4. The semiconductor structure (100) according to claim 1, wherein, The semiconductor material of the carrier substrate (30) is selected from silicon carbide, silicon, gallium nitride and germanium, and has a single crystal, polycrystalline or amorphous structure.

5. The semiconductor structure (100) according to claim 1, wherein, The metallic material of the nodule (21) is selected from tungsten, titanium, nickel, aluminum, molybdenum, niobium, tantalum, cobalt and copper.

6. The semiconductor structure (100) according to claim 1, wherein, The coverage of the nodules (21) in the midplane (P) of the interface region (20) is between 1% and 70%.

7. The semiconductor structure (100) according to claim 1, wherein, The nodule (21) has a density of less than 0.1 mohm·cm. 2 The resistivity is such that the interface region (20) has a resistivity of less than 0.1 mol·cm⁻¹. 2 The resistivity.

8. The semiconductor structure (100) according to claim 1, wherein, The nodule (21) has a thickness of less than or equal to 20 nm.

9. A power component manufactured on and / or in the working layer (10) of a semiconductor structure (100) according to any one of claims 1 to 8, the power component comprising at least one electrical contact on and / or in the carrier substrate (30) at a horizontal position on the back side of the semiconductor structure (100).

10. A manufacturing process for a semiconductor structure (100) according to any one of claims 1 to 8, the manufacturing process comprising the following steps: a) Provide a working layer (10) made of single-crystal semiconductor material with a free surface (10a) to be bonded. b) Provide a carrier substrate (30) made of semiconductor material having a free surface (30a) to be bonded. c) Deposit a film (2) made of a metallic material on the free surface (10a) to be bonded of the working layer (10) and / or the free surface (30a) to be bonded of the carrier substrate (30) under a non-oxidizing controlled atmosphere. The film (2) is capable of forming an ohmic contact with the working layer (10) and the carrier substrate (30) and has a thickness of less than or equal to 20 nm. d) Forming an intermediate structure (150), including operations of directly bonding the free surfaces to be bonded of the working layer (10) and the free surfaces to be bonded of the carrier substrate (30) under a non-oxidizing controlled atmosphere, the intermediate structure (150) comprising an encapsulation film (2') derived from one or more films (2) deposited in step c). e) Anneal the intermediate structure (150) at a temperature above or equal to the critical temperature so that the encapsulation film (2') is segmented into conductive nodes (21) that form ohmic contacts with the working layer (10) and the carrier substrate (30), and the interface region (20) is formed.

11. The production process according to claim 10, wherein, The working layer (10) and the carrier substrate (30) are formed of the same semiconductor material and have the same doping type.

12. The production process according to claim 10, wherein, Step a) includes the operation of injecting a light material into a donor substrate (1) to form a buried weakening plane (11), the buried weakening plane (11) defining the working layer (10) together with the front side (10a) of the donor substrate (1).

13. The production process according to claim 12, wherein, Step a) includes forming the donor substrate (1) by epitaxially growing a donor layer (1') on an initial substrate, and then performing the implantation into the donor layer (1').

14. The production process according to claim 12, wherein, Step d) includes separating at the level of the buried weakening plane (11) after the direct bonding produces the bonding assembly (200) including the donor substrate (1) and the carrier substrate (30), to form, on the one hand, the intermediate structure (150) including the working layer (10), the encapsulation film (2') and the carrier substrate (30), and on the other hand, the remaining portion of the donor substrate (1).

15. The manufacturing process according to claim 10, wherein the manufacturing process includes a step c' of deoxidizing the free surface (10a) to be bonded of the working layer (10) and / or the free surface (30a) to be bonded of the carrier substrate (30) prior to the deposition step c).

16. The production process according to claim 10, wherein, The deposition in step c) and the direct bonding in step d) are performed integrally in the same device.

17. The production process according to claim 10, wherein, The thickness of the film (2) deposited in step c) is less than or equal to 10 nm.

18. The production process according to claim 10, wherein, Steps c) and d) are performed in a vacuum.

19. The production process according to claim 10, wherein, Deposition step c) is performed using sputtering technology at ambient temperature.

20. The production process according to claim 10, wherein, The critical temperature is between 500°C and 1800°C, depending on the properties of the metal material of the encapsulation film (2') and the one or more semiconductor materials of the working layer (10) and the carrier substrate (30).

Images