Chip detection method and device, storage medium and electronic device

Abstract

This application provides a chip testing method, apparatus, storage medium, and electronic device. The method includes: with a target fixture connected to a set of pins of a chip under test (DUT), detecting the impedance values ​​between the set of pins to obtain a set of impedance values; determining whether the impedance of the DUT is normal based on the set of impedance values; if the impedance of the DUT is determined to be normal, inputting a predetermined voltage signal to a first input pin of the DUT and acquiring a target output signal from a first output pin of the DUT, wherein the target output signal is the signal output by the DUT after performing a target function when the input voltage signal is the predetermined voltage signal; and determining whether the DUT is abnormal based on the target output signal. This application solves the technical problem of low chip testing efficiency in related technologies, thereby improving the efficiency of chip testing.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and more specifically, to a chip testing method and apparatus, a storage medium, and an electronic device. Background Technology

[0002] A server system comprises hundreds or even thousands of chips. These chips, along with power supply lines and logic circuits, work together to drive the load on the CPU, memory, PCH, and other components, ultimately enabling system functionality. Therefore, ensuring high-quality chip soldering and proper functioning is crucial for the robust and secure operation of a server system. Generally, PCB manufacturers use methods like X-rays to check IC soldering success during the soldering process. After the PCB leaves the production line, if chips are re-soldered or faulty chips need to be analyzed, manual inspection, impedance measurement with a multimeter, and power-on testing are required to check for issues such as cold solder joints and short circuits. However, manual inspection of chip pins has limitations and often fails to accurately identify anomalies. Using a multimeter to measure impedance is inefficient, and directly powering the PCB carries the potential risk of device burnout. Clearly, current chip testing methods suffer from low efficiency.

[0003] No effective solution has yet been proposed to address the technical problem of low efficiency in chip detection in related technologies. Summary of the Invention

[0004] This application provides a chip detection method and apparatus, a storage medium and an electronic device, to at least solve the technical problem of low efficiency in chip detection in related technologies.

[0005] According to one embodiment of this application, a chip testing method is provided, comprising: when a target fixture is connected to a set of pins of a chip under test, detecting the impedance value between the set of pins to obtain a set of impedance values; determining whether the impedance of the chip under test is normal based on the set of impedance values; if the impedance of the chip under test is determined to be normal, inputting a predetermined voltage signal to a first input pin of the chip under test and obtaining a target output signal of a first output pin of the chip under test, wherein the set of pins includes the first input pin and the first output pin, and the target output signal is the signal output by the chip under test after performing a target function when the input voltage signal is the predetermined voltage signal; and determining whether the chip under test is abnormal based on the target output signal.

[0006] In an exemplary embodiment, determining whether the impedance of the chip under test is normal based on the set of impedance values ​​includes: determining that the impedance of the chip under test is normal when the impedance values ​​between each pair of pins in the N pairs of pins in the set of pins all satisfy the predetermined impedance conditions corresponding to each pair of pins, wherein the set of impedance values ​​includes the impedance values ​​between each pair of pins in the N pairs of pins, and N is equal to 1, or is a positive integer greater than or equal to 2.

[0007] In an exemplary embodiment, the method further includes performing the following steps on the i-th pair of pins in the N pairs of pins, wherein i is a positive integer greater than or equal to 1 and less than or equal to N: if the i-th pair of pins are two pins in the chip under test that have a short-circuit connection, determining whether the impedance value between the i-th pair of pins is 0; if the impedance value between the i-th pair of pins is 0, determining that the impedance value between the i-th pair of pins satisfies the i-th impedance condition corresponding to the i-th pair of pins, wherein the i-th impedance condition means that the impedance value between the i-th pair of pins is 0; or in When the i-th pair of pins are two pins in the chip under test that have a short-circuit connection, it is determined whether the impedance value between the i-th pair of pins is within the i-th predetermined impedance range. If the impedance value between the i-th pair of pins is within the i-th predetermined impedance range, it is determined that the impedance value between the i-th pair of pins satisfies the i-th impedance condition corresponding to the i-th pair of pins. The i-th impedance condition means that the impedance value between the i-th pair of pins is within the i-th predetermined impedance range, and the i-th predetermined impedance range is [0, A), or [0, A], where A is a positive number greater than 0.

[0008] In an exemplary embodiment, the method further includes performing the following steps on the i-th pair of pins in the N pairs of pins, wherein i is a positive integer greater than or equal to 1 and less than or equal to N: when the i-th pair of pins are two pins in the chip under test that have an open-circuit connection, determining whether the impedance value between the i-th pair of pins is within the i-th predetermined impedance range; when the impedance value between the i-th pair of pins is within the i-th predetermined impedance range, determining that the impedance value between the i-th pair of pins satisfies the i-th impedance condition corresponding to the i-th pair of pins, wherein the i-th impedance condition means that the impedance value between the i-th pair of pins is within the i-th predetermined impedance range, and the i-th predetermined impedance range is a positive number greater than A, or, is a positive number greater than or equal to A, or, is [A,B), or, is [A,B], or, is (A,B), or, is (A,B], where A is a positive number greater than 0 and B is a positive number greater than A.

[0009] In an exemplary embodiment, inputting a predetermined voltage signal to the first input pin of the chip under test includes: inputting the predetermined voltage signal to the first input pin of the chip under test via a signal generator, wherein the signal generator is connected to the first input pin via the target fixture.

[0010] In an exemplary embodiment, determining whether the chip under test is abnormal based on the target output signal includes: determining that the chip under test is normal if the voltage value of the target output signal is within a predetermined voltage value range, wherein the predetermined voltage value range corresponds to the target function, or corresponds to the target function and the predetermined voltage signal; and determining that the chip under test is abnormal if the voltage value of the target output signal is not within the predetermined voltage value range.

[0011] In an exemplary embodiment, detecting the impedance value between the set of pins to obtain a set of impedance values ​​includes: detecting the impedance value between each pair of pins in the N pairs of pins in the set of pins through an impedance detection module to obtain the set of impedance values, wherein the impedance detection module is connected to the target fixture through a target cable, a set of clamps of the target fixture corresponds one-to-one with a set of pins of the chip under test, the target cable includes a wire corresponding to each clamp of the set of clamps of the target fixture, and N is equal to 1, or is a positive integer greater than or equal to 2.

[0012] In one exemplary embodiment, the N pairs of pins in the set of pins include: every two adjacent pins in the set of pins, or every two pins in the set of pins.

[0013] In one exemplary embodiment, the method further includes: issuing a target prompt signal when it is determined that the impedance of the chip under test is abnormal, wherein the target prompt signal is used to indicate that the impedance of the chip under test is abnormal.

[0014] According to another embodiment of this application, a chip testing device is also provided, comprising: a target fixture configured to be connected to a set of pins of a chip under test (DUT) and clamp the DUT; an impedance detection module connected to the target fixture, configured to detect the impedance values ​​between the set of pins through the target fixture to obtain a set of impedance values; a signal generator connected to a first input pin of the DUT through the target fixture, configured to input a predetermined voltage signal to the first input pin when the impedance of the DUT is determined to be normal based on the set of impedance values; and a chip testing module configured to acquire a target output signal of a first output pin of the DUT when the signal generator inputs the predetermined voltage signal to the first input pin of the DUT, and determine whether the DUT is abnormal based on the target output signal, wherein the set of pins includes the first input pin and the first output pin, and the target output signal is the signal output by the DUT after performing a target function when the input voltage signal is the predetermined voltage signal.

[0015] In one exemplary embodiment, the target fixture includes a set of clamps corresponding to the number of the set of pins; the impedance detection module is connected to the target fixture via a target cable, the target cable including a wire corresponding to each clamp in the set of clamps of the target fixture; the signal generator is connected to the first input pin via the target cable.

[0016] In one exemplary embodiment, the impedance detection module is connected to the signal generator. The impedance detection module is configured to send a target start signal to the signal generator when the impedance of the chip under test is determined to be normal based on the set of impedance values. The target start signal is used to instruct the signal generator to input the predetermined voltage signal to the first input pin of the chip under test.

[0017] In one exemplary embodiment, the device further includes: a first indicator light configured to emit a first color light when the impedance of the chip under test is determined to be normal based on the set of impedance values, or to emit a second color light when the impedance of the chip under test is determined to be abnormal based on the set of impedance values; and / or a second indicator light configured to illuminate when the voltage value of the target output signal is within a predetermined voltage value range, or not illuminate when the voltage value of the target output signal is outside the predetermined voltage value range, wherein the predetermined voltage value range corresponds to the target function, or corresponds to the target function and the predetermined voltage signal.

[0018] According to another embodiment of this application, a chip testing device is provided, comprising: a detection unit, configured to detect the impedance value between a set of pins of a target fixture and a chip under test, and obtain a set of impedance values; a first determination unit, configured to determine whether the impedance of the chip under test is normal based on the set of impedance values; a processing unit, configured to, when the impedance of the chip under test is determined to be normal, input a predetermined voltage signal to a first input pin of the chip under test, and obtain a target output signal of a first output pin of the chip under test, wherein the set of pins includes the first input pin and the first output pin, and the target output signal is a signal output by the chip under test after performing a target function when the input voltage signal is the predetermined voltage signal; and a second determination unit, configured to determine whether the chip under test is abnormal based on the target output signal.

[0019] According to yet another embodiment of this application, a computer-readable storage medium is also provided, wherein a computer program is stored therein, and the computer program is configured to perform the steps in any of the above method embodiments when it is run.

[0020] According to yet another embodiment of this application, an electronic device is also provided, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0021] Through the embodiments of this application, by connecting a target fixture to a set of pins of the chip under test (DUT) and detecting the impedance values ​​between these pins, a set of impedance values ​​is obtained. Based on these impedance values, it is determined whether the impedance of the DUT is normal. When the impedance of the DUT is determined to be normal, a predetermined voltage signal is input to the first input pin of the DUT to obtain the target output signal of the first output pin of the DUT. The target output signal is the signal output by the DUT after performing the target function with the predetermined voltage signal input. Then, it is determined whether the DUT is abnormal based on the target output signal. This achieves the goal of conveniently detecting the impedance of the DUT using a target fixture, and obtaining the target output signal by inputting a predetermined voltage signal when the impedance of the DUT is determined to be normal, thereby determining whether the DUT is abnormal based on the target output signal. This avoids the problem of low detection efficiency caused by manual observation or measuring the impedance between pins one by one with a multimeter in related technologies, and also avoids the problem of chip damage caused by directly powering on for testing without determining whether the chip impedance is normal. Therefore, it solves the technical problem of low chip detection efficiency in related technologies and achieves the effect of improving chip detection efficiency. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the hardware environment of a server for a chip detection method according to an embodiment of this application;

[0023] Figure 2 This is a flowchart of a chip detection method according to an embodiment of this application;

[0024] Figure 3 This is a structural block diagram of a chip testing device according to an embodiment of this application;

[0025] Figure 4 This is an example diagram of a chip fixture according to an embodiment of this application;

[0026] Figure 5 This is a schematic diagram of the control circuit of a chip testing device according to an embodiment of this application;

[0027] Figure 6 This is an example chip diagram according to an embodiment of this application;

[0028] Figure 7 This is a structural block diagram of a chip detection device according to an embodiment of this application. Detailed Implementation

[0029] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0030] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0031] The methods and embodiments provided in this application can be executed on a server, computer terminal, device terminal, or similar computing device. Taking running on a server as an example, Figure 1This is a schematic diagram of the hardware environment of a server for a chip detection method according to an embodiment of this application. Figure 1 As shown, a server may include one or more ( Figure 1 Only one is shown in the image. A processor 102 (which may include, but is not limited to, a microprocessor MCU or a programmable logic device FPGA, etc.) and a memory 104 for storing data are also shown. In one exemplary embodiment, the server may further include a transmission device 106 for communication functions and an input / output device 108. Those skilled in the art will understand that... Figure 1 The structure shown is for illustrative purposes only and does not limit the structure of the server described above. For example, the server may also include components that are more complex than... Figure 1 The more or fewer components shown, or having the same Figure 1 Equivalent functions or ratios shown Figure 1 The functions shown have more different configurations.

[0032] The memory 104 can be used to store computer programs, such as application software programs and modules, like the computer program corresponding to the chip detection method in this embodiment of the invention. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, thereby implementing the above-described method. The memory 104 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include memory remotely located relative to the processor 102, and these remote memories can be connected to a server via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0033] The transmission device 106 is used to receive or send data via a network. Specific examples of the network described above may include a wireless network provided by the server's communication provider. In one example, the transmission device 106 includes a Network Interface Controller (NIC), which can connect to other network devices via a base station to communicate with the Internet. In another example, the transmission device 106 may be a Radio Frequency (RF) module used for wireless communication with the Internet.

[0034] This embodiment provides a chip detection method. Figure 2 This is a flowchart of a chip detection method according to an embodiment of this application, such as... Figure 2 As shown, the process includes the following steps:

[0035] Step S202: With the target fixture and a set of pins of the chip under test already connected, detect the impedance value between the set of pins to obtain a set of impedance values;

[0036] Step S204: Determine whether the impedance of the chip under test is normal based on the set of impedance values.

[0037] Step S206: When it is determined that the impedance of the chip under test is normal, a predetermined voltage signal is input to the first input pin of the chip under test, and the target output signal of the first output pin of the chip under test is obtained. The set of pins includes the first input pin and the first output pin. The target output signal is the signal output by the chip under test after performing the target function when the input voltage signal is the predetermined voltage signal.

[0038] Step S208: Determine whether the chip under test is abnormal based on the target output signal.

[0039] Through the above steps, by connecting the target fixture to a set of pins of the chip under test (DUT) and detecting the impedance values ​​between these pins, a set of impedance values ​​is obtained. Based on these impedance values, it is determined whether the impedance of the DUT is normal. When the impedance of the DUT is determined to be normal, a predetermined voltage signal is input to the first input pin of the DUT to obtain the target output signal of the first output pin of the DUT. The target output signal is the signal output by the DUT after performing the target function under the input predetermined voltage signal. Then, it is determined whether the DUT is abnormal based on the target output signal. This achieves the goal of conveniently detecting the impedance of the DUT using the target fixture, and obtaining the target output signal by inputting a predetermined voltage signal when the impedance of the DUT is determined to be normal, thereby determining whether the DUT is abnormal based on the target output signal. This avoids the low detection efficiency caused by manual observation or measuring the impedance between each pin individually with a multimeter in related technologies, and also avoids the problem of chip damage caused by directly powering on for testing without determining whether the chip impedance is normal. Therefore, it solves the technical problem of low chip detection efficiency in related technologies, achieving the effect of improving chip detection efficiency.

[0040] The entity performing the above steps can be an equipment, such as a testing device, testing tool, or testing fixture, but is not limited to these.

[0041] In the technical solution provided in step S202 above, the target fixture includes a set of clamps, and the number of clamps corresponds to the number of chips. For example, for a PIN8 chip, the target fixture includes 8 clamps, or for a PIN6 chip, the configured target fixture has 6 clamps. The target fixture is used to clamp or fix a set of pins of the chip under test, and the set of clamps of the target fixture is connected to the set of pins of the chip under test. Usually, the clamps of the target fixture and the pins of the chip under test are metal. When a power-on test is performed, the clamps and the pins are electrically connected. In practical applications, the target fixture is equipped with one or more cables, including wires connected to each clamp pin. For a set of pins of the chip under test (e.g., PIN8, i.e., 8 pins), it may be necessary to test the impedance values ​​between multiple pairs of pins. A pair of pins includes two different pins, such as the impedance values ​​between two adjacent or non-adjacent pins. The wires corresponding to the pair of pins to be tested can be pre-connected to the test terminals of the impedance detection module. Similarly, if multiple pairs of pins need to be tested, the wires corresponding to the multiple pairs of pins to be tested can be pre-connected to the test terminals of the impedance detection module. Optionally, the impedance detection module can detect the impedance values ​​of multiple pairs of pins simultaneously; thus, a set of impedance values ​​can be obtained. Optionally, this step can be completed by the impedance detection module and the target fixture.

[0042] In the technical solution provided in step S204 above, the impedance of the chip under test is determined based on a set of impedance values. Taking a PIN8 chip as an example, if PIN-4 and PIN-5 (i.e., pins 4 and 5) are shorted, the impedance between the pair of pins formed by PIN-4 and PIN-5 should be zero or very small. The impedance value corresponding to this pair of pins in a set of impedance values ​​is used to determine whether the pair of pins is properly shorted. Alternatively, if pins PIN-1 and PIN-2 of the chip do not have a short circuit connection, the impedance value between the pair of pins formed by PIN-1 and PIN-2 should be greater than a certain resistance value (such as 2kΩ, or other values, or infinity). However, if the impedance value corresponding to this pair of pins (i.e., PIN-1 and PIN-5) is determined based on a set of impedance values, the impedance of the chip under test is determined to be normal. If the impedance value corresponding to PIN-2 is zero, it can be determined that there is a short circuit between PIN-1 and PIN-2. This may have been accidentally caused during PCB fabrication or surface mounting. Similarly, a set of impedance values ​​can be used to determine whether the impedance values ​​of each pin pair meet the predetermined impedance conditions or predetermined impedance range. Therefore, a set of impedance values ​​can be used to determine whether the impedance of the chip under test is normal. If it is determined that the impedance of the chip under test is abnormal, subsequent power-on testing is not necessary, i.e., basic functional testing of the chip is not required. This is because internal faults or faults between pins may cause the chip to burn out. This avoids the problem in related technologies where direct power-on testing without determining whether the chip impedance is normal can easily lead to chip damage.

[0043] In the technical solution provided in steps S206-S208 above, when it is determined that the impedance of the chip under test is normal, a predetermined voltage signal can be input to the first input pin of the chip under test. For example, the first input pin is the voltage input pin of the chip (such as VIN). The predetermined voltage signal can be set according to the detection needs of different chips under test. For example, the predetermined voltage signal can be a constant voltage signal, or it can be a pulse voltage signal or other signals. The magnitude of the predetermined voltage signal can also be set according to the specific chip under test. After inputting the predetermined voltage signal, the target output signal of the first output pin (such as VOUT) of the chip under test is obtained. The target output signal is the signal output by the chip under test after performing the target function. For example, if the chip under test is a chip with voltage conversion function, or a chip with buck or boost function, the output voltage VOUT is normally about 5V or 3V. At this time, the chip under test can be determined to be abnormal by detecting the target output signal of the first output pin. Optionally, while inputting a predetermined voltage signal to the first input pin of the chip under test, a second predetermined voltage signal can also be input to the second input pin of the chip under test (such as the EN terminal or the enable terminal). For example, the second predetermined voltage signal is a high-level or low-level signal. Step S206 can be executed by a signal generator (or signal generation module), while the target output signal can be executed by a chip detection module.

[0044] Optionally, the above steps can be performed by a testing device, which includes the impedance detection module, signal generator, and chip detection module. Optionally, the testing device may also include the target fixture, integrating the target fixture with the testing device. The target fixture can be easily disassembled, facilitating the replacement of different target fixtures when testing different models or types of chips. Through the above embodiments, the problem of low testing efficiency caused by manually observing or measuring the impedance between pins one by one using a multimeter, as found in related technologies, is avoided. It also avoids the problem of chip damage caused by directly powering on for testing without determining whether the chip impedance is normal, as found in related technologies. Therefore, the technical problem of low chip testing efficiency in related technologies can be solved, achieving the effect of improving chip testing efficiency.

[0045] In an optional embodiment, determining whether the impedance of the chip under test is normal based on the set of impedance values ​​includes: determining that the impedance of the chip under test is normal when the impedance values ​​between each pair of pins in the set of N pins all meet the predetermined impedance conditions corresponding to each pair of pins, wherein the set of impedance values ​​includes the impedance values ​​between each pair of pins in the set of N pins, and N is equal to 1, or is a positive integer greater than or equal to 2.

[0046] Optionally, in this embodiment, if there are N pairs of pins in a set of pins of the chip under test (e.g., PIN8, i.e., 8 pins) that need to have their impedance tested, for example, the N pairs of pins can include any two adjacent pins or any two non-adjacent pins. When the impedance values ​​between each pair of pins in the N pairs of pins meet the predetermined impedance conditions, it can be determined that the impedance of the chip under test is normal. For example, the impedance value between two pins that are designed to be short-circuited internally should be zero or close to zero, or the impedance value between a pair of pins that are not inherently short-circuited should be greater than a certain resistance value (e.g., 2kΩ, or other values) or infinity. Through this embodiment, the impedance of the chip under test can be determined by whether the impedance values ​​between each pair of pins in a set of impedance values ​​meet the predetermined impedance conditions corresponding to each pair of pins.

[0047] In an optional embodiment, the method further includes performing the following steps on the i-th pair of pins in the N pairs of pins, where i is a positive integer greater than or equal to 1 and less than or equal to N: if the i-th pair of pins are two pins in the chip under test that have a short-circuit connection, determining whether the impedance value between the i-th pair of pins is 0; if the impedance value between the i-th pair of pins is 0, determining that the impedance value between the i-th pair of pins satisfies the i-th impedance condition corresponding to the i-th pair of pins, wherein the i-th impedance condition means that the impedance value between the i-th pair of pins is 0; or in When the i-th pair of pins are two pins in the chip under test that have a short-circuit connection, it is determined whether the impedance value between the i-th pair of pins is within the i-th predetermined impedance range. If the impedance value between the i-th pair of pins is within the i-th predetermined impedance range, it is determined that the impedance value between the i-th pair of pins satisfies the i-th impedance condition corresponding to the i-th pair of pins. The i-th impedance condition means that the impedance value between the i-th pair of pins is within the i-th predetermined impedance range, and the i-th predetermined impedance range is [0, A), or [0, A], where A is a positive number greater than 0.

[0048] Optionally, in this embodiment, when the i-th pair of pins in the N pairs of pins are two pins in the chip under test that are short-circuited, if the impedance value between the i-th pair of pins is determined to be 0, it can be determined that the impedance value of the i-th pair of pins satisfies the i-th impedance condition corresponding to the i-th pair of pins; or, when the i-th pair of pins in the N pairs of pins are two pins in the chip under test that are short-circuited, if the impedance value between the i-th pair of pins is determined to be within the i-th predetermined impedance range (e.g., 0-100mΩ, or others), it can be determined that the impedance value of the i-th pair of pins satisfies the i-th impedance condition corresponding to the i-th pair of pins. Through this embodiment, the purpose of determining whether the impedance value of the i-th pair of pins in the chip under test that are short-circuited satisfies the corresponding impedance condition is achieved.

[0049] In an optional embodiment, the method further includes performing the following steps on the i-th pair of pins in the N pairs of pins, where i is a positive integer greater than or equal to 1 and less than or equal to N: when the i-th pair of pins are two pins in the chip under test that have an open-circuit connection, determining whether the impedance value between the i-th pair of pins is within the i-th predetermined impedance range; when the impedance value between the i-th pair of pins is within the i-th predetermined impedance range, determining that the impedance value between the i-th pair of pins satisfies the i-th impedance condition corresponding to the i-th pair of pins, where the i-th impedance condition means that the impedance value between the i-th pair of pins is within the i-th predetermined impedance range, and the i-th predetermined impedance range is a positive number greater than A, or, is a positive number greater than or equal to A, or, is [A,B), or, is [A,B], or, is (A,B), or, is (A,B], where A is a positive number greater than 0 and B is a positive number greater than A.

[0050] Optionally, in this embodiment, when the i-th pair of pins in the N pairs of pins are two pins in the chip under test that have an open circuit connection, if the impedance value between the i-th pair of pins is determined to be within the i-th predetermined impedance range (e.g., 1K to 10K, or others), it can be determined that the impedance value of the i-th pair of pins satisfies the i-th impedance condition corresponding to the i-th pair of pins. Through this embodiment, the purpose of determining whether the impedance value of the i-th pair of pins in the chip under test that has an open circuit connection satisfies the corresponding impedance condition is achieved.

[0051] In an optional embodiment, inputting a predetermined voltage signal to the first input pin of the chip under test includes: inputting the predetermined voltage signal to the first input pin of the chip under test through a signal generator, wherein the signal generator is connected to the first input pin through the target fixture.

[0052] Optionally, in this embodiment, a predetermined voltage signal can be input to the first input pin (e.g., VIN, i.e., the input power signal) of the chip under test (DUT) via a signal generator. The predetermined voltage signal can be set according to the testing needs of different DUT chips. For example, the predetermined voltage signal can be a constant voltage signal, a pulse voltage signal, or other signals. The magnitude of the predetermined voltage signal can also be set according to the specific DUT chip. Optionally, while inputting the predetermined voltage signal to the first input pin of the DUT chip, a second predetermined voltage signal can also be input to the second input pin (e.g., the EN terminal, or the enable terminal) of the DUT chip. For example, the second predetermined voltage signal can be a high-level or low-level signal. Through this embodiment, the purpose of inputting a predetermined voltage signal to the DUT chip via a signal generator to test the basic functions of the DUT chip is achieved.

[0053] In an optional embodiment, determining whether the chip under test is abnormal based on the target output signal includes: determining that the chip under test is normal if the voltage value of the target output signal is within a predetermined voltage range, wherein the predetermined voltage range corresponds to the target function, or corresponds to the target function and the predetermined voltage signal; and determining that the chip under test is abnormal if the voltage value of the target output signal is not within the predetermined voltage range.

[0054] Optionally, in this embodiment, when the voltage value of the target output signal is determined to be within a predetermined voltage range, the chip under test (DUT) can be determined to be normal. For example, the predetermined voltage range is 2.4V-3.6V or other voltage ranges. Alternatively, if the ideal output voltage value of the first output pin should be 3V, a voltage range can be set according to the actual situation, such as a fluctuation of 20% (or other) being considered normal. When the voltage value of the target output signal is determined to be outside the predetermined voltage range, the DUT can be determined to be abnormal. The aforementioned predetermined voltage range corresponds to the target function of the DUT, or corresponds to the target function and the predetermined voltage signal. Therefore, based on the target output signal, it can be determined whether the basic function of the DUT is abnormal. Through this embodiment, the purpose of determining whether the basic function of the DUT is abnormal based on the target output signal is achieved.

[0055] In an optional embodiment, detecting the impedance value between the set of pins to obtain a set of impedance values ​​includes: detecting the impedance value between each pair of pins in the N pairs of pins in the set of pins through an impedance detection module to obtain the set of impedance values, wherein the impedance detection module is connected to the target fixture through a target cable, a set of clamps of the target fixture corresponds one-to-one with a set of pins of the chip under test, the target cable includes a wire corresponding to each clamp of the set of clamps of the target fixture, and N is equal to 1, or is a positive integer greater than or equal to 2.

[0056] Optionally, in this embodiment, the impedance detection module can detect the impedance value between each pair of pins in a set of N pins. The impedance detection module can be connected to a target fixture via a target cable. The target fixture includes a set of clamps, and the set of clamps is connected to a set of pins of the chip under test. The target cable includes wires connected to each clamp. For a set of pins of the chip under test (e.g., PIN8, i.e., 8 pins), it may be necessary to test the impedance value between multiple pairs of pins. A pair of pins includes two different pins, such as the impedance value between two adjacent or non-adjacent pins. The wires corresponding to the pair of pins to be tested can be pre-connected to the test terminals of the impedance detection module. Similarly, if multiple pairs of pins need to be tested, the wires corresponding to the multiple pairs of pins to be tested can be pre-connected to the test terminals of the impedance detection module respectively. Optionally, the impedance detection module can detect the impedance value between multiple pairs of pins simultaneously. Through this embodiment, the purpose of detecting the impedance value between each pair of pins in N pairs of pins is achieved by using an impedance detection module.

[0057] In an optional embodiment, the N pairs of pins in the set of pins include: every two adjacent pins in the set of pins, or every two pins in the set of pins.

[0058] Optionally, in this embodiment, N pairs of pins may include every two adjacent pins in a set of pins, or N pairs of pins may include any two pins in a set of pins.

[0059] In an optional embodiment, the method further includes: issuing a target prompt signal when it is determined that the impedance of the chip under test is abnormal, wherein the target prompt signal is used to indicate that the impedance of the chip under test is abnormal.

[0060] Optionally, in this embodiment, when it is determined that the impedance of the chip under test is abnormal, a target prompt signal can be issued to indicate that the impedance of the chip under test is abnormal. For example, the target prompt signal can be an audible prompt signal or a visual prompt signal.

[0061] This embodiment also provides a chip testing device. Figure 3This is a structural block diagram of a chip testing device according to an embodiment of this application, such as... Figure 3 As shown, the device includes:

[0062] The target fixture 302 is configured to connect to a set of pins of the chip under test and clamp the chip under test;

[0063] An impedance detection module 304 is connected to the target fixture. The impedance detection module is configured to detect the impedance value between the set of pins through the target fixture to obtain a set of impedance values.

[0064] The signal generator 306 is connected to the first input pin of the chip under test via the target fixture. The signal generator is configured to input a predetermined voltage signal to the first input pin when the impedance of the chip under test is determined to be normal based on the set of impedance values.

[0065] The chip detection module 308 is configured to acquire the target output signal of the first output pin of the chip under test when the signal generator inputs the predetermined voltage signal to the first input pin of the chip under test, and determine whether the chip under test is abnormal based on the target output signal. The set of pins includes the first input pin and the first output pin, and the target output signal is the signal output by the chip under test after performing the target function when the input voltage signal is the predetermined voltage signal.

[0066] Using the aforementioned device, the target fixture 302 is connected to a set of pins of the chip under test, and the impedance detection module 304 detects the impedance values ​​between the set of pins to obtain a set of impedance values. Based on the set of impedance values, it is determined whether the impedance of the chip under test is normal. When it is determined that the impedance of the chip under test is normal, the signal generator 306 inputs a predetermined voltage signal to the first input pin of the chip under test, and the chip detection module 308 obtains the target output signal of the first output pin of the chip under test. The target output signal is the signal output by the chip under test after performing the target function under the input of the predetermined voltage signal. Then, it is determined whether the chip under test is abnormal based on the target output signal. This invention achieves the goal of conveniently detecting whether the impedance of the chip under test is normal through a target fixture. Furthermore, once the impedance of the chip under test is determined to be normal, a target output signal is obtained by inputting a predetermined voltage signal, and the abnormality of the chip under test is determined based on the target output signal. This avoids the problem of low detection efficiency caused by manual observation or measuring the impedance between pins one by one with a multimeter in related technologies. It also avoids the problem of chip damage that can easily occur when directly powering on the chip for testing without determining whether the chip impedance is normal. Therefore, it solves the technical problem of low chip detection efficiency in related technologies, achieving the effect of improving chip detection efficiency.

[0067] In an optional embodiment, the target fixture includes a set of clamps corresponding to the number of the set of pins; the impedance detection module is connected to the target fixture via a target cable, the target cable including wires corresponding to each clamp in the set of clamps of the target fixture; the signal generator is connected to the first input pin via the target cable.

[0068] Optionally, in this embodiment, the target fixture is used to clamp or fix a set of pins of the chip under test. The target fixture includes a set of clamps, and the set of clamps of the target fixture is connected to a set of pins of the chip under test. The impedance detection module can be connected to the target fixture via a target cable. The target fixture includes a set of clamps, and the set of clamps of the target fixture is connected to a set of pins of the chip under test. The target cable includes wires connected to each clamp. The signal generator can also be connected to the first input pin (e.g., VIN, i.e., the input power signal) of the chip under test via the target cable. Optionally, while inputting a predetermined voltage signal to the first input pin of the chip under test, a second predetermined voltage signal can also be input to the second input pin (e.g., EN terminal, or enable terminal) of the chip under test. In this case, it can also be connected to the second input pin (e.g., VIN, i.e., the input power signal) of the chip under test via the target cable.

[0069] In an optional embodiment, the impedance detection module is connected to the signal generator, and the impedance detection module is configured to send a target start signal to the signal generator when the impedance of the chip under test is determined to be normal based on the set of impedance values. The target start signal is used to instruct the signal generator to input the predetermined voltage signal to the first input pin of the chip under test.

[0070] Optionally, in this embodiment, the impedance detection module is connected to the signal generator. When the impedance of the chip under test is determined to be normal based on a set of impedance values ​​detected by the impedance detection module, the impedance detection module can send a target start signal to the signal generator. That is, the start signal generator inputs a predetermined voltage signal to the first input pin of the chip under test. Of course, if the impedance of the chip under test is determined to be abnormal, the start signal is not sent to the signal generator to avoid the problem that the chip under test may be burned out after power-on.

[0071] In an optional embodiment, the device further includes: a first indicator light configured to emit a first color light when the impedance of the chip under test is determined to be normal based on the set of impedance values, or to emit a second color light when the impedance of the chip under test is determined to be abnormal based on the set of impedance values; and / or a second indicator light configured to illuminate when the voltage value of the target output signal is within a predetermined voltage value range, or not illuminate when the voltage value of the target output signal is outside the predetermined voltage value range, wherein the predetermined voltage value range corresponds to the target function, or corresponds to the target function and the predetermined voltage signal.

[0072] Optionally, in this embodiment, the chip testing device may further include a first indicator light, which is used to indicate whether the impedance value of the chip under test is normal. For example, when the impedance of the chip under test is determined to be normal based on a set of impedance values, the first indicator light may emit a first color light (such as green, or other colors); or, when the impedance of the chip under test is determined to be abnormal based on a set of impedance values, the first indicator light may emit a second color light (such as red, or other colors). Optionally, the chip testing device may further include a second indicator light, which is used to indicate whether the basic function of the chip under test is normal, that is, whether the voltage value of the target output signal is within a predetermined voltage value range. For example, when the voltage value of the target output signal is within a predetermined voltage value range, the second indicator light may light up; or, when the voltage value of the target output signal is not within a predetermined voltage value range, the second indicator light may not light up. In this way, the testing personnel can determine whether the basic function of the chip under test is normal based on the indicator light. Of course, the second indicator light may also adopt a similar method as the first indicator light described above, using light color to indicate whether the voltage value of the target output signal is within a predetermined voltage value range.

[0073] Obviously, the embodiments described above are only some embodiments of the present invention, and not all embodiments. The present invention will be specifically described below with reference to the embodiments.

[0074] This invention provides a chip testing fixture, which includes: (1) a chip clamp, such as... Figure 4 As shown, Figure 4 This is an example diagram of a chip fixture according to an embodiment of this application. The fixture includes a set of clamping feet and a cable is also provided in the fixture, which can be used to perform impedance or power-on tests on the pins of the chip; (2) Control circuit section, such as Figure 5 As shown, the control circuit includes an impedance detection module, a signal generator, an output detection module, etc.

[0075] The working principle of the chip detection fixture in this embodiment will be explained below.

[0076] When open / short circuit testing of a chip is required, a chip fixture is clamped onto the corresponding pins of the chip, receiving different signals from the control circuit board. On the control circuit board, an impedance detection module performs impedance testing on the different pins of the chip. When testing different models or types of chips, corresponding chip fixtures are configured; for example, the number of clamping pins on the chip fixture corresponds one-to-one with the number of pins on the chip itself.

[0077] The impedance detection module mainly consists of an embedded voltage source, a voltage detection unit, and a current detection unit. Voltage and current values ​​are transmitted to the calculation module for resistance calculation and judgment. If the impedance is normal (the impedance of pins with the same function is zero, and the impedance of pins with different functions is between zero and infinity or within a certain impedance range, such as K1 to K2), then the signal generator is triggered, and LED1 (e.g., ...) is activated. Figure 5 As shown, the LED 1 (corresponding to the aforementioned first indicator light) displays a green light. If the impedance is abnormal, it indicates that there is an open circuit or short circuit in the current chip, the signal generator will not start, and LED 1 will display a red light.

[0078] When the impedance is normal, an Enable signal is sent to the signal generator to start it, and voltage pulses are sent to the chip's VIN and EN pins while detecting the chip's output VOUT. The amplitude and shape of the voltage pulses can be manually set according to the chip specifications. If the VOUT output is normal, LED2 (e.g., ...) will activate. Figure 5 As shown, a green light (corresponding to the aforementioned second indicator light) indicates that the chip is currently soldered well and its basic functions are normal. Specific Implementation Example 1

[0080] The following example uses the power supply chip TPS82130. Figure 6 The following is a chip example diagram based on an embodiment of this application, which illustrates specific implementations of the present invention:

[0081] 1) Due to certain reasons, the TPS82130 on a certain board was re-soldered;

[0082] 2) The TPS82130 contains 8 pins (corresponding to the aforementioned set of pins) and is designed for 8-pin chip fixtures;

[0083] 3) Clamp the fixture onto the 8 pins of the chip;

[0084] 4) The control circuit board first performs impedance detection on it, detecting the impedance between 1-2, 2-3, 3-4, 4-5, 5-6, 6-7, and 7-8 (corresponding to the aforementioned set of impedance values);

[0085] 5) The measured impedance is normal, LED1 is green, and the EN signal generator is high;

[0086] 6) The signal generator sends voltage pulses higher than the threshold to VIN and EN of the TPS82130;

[0087] 7) When VOUT is detected to have a corresponding output, LED2 lights up green, indicating that the TPS82130 is not open or short-circuited and its basic functions are normal.

[0088] In the above embodiment, the testing fixture consists of a control circuit board and a chip fixture. The chip fixture is manufactured according to common chip types on the market, including 4-pin, 6-pin, and 8-pin types, and can be replaced according to the package of the chip to be tested. The control circuit board performs impedance testing and basic single-chip function testing on the chip through the fixture. After the impedance test is normal, LED1 (green light) lights up, and a signal generator sends voltage pulses to the input and enable pins to check if the output is normal. If it is normal, LED2 (green light) lights up.

[0089] The above embodiments provide a portable chip open / short circuit detection fixture. This fixture consists of a control circuit board and a chip clamp. The control circuit board performs impedance detection and basic single-chip function testing on the chip through the clamp. After normal impedance detection, a green LED illuminates, and a signal generator sends voltage pulses to the input and enable pins to check if the output is normal. If normal, a second green LED illuminates. This fixture allows for open / short circuit testing of chips anytime, anywhere, significantly saving time and manpower costs in chip measurement, improving the reliability and effectiveness of testing, and preventing device burnout or even board damage due to poor chip soldering or inherent malfunctions, thus reducing risks and economic losses.

[0090] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solutions of the embodiments of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0091] This embodiment also provides a chip detection device. Figure 7 This is a structural block diagram of a chip detection device according to an embodiment of this application, such as... Figure 7 As shown, the device includes:

[0092] The detection unit 702 is used to detect the impedance value between a set of pins of the target fixture and the chip under test, and obtain a set of impedance values.

[0093] The first determining unit 704 is used to determine whether the impedance of the chip under test is normal based on the set of impedance values.

[0094] The processing unit 706 is configured to, when it is determined that the impedance of the chip under test is normal, input a predetermined voltage signal to the first input pin of the chip under test and obtain a target output signal of the first output pin of the chip under test, wherein the set of pins includes the first input pin and the first output pin, and the target output signal is the signal output by the chip under test after performing the target function when the input voltage signal is the predetermined voltage signal;

[0095] The second determining unit 708 is used to determine whether the chip under test is abnormal based on the target output signal.

[0096] It should be noted that the above-mentioned units or modules can be implemented by software or hardware. For the latter, they can be implemented in the following ways, but not limited to these: all the above-mentioned units or modules are located in the same processor; or, the above-mentioned units or modules are located in different processors in any combination.

[0097] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above method embodiments when run.

[0098] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0099] Embodiments of this application also provide an electronic device including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0100] In one exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor and the input / output device is connected to the processor.

[0101] Specific examples in this embodiment can be found in the examples described in the above embodiments and exemplary implementations, and will not be repeated here.

[0102] Obviously, those skilled in the art should understand that the modules or steps of the embodiments of this application described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. They can be implemented using computer-executable program code, and thus can be stored in a storage device for execution by a computing device. In some cases, the steps shown or described can be performed in a different order than those presented here, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, the embodiments of this application are not limited to any particular combination of hardware and software.

[0103] The above description is merely a preferred embodiment of this application and is not intended to limit the embodiments of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the principles of the embodiments of this application should be included within the protection scope of the embodiments of this application.

Claims

1. A chip detection method, characterized in that, include: With the target fixture and a set of pins of the chip under test already connected, the impedance value between the set of pins is detected to obtain a set of impedance values; Based on the set of impedance values, determine whether the impedance of the chip under test is normal; When it is determined that the impedance of the chip under test is normal, a predetermined voltage signal is input to the first input pin of the chip under test, and the target output signal of the first output pin of the chip under test is obtained. The set of pins includes the first input pin and the first output pin. The target output signal is the signal output by the chip under test after performing the target function when the input voltage signal is the predetermined voltage signal. The test chip is determined to be malfunctioning based on the target output signal.

2. The method according to claim 1, characterized in that, The step of determining whether the impedance of the chip under test is normal based on the set of impedance values ​​includes: If the impedance values ​​between each pair of pins in the N pairs of pins in the set of pins all meet the predetermined impedance conditions corresponding to each pair of pins, it is determined that the impedance of the chip under test is normal. The set of impedance values ​​includes the impedance values ​​between each pair of pins in the N pairs of pins, where N is equal to 1, or is a positive integer greater than or equal to 2.

3. The method according to claim 2, characterized in that, The method further includes: Perform the following steps on the i-th pair of pins in the N pairs, where i is a positive integer greater than or equal to 1 and less than or equal to N: If the i-th pair of pins are two pins in the chip under test that have a short-circuit connection, determine whether the impedance value between the i-th pair of pins is 0. If the impedance value between the i-th pair of pins is 0, determine that the impedance value between the i-th pair of pins satisfies the i-th impedance condition corresponding to the i-th pair of pins, where the i-th impedance condition means that the impedance value between the i-th pair of pins is 0; or When the i-th pair of pins are two pins in the chip under test that have a short-circuit connection, it is determined whether the impedance value between the i-th pair of pins is within the i-th predetermined impedance range. If the impedance value between the i-th pair of pins is within the i-th predetermined impedance range, it is determined that the impedance value between the i-th pair of pins satisfies the i-th impedance condition corresponding to the i-th pair of pins. The i-th impedance condition means that the impedance value between the i-th pair of pins is within the i-th predetermined impedance range, and the i-th predetermined impedance range is [0, A1), or [0, A1], where A1 is a positive number greater than 0.

4. The method according to claim 2, characterized in that, The method further includes: Perform the following steps on the i-th pair of pins in the N pairs, where i is a positive integer greater than or equal to 1 and less than or equal to N: When the i-th pair of pins are two pins in the chip under test that have an open-circuit connection, it is determined whether the impedance value between the i-th pair of pins is within the i-th predetermined impedance range. If the impedance value between the i-th pair of pins is within the i-th predetermined impedance range, it is determined that the impedance value between the i-th pair of pins satisfies the i-th impedance condition corresponding to the i-th pair of pins. The i-th impedance condition means that the impedance value between the i-th pair of pins is within the i-th predetermined impedance range. The i-th predetermined impedance range is a positive number greater than A2, or, is a positive number greater than or equal to A2, or, is [A2, B), or, is [A2, B], or, is (A2, B), or, is (A2, B], where A2 is a positive number greater than 0 and B is a positive number greater than A2.

5. The method according to claim 1, characterized in that, The step of inputting a predetermined voltage signal to the first input pin of the chip under test includes: The predetermined voltage signal is input to the first input pin of the chip under test through a signal generator, wherein the signal generator is connected to the first input pin through the target fixture.

6. The method according to claim 1, characterized in that, The step of determining whether the chip under test is abnormal based on the target output signal includes: If the voltage value of the target output signal is determined to be within a predetermined voltage range, the chip under test is determined to be normal. The predetermined voltage range corresponds to the target function, or corresponds to the target function and the predetermined voltage signal. If the voltage value of the target output signal is determined to be outside the predetermined voltage range, the chip under test is determined to be abnormal.

7. The method according to claim 1, characterized in that, The process of detecting the impedance values ​​between the set of pins to obtain a set of impedance values ​​includes: The impedance value is obtained by detecting the impedance value between each pair of pins in the N pairs of pins in the set of pins through the impedance detection module. The impedance detection module is connected to the target fixture through the target cable. A set of clamps of the target fixture corresponds one-to-one with a set of pins of the chip under test. The target cable includes wires corresponding to each clamp of the set of clamps of the target fixture. N is equal to 1, or is a positive integer greater than or equal to 2.

8. The method according to claim 2 or 7, characterized in that, The N pairs of pins in the set of pins include: each two adjacent pins in the set of pins, or each two pins in the set of pins.

9. The method according to any one of claims 1 to 7, characterized in that, The method further includes: If the impedance of the chip under test is determined to be abnormal, a target prompt signal is issued, wherein the target prompt signal is used to indicate that the impedance of the chip under test is abnormal.

10. A chip testing device, characterized in that, include: The target fixture is configured to connect to a set of pins of the chip under test and clamp the chip under test; An impedance detection module is connected to the target fixture. The impedance detection module is configured to detect the impedance value between the set of pins through the target fixture to obtain a set of impedance values. A signal generator is connected to the first input pin of the chip under test via the target fixture. The signal generator is configured to input a predetermined voltage signal to the first input pin when the impedance of the chip under test is determined to be normal based on the set of impedance values. The chip detection module is configured to acquire the target output signal of the first output pin of the chip under test when the signal generator inputs the predetermined voltage signal to the first input pin of the chip under test, and determine whether the chip under test is abnormal based on the target output signal. The set of pins includes the first input pin and the first output pin, and the target output signal is the signal output by the chip under test after performing the target function when the input voltage signal is the predetermined voltage signal.

11. The device according to claim 10, characterized in that, The target fixture includes a set of clamping feet corresponding to the number of the set of pins; The impedance detection module is connected to the target fixture via a target cable, the target cable including a wire corresponding to each of the clamps in a set of clamps of the target fixture; The signal generator is connected to the first input pin via the target cable.

12. The device according to claim 10, characterized in that, The impedance detection module is connected to the signal generator. The impedance detection module is configured to send a target start signal to the signal generator when the impedance of the chip under test is determined to be normal based on the set of impedance values. The target start signal is used to instruct the signal generator to input the predetermined voltage signal to the first input pin of the chip under test.

13. The device according to any one of claims 10 to 12, characterized in that, The device also includes: The first indicator light is configured to emit a first-color light when the impedance of the chip under test is determined to be normal based on the set of impedance values, or to emit a second-color light when the impedance of the chip under test is determined to be abnormal based on the set of impedance values; and / or The second indicator light is configured to illuminate when the voltage value of the target output signal is within a predetermined voltage range, or not illuminate when the voltage value of the target output signal is outside the predetermined voltage range, wherein the predetermined voltage range corresponds to the target function, or corresponds to both the target function and the predetermined voltage signal.

14. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the method described in any one of claims 1 to 9.

15. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method described in any one of claims 1 to 9.

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