Multiresolution cache

Abstract

A multi-resolution cache includes a first cache segment, a second cache segment, and a third cache segment, the first segment having a first resolution and the second and third cache segments having a second resolution, the second resolution being less than the first resolution, the first and third cache segments being communicatively coupled to an off-chip memory, the first and third cache segments being configured to receive data of cache lines having the first and second resolutions; a fourth cache segment and a fifth cache segment, the fourth and fifth cache segments having the second resolution; a first resolution reducer communicatively coupled to the first and fourth cache segments and configured to reduce the resolution when a cache data line of the first resolution is shifted from the first cache segment to the fourth cache segment; a first resolution elevator communicatively coupled to all cache segments having a second resolution and configured to elevate a reduced resolution cache data to a first resolution and output it.

Description

Technical Field

[0001] The present invention relates to a multi-resolution cache. Background Art

[0002] Image processing operations, such as spatial filtering and motion-compensated frame interpolation (MCFI) (also known as motion estimation and compensation or MEMC), are performed on local image neighborhoods, e.g., local neighborhoods in the spatial domain. Typically, an image data cache is used to reduce memory access bandwidth, reading image data from memory only once and providing access to the local neighborhood from the cached data. Therefore, a larger neighborhood means a larger cache size, and thus a higher cache cost. Summary of the Invention

[0003] In one aspect, a multi-resolution cache comprises a first cache segment (102), a second cache segment (108), and a third cache segment (110) having a first resolution, a second resolution, and a third resolution, respectively; the second resolution is smaller than the first resolution, and the third resolution is smaller than the second resolution, the first cache segment (102), the second cache segment (108), and the third cache segment (110) being communicatively coupled to an off-chip memory (120); the first cache segment (102), the second cache segment (108), and the third cache segment (110) being configured to receive one cache line of (image) data having the first resolution, the second resolution, and the third resolution from the off-chip memory (i.e., located outside the cache, such as DDRRAM, a (cached) video stream, etc.); the fourth cache segment (106) and the fifth cache segment (104) having the second resolution and the third resolution, respectively; a first resolution reducer (114) being communicatively coupled to the first cache segment The invention relates to a first cache segment (102) and a fourth cache segment (106) configured to reduce the resolution of a first resolution cache line when the first resolution cache line is shifted from the first cache segment (102) to the fourth cache segment (106); a second resolution reducer (112) communicatively coupled to the fourth cache segment (106) and the fifth cache segment (104) and configured to further reduce the resolution of the cache line when the reduced resolution cache line is shifted from the fourth cache segment (106) to the fifth cache segment (104) The first resolution enhancer (118) and the second resolution enhancer (116) are communicatively coupled to the second cache segment (108) and the third cache segment (110), respectively, and are also communicatively coupled to the fourth cache segment (106) and the fifth cache segment (104), respectively, and are configured to enhance the reduced-resolution cache data and the further reduced-resolution buffered data to the first resolution and output the enhanced-resolution cache data. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] To easily identify the discussion of any particular element or act, the most significant digit(s) in a reference number refers to the drawing number in which the element is first introduced.

[0005] Figure 1 A multi-resolution cache is shown according to one embodiment.

[0006] Figure 2 A multi-resolution cache is shown according to one embodiment.

[0007] Figure 3 A multi-resolution cache is shown according to one embodiment.

[0008] Figure 4 A multi-resolution cache is shown according to one embodiment.

[0009] Figure 5 A multi-resolution cache is shown according to one embodiment.

[0010] Figure 6 A multi-resolution cache is shown according to one embodiment.

[0011] Figure 7 A method according to one embodiment is shown.

[0012] Description of reference numerals:

[0013] Multi-resolution cache 100;

[0014] Cache segments 102, 104, 106, 108, 110

[0015] resolution reducers 114, 112;

[0016] resolution enhancers 116, 118;

[0017] Off-chip memory 120;

[0018] Multi-resolution cache 200;

[0019] cache segments 202, 206, 208, 210, 212;

[0020] resolution reducer 204;

[0021] Multi-resolution cache 300;

[0022] Off-chip memory 306;

[0023] cache segments 302, 304, 308, 310, 312, 314;

[0024] resolution enhancer 316;

[0025] Multi-resolution cache 400;

[0026] cache segments 402, 404, 406, 408, 410;

[0027] resolution reducers 412, 414;

[0028] resolution enhancers 418, 420;

[0029] Off-chip memory 416;

[0030] Multi-resolution cache 500;

[0031] Full resolution cache segment 502;

[0032] Half-resolution cache segment 504;

[0033] quarter-resolution cache segments 506, 510;

[0034] Half-resolution cache segment 508;

[0035] Off-chip memory 516;

[0036] resolution reducers 512, 514;

[0037] resolution enhancers 518, 520;

[0038] Multi-resolution cache 600;

[0039] Full resolution cache segment 602;

[0040] half-resolution cache segments 604, 606, 608;

[0041] quarter resolution cache segment 610;

[0042] resolution reducers 612, 614;

[0043] resolution enhancers 618, 620;

[0044] Off-chip memory 616;

[0045] Method 700;

[0046] Boxes 702, 704, 706, 708, 710, 712, 714, 716. DETAILED DESCRIPTION

[0047] Several embodiments use a multi-resolution cache, whereby a portion of the cache contains images having a higher (e.g., full) resolution and another portion of the cache contains images having a lower resolution. In this way, the same cache size can provide access to a larger neighborhood area than a single-resolution cache, or in other words, a lower cache size is required for the same neighborhood size.

[0048] The cache system may generate lower resolution data from the higher resolution data if higher resolution data is available in cache, and read the lower resolution data from memory when higher resolution data is not available in cache.

[0049] The cache system provides data at the highest available resolution, or it provides a blend of the two resolutions where the two cache resolution segments overlap or transition.

[0050] Image processing functions (e.g., spatial or spatiotemporal) can often benefit from a larger size of the local neighborhood (filter aperture size). Embodiments can achieve better image processing results by increasing the aperture size, thereby providing data for pixels farther from the center pixel at a reduced resolution rather than the resolution of the original image data (located in memory).

[0051] A practical example of an application that can benefit from a larger aperture despite a reduction in resolution is MCFI. In MCFI, intermediate frames are generated between the original video frames, for example, converting 24 frames per second (fps) film to 120fps film. MCFI needs to extract image pixels from adjacent input frames along the motion trajectory, for which a spatial aperture is required at each input frame. The available local neighborhood (aperture) size defines the maximum amount of motion that can be correctly compensated before interpolation. For example, if the vertically available aperture size is 101 lines centered at the current pixel position, objects with up to + / - 50 vertical lines of motion from the input frame to the output frame can be correctly interpolated, while objects with larger vertical motion will produce incorrect interpolation results. If we provide pixels with an aperture of more than 101 lines at a lower resolution, MCFI can correctly perform motion compensation, albeit at a lower output resolution.

[0052] Thus, embodiments provide a system for storing image data at multiple resolutions in a cache and providing access to the image data, thereby reducing the cache size for the same access range compared to a single-resolution cache mechanism, or in other words, providing a larger access range for the same cache size compared to a single-resolution cache mechanism.

[0053] The multi-resolution cache system includes:

[0054] 1. At least 2 cache segments, one of which is used to store images at a high resolution and one or more of which is used to store images at a lower resolution, whereby the different resolution segments may optionally partially or completely overlap each other.

[0055] 2. A mechanism for filling a cache with (image) data whereby a given amount of old data (e.g. one image line) is removed from the cache, the data in the cache is shifted by a given amount (note that shifted does not necessarily mean physically, confirmation is conceptual, e.g. using data pointers), and the given amount of new data is written to the cache, whereby lower resolution data for a lower resolution cache segment is generated using higher resolution data available in the cache or read from memory (e.g. by reducing the resolution of available adjacent high resolution pixel data), and data is only read from memory for cases where no higher resolution version is available in the cache.

[0056] 3. A mechanism to access (read) data at a desired (image) location from a cache, whereby:

[0057] If the data location is available in the high-resolution cache segment but not in the low-resolution segment, the high-resolution data is returned.

[0058] If no data location is available in the high-resolution cache segment but data exists in the low-resolution cache segment, an approximation of the data is calculated and returned using the low-resolution data, such as by interpolating data from immediate neighbors in the low-resolution cache segment (raising the resolution).

[0059] If the data location is located in an area where two resolution segments overlap or transition, a "blend" of (1) data from the high-resolution cache segment and (2) data from the low-resolution cache segment may be returned, such that the blend ratio is, for example, proportional to the distance of the data location from the two resolution segments. This mechanism ensures that output data in areas of resolution overlap or transition transitions sharply from one resolution to the other, but fades gradually between the two resolutions.

[0060] For example, the "blending" operation can be implemented, for example, by "interpolation," so that as the pixel distance D1 from segment 1 decreases, the returned pixel value Pout approaches the pixel value P1, and as the pixel distance D2 from segment 2 decreases, the returned pixel value Pout approaches the pixel value P2 from segment 2. For example, when "linear interpolation" is used, the above operation can be implemented as Pout = (P1*D2+P2*D1) / (D1+D2).

[0061] o Alternatively, "blend" may return the highest resolution available in the overlapping area, rather than the smooth transition described above.

[0062] Figure 1A multi-resolution cache 100 according to one embodiment is shown. The multi-resolution cache 100 includes a full-resolution cache segment 102, a half-resolution segment 106, and a half-resolution segment 108, and a quarter-resolution cache segment 104 and a quarter-resolution cache segment 110 arranged vertically symmetrically. The half-resolution cache segment 106 and the half-resolution cache segment 108 are arranged vertically above and below the full-resolution cache segment 102, respectively. The quarter-resolution cache segment 104 and the quarter-resolution cache segment 110 are arranged vertically above and below the half-resolution cache segment 106 and the half-resolution cache segment 108, respectively. The multi-resolution cache 100 also includes a resolution reducer 114 and a resolution reducer 112 that respectively reduce the resolution (e.g., using a bilinear resolution reducer) by 50% from the full-resolution cache segment 102 to the half-resolution cache segment 106, and further reduce the resolution by 50% from the half-resolution cache segment 106 to the quarter-resolution cache segment 104. A 4X upscaling 116 and a 2X upscaling 118 upscale the resolution from the quarter-resolution and half-resolution cache segments 104 and 110, respectively, to the full resolution (e.g., by using bilinear interpolation or other interpolation algorithms) for the outputs from the quarter-resolution cache segments 104 and 110, and the half-resolution cache segments 106 and 108, respectively.

[0063] In the multi-resolution cache 100, the size of a full-resolution segment is C = H * W (where H represents height and W represents width), the size of a half-resolution segment is C / 4 = (H / 2) * (W / 2), and the size of a quarter-resolution segment is C / 16 = (H / 4) * (W / 4). Therefore, the total cache size is 1.625 * C data elements (1.625 = 1 + 2 * (quarter) + 2 * (1 / 16)).

[0064] Assuming a top-to-bottom image row scan direction, the multi-resolution cache 100 may be filled as follows.

[0065] At each new full resolution image row, the data of the full resolution cache segment is shifted up by one row and a new row of full resolution (image) data is read from the off-chip memory 120 and written at the empty (shifted) row of the full resolution cache segment 102.

[0066] At each new half-resolution image line, Figure 1 The data in the bottom half-resolution cache segment 108 is shifted up one row, and a new half-resolution (image) row of data is read from the off-chip memory 120 and written to the Figure 1At the empty (shifted) line of the bottom half-resolution cache segment 108 .

[0067] At each new quarter-resolution image row, Figure 1 The data of the quarter resolution cache segment 110 at the bottom is shifted up one row, and a new row of quarter resolution (image) data is read from the off-chip memory 120 and written to the Figure 1 At the empty (shifted) line of the bottom quarter-resolution height cache segment 110 .

[0068] At each new half-resolution image line, Figure 1 The data in the top half-resolution cache segment 106 is shifted by one row, and a new half-resolution (image) data row is generated by using the data cached in the full-resolution cache segment 102 (e.g., reduced in resolution using the resolution reducer 114) and written to the Figure 1 At the empty (shifted) line of the top half-resolution cache segment 106 .

[0069] At each new quarter-resolution image row, Figure 1 The data of the top quarter resolution cache segment 104 is shifted by one row and is used Figure 1 The data cached in the top half-resolution cache segment 106 is reduced in resolution (e.g., using the resolution reducer 112) to generate a new quarter-resolution (image) data line and written to the Figure 1 At the empty (shifted) line of the top quarter-resolution cache segment 104 .

[0070] Thus, in the multi-resolution cache 100, processing the entire image only requires reading the image data at each of the three resolutions (full resolution, half resolution, and quarter resolution) once, as shown in FIG. Figure 1 As shown in , it is represented by "Total memory read: 1.3125*F" (1+one quarter + 1 / 16=1.3125), where F identifies the size of the image frame.

[0071] In summary, the multi-resolution cache 100 provides cached data access at 3 resolutions at a cost of 1.625*C cache cells and 1.3125*F of memory bandwidth.

[0072] If the scanning direction is not top to bottom, but bottom to top, left to right or right to left, the order of shifting cache data and filling empty data rows (or columns) is adjusted accordingly to achieve an equivalent mechanism of the cache filling mechanism explained above, but in a mirrored or circular order.

[0073] When accessing data cached in low resolution cache segments 104 and 106, where the data in the segment is stored at a reduced spatial resolution, adjacent low resolution data may be used to generate an approximation of the data at the requested location, for example using 2D spatial interpolation.

[0074] As will be discussed in the following examples, note that:

[0075] • Cache can have 2 or more levels.

[0076] The stack can be implemented horizontally or vertically.

[0077] • The data reduction factor (eg spatial resolution reduction factor) can be dynamically selected based on the required access range and available cache size.

[0078] • The horizontal and vertical data reduction of each resolution level (eg spatial resolution reduction level) may be equal or may be different from each other.

[0079] • The cache does not need to be positioned symmetrically around the current pixel position, but can be arranged with a (horizontal and / or vertical) offset relative to the current pixel position (so-called skewed positioning of the cache).

[0080] The allocation of cache data to each resolution level can be done dynamically and in a non-equal manner. For example, a larger amount of cache size can be allocated to the bottom cache segment when needed compared to the top cache segment.

[0081] Figure 2A multi-resolution cache 200 according to one embodiment is shown. Multi-resolution cache 200 includes a full-resolution cache segment 202, a resolution reducer 204, a half-resolution cache segment 206, a half-resolution cache segment 208, a half-resolution cache segment 210, a half-resolution cache segment 212, and a resolution increaser. Off-chip memory 214 is communicatively coupled to full-resolution cache segment 202 and half-resolution cache segment 210. Multi-resolution cache 200 operates in a manner similar to multi-resolution cache 100, except that there are no quarter-resolution cache segments. Therefore, only a single resolution reduction operation is required to generate half-resolution data for populating cache segment 206 from the full-resolution data available in cache segment 202. The half-resolution data for populating cache segment 210 is read from memory. As shown, multi-resolution cache 200 has symmetrical top / bottom resolution segments (a resolution reduction operation is required to generate half-resolution data from the full-resolution data available in the cache). The required cache size is 2*C and the required memory read bandwidth is 1.25*F.

[0082] In one embodiment, cache segments 210 and 212 below full-resolution cache segment 202 are effectively unified to form what appears to be a single segment, and cache segments 206 and 208 above full-resolution cache segment 202 are effectively unified to form what appears to be another single segment. That is, there are only three segments: a full-resolution segment and two half-resolution (or other resolution) segments.

[0083] Figure 3 A multi-resolution cache 300 according to one embodiment is shown. Multi-resolution cache 300 operates in a manner similar to multi-resolution cache 200, except that full-resolution cache segment 302 completely overlaps half-resolution cache segment 304, eliminating the need for resolution reduction. Specifically, multi-resolution cache 300 includes full-resolution cache segment 302, half-resolution cache segment 304, half-resolution cache segment 308, half-resolution cache segment 310, half-resolution cache segment 312, half-resolution cache segment 314, and a resolution upscaling device 316. Off-chip memory 306 is communicatively coupled to full-resolution cache segment 302 and half-resolution cache segment 314. The required cache size is 2.25*C, and the required memory read bandwidth is 1.25*F.

[0084] Figure 4A multi-resolution cache 400 is shown according to one embodiment. The multi-resolution cache 400 includes a full-resolution cache segment 402, a full-resolution cache segment 404, a full-resolution cache segment 406, a half-resolution cache segment 408, a quarter-resolution cache segment 410, a resolution downsizer 412, a resolution downsizer 414, a resolution upsizer 418, and a resolution upsizer 420. An off-chip memory 416 is communicatively coupled to the full-resolution cache segment 402.

[0085] Multi-resolution cache 400, like multi-resolution cache 100, has three resolutions, but with asymmetric top / bottom resolution segments. Two resolution reduction operations are required to generate half-resolution data from the full-resolution data available in full-resolution cache segment 406, and to generate quarter-resolution data from the half-resolution data available in half-resolution cache segment 408. Using three full-resolution levels in the bottom half of the cache stack eliminates the need to read multiple image resolutions from memory; only a single (full) resolution image needs to be read from memory. The required cache size is 3.3125*C, and the required memory read bandwidth is 1*F.

[0086] Figure 5 1 shows a multi-resolution cache 500 according to one embodiment. The multi-resolution cache 500 is connected to a full-resolution cache segment 502, a half-resolution cache segment 504, a quarter-resolution cache segment 506, a half-resolution cache segment 508, a quarter-resolution cache segment 510, a resolution reducer 512, a resolution reducer 514, a resolution upscaling 518, and a resolution upscaling 520. However, the current pixel row is tilted upward in this example (i.e., the current pixel row need not be centered in the middle of the full-resolution cache segment 502). An off-chip memory 516 is communicatively coupled to the full-resolution cache segment 502 and the quarter-resolution cache segment 506.

[0087] Figure 61 shows a multi-resolution cache 600 according to one embodiment. In this embodiment, the sizes of all cache segments are dynamically allocated. Multi-resolution cache 600 includes a full-resolution cache segment 602, a half-resolution cache segment 604, a half-resolution cache segment 606, a half-resolution cache segment 608, a quarter-resolution cache segment 610, a resolution reducer 612, a resolution reducer 614, a resolution upscaling 618, and a resolution upscaling 620. Full-resolution cache segment 602, half-resolution cache segment 604, and half-resolution cache segment 606 are communicatively coupled to an off-chip memory 616.

[0088] Multi-resolution cache 600 operates in a manner similar to multi-resolution cache 500, where the current pixel row is tilted upward in this example (i.e., the current pixel row need not be centered in the middle of full-resolution cache segment 602), except that cache data is distributed unequally at the top and bottom of full-resolution cache segment 602 (more cache data is allocated to the bottom and less to the top, which can be performed dynamically).

[0089] In its most basic embodiment, a multi-resolution cache system comprises two segments, each having a different resolution, whereby the higher resolution cache segment obtains its contents from off-chip memory and the lower resolution cache segment obtains its contents from off-chip memory if the content is not available in the higher resolution segment, or obtains its contents by reducing the resolution of the higher resolution segment if the content is available in the higher resolution segment.

[0090] Figure 7Method 700 according to one embodiment is shown. Any cache described herein can perform method 700. In block 702, a multi-resolution cache reads a cache line of data at full resolution from an off-chip memory. In block 704, the multi-resolution cache stores the read data in a first full-resolution cache segment of the cache. In block 706, the multi-resolution cache downscales the read data to a resolution lower than full resolution as the data is shifted out of the full-resolution cache. In block 708, the multi-resolution cache shifts the downscaled data to a first low-resolution cache segment of the cache. In block 710, the multi-resolution cache reads a second cache line of data at full resolution from the off-chip memory. In block 712, the multi-resolution cache stores the read second cache line of data in the first full-resolution cache segment. In block 714, the multi-resolution cache upscales the downscaled data to full resolution. In block 716, the multi-resolution cache outputs the upscaled data (e.g., for display or other purposes).

[0091] The following examples describe various embodiments of the methods, computer-readable media, and systems (eg, machines, apparatuses, or other devices) discussed herein.

[0092] 1. A multi-resolution cache comprising:

[0093] a first cache segment, a second cache segment, and a third cache segment, the first cache segment, the second cache segment, and the third cache segment having a first resolution, a second resolution, and a third resolution, respectively, the second resolution being smaller than the first resolution and the third resolution being smaller than the second resolution, the first cache segment, the second cache segment, and the third cache segment being communicatively coupled to an off-chip memory, the first cache segment, the second cache segment, and the third cache segment being configured to receive cache lines of data having the first resolution, the second resolution, and the third resolution;

[0094] a fourth cache segment and a fifth cache segment, the fourth cache segment and the fifth cache segment having the second resolution and the third resolution, respectively;

[0095] a first resolution reducer communicatively coupled to the first cache segment and a fourth cache segment and configured to reduce the resolution when the resolution cache line is shifted from the first cache segment to the fourth cache segment;

[0096] a second resolution reducer communicatively coupled to the fourth cache segment and the fifth cache segment and configured to further reduce a resolution of the reduced-resolution cache data line as the reduced-resolution cache data line is shifted from the fourth cache segment to the fifth cache segment;

[0097] A first resolution upscaling device and a second resolution upscaling device are communicatively coupled to the second cache segment and the third cache segment, respectively, and are also communicatively coupled to the fourth cache segment and the fifth cache segment, respectively, and are configured to upscale the reduced-resolution cache data and the further reduced-resolution buffered data to the first resolution and output the upscaled-resolution cache data.

[0098] 2. The multi-resolution cache of example 1, wherein the second resolution is half the first resolution, and the third resolution is one quarter the first resolution.

[0099] 3. The multi-resolution cache of any preceding example, wherein the first resolution is full resolution.

[0100] 4. The multi-resolution cache of any of the preceding examples, wherein the second cache segment, the third cache segment, the fourth cache segment, and the fifth cache segment are arranged in a symmetrical configuration around the first cache segment.

[0101] 5. The multi-resolution cache of any preceding example, wherein the cache data allocation of the second cache segment is not equal to the cache data allocation of the fourth cache segment.

[0102] 6. The multi-resolution cache of any of the preceding examples, wherein cache data size allocations and resolutions of all cache segments are dynamically or unequally allocated, such that the downconverter is adjusted accordingly to generate a reduced resolution target resolution from a data source resolution.

[0103] 7. The multi-resolution cache of any preceding example, wherein the current pixel row is not centered in the first cache segment.

[0104] 8. The multi-resolution cache of any preceding example, further comprising a sixth cache segment having a resolution less than the first resolution and overlapping the first cache segment.

[0105] 9. A method of operating a multi-resolution cache according to any of the preceding examples, comprising:

[0106] Reading data of one cache line at full resolution from the off-chip memory;

[0107] storing the read data in the first cache segment of the cache;

[0108] reducing the resolution of the data of the first cache segment to a resolution lower than the full resolution;

[0109] shifting reduced-resolution data to said fourth cache segment of said cache;

[0110] reading data of a second cache line at full resolution from the off-chip memory;

[0111] storing the read data of the second cache line in the first cache segment;

[0112] Upscaling the reduced resolution data to the full resolution; and

[0113] Outputs data with increased resolution.

[0114] 10. A multi-resolution cache comprising:

[0115] a first cache segment, a second cache segment, and a third cache segment, the first cache segment having a first resolution and the second cache segment and the third cache segment having a second resolution, the second resolution being less than the first resolution, the first cache segment and the third cache segment being communicatively coupled to an off-chip memory, the first cache segment and the third cache segment being configured to receive cache lines of data having the first resolution and the second resolution;

[0116] a fourth cache segment and a fifth cache segment, the fourth cache segment and the fifth cache segment having the second resolution;

[0117] a first resolution reducer communicatively coupled to the first cache segment and a fourth cache segment and configured to reduce the resolution when a cache data line at the first resolution is shifted from the first cache segment to the fourth cache segment;

[0118] A first resolution upscaling device is communicatively coupled to the fourth cache segment and the fifth cache segment and is configured to upscale the reduced-resolution cache data to the first resolution and output the upscaled-resolution cache data.

[0119] 11. The multi-resolution cache of any of the preceding examples, wherein the second cache segment is configured to receive cached data having the second resolution from the third cache segment when data is shifted from the third cache segment to the second cache segment.

[0120] 12. The multi-resolution cache of any preceding example, wherein the second resolution is half the first resolution.

[0121] 13. The multi-resolution cache of any of the preceding examples, wherein the second cache segment, the third cache segment, the fourth cache segment, and the fifth cache segment are arranged in a symmetrical configuration around the first cache segment.

[0122] 14. The multi-resolution cache of any preceding example, wherein cache data distribution across all cache segments is unequal.

[0123] 15. The multi-resolution cache of any preceding example, further comprising a sixth cache segment having a resolution less than the first resolution and overlapping the first cache segment.

[0124] 16. A multi-resolution cache comprising:

[0125] a first cache segment, a second cache segment, and a third cache segment, the first cache segment, the second cache segment, and the third cache segment having a first resolution, the first cache segment being communicatively coupled to an off-chip memory, the first cache segment being configured to receive cache lines of data having the first resolution;

[0126] a fourth cache segment and a fifth cache segment, the fourth cache segment and the fifth cache segment having a second resolution and a third resolution, respectively, the second resolution being smaller than the first resolution and the third resolution being smaller than the second resolution;

[0127] a first resolution reducer communicatively coupled to the fourth cache segment and configured to reduce the resolution of a cache line of a first resolution when the cache line is shifted from the third cache segment to the fourth cache segment;

[0128] a second resolution reducer communicatively coupled to the fourth cache segment and the fifth cache segment and configured to further reduce the resolution of the reduced-resolution cache data line as the reduced-resolution cache data line is shifted from the fourth cache segment to the fifth cache segment; and

[0129] A first resolution upscaling device and a second resolution upscaling device are communicatively coupled to the fourth cache segment and the fifth cache segment, respectively, and are configured to upscale the reduced-resolution cache data and the further reduced-rate cache data to the first resolution and output the upscaled-resolution cache data.

[0130] 17. The multi-resolution cache of any preceding example, wherein the second resolution is half the first resolution, and the third resolution is one quarter the first resolution.

[0131] 18. The multi-resolution cache of any preceding example, wherein the current pixel row is not centered in the third cache segment.

[0132] 19. A method of operating a multi-resolution cache as recited in any preceding example, comprising:

[0133] Reading data of one cache line at full resolution from the off-chip memory;

[0134] storing the read data in the first cache segment of the cache;

[0135] reducing the resolution of data of the first cache segment to a resolution lower than the full resolution;

[0136] shifting reduced-resolution data to said fourth cache segment of said cache;

[0137] reading data of a second cache line at full resolution from the off-chip memory;

[0138] storing the read data of the second cache line in the first cache segment;

[0139] Upscaling the reduced resolution data to full resolution; and

[0140] Outputs data with increased resolution.

[0141] 20. A multi-resolution cache comprising:

[0142] a first cache segment and a second cache segment, the first segment having a first resolution and the second segment having a second resolution, the second resolution being less than the first resolution, the first cache segment being communicatively coupled to an off-chip memory, the first cache segment being configured to receive cache lines of data having the first resolution;

[0143] a first resolution reducer communicatively coupled to the first cache segment and the second cache segment and configured to reduce a resolution of a received cache line of data at a first resolution as the received cache line of data is shifted from the first cache segment to the second cache segment;

[0144] A first resolution upscaling device is communicatively coupled to the second cache segment and configured to upscale the reduced-resolution cached data to the first resolution and output the upscaled-resolution cached data.

[0145] 21. A multi-resolution cache as in any of the preceding examples, wherein cache data size allocations and resolutions of all cache segments are dynamically or unequally allocated, such that a downconverter is adjusted accordingly to generate a reduced resolution target resolution from a data source resolution.

[0146] 22. The multi-resolution cache of any of the preceding examples, wherein the second cache segment is communicatively coupled to the off-chip memory and is further configured to receive the cache line data from the off-chip memory when the cache line data is not available in the first cache segment.

[0147] Although the described flowcharts may illustrate operations as sequential processing, many operations may be performed in parallel or simultaneously. Furthermore, the order of the operations may be rearranged. A process is terminated when its operations are completed. A process may correspond to a method, procedure, algorithm, etc. The operations of a method may be performed in whole or in part, may be performed in combination with some or all of the operations in other methods, or may be performed by any number of different systems, such as the systems described herein, or any portion thereof, such as a processor included in any of these systems.

[0148] Although the present disclosure is described in terms of several embodiments, those skilled in the art will recognize that the disclosure is not limited to the embodiments described herein and can be implemented through modification and alteration within the spirit and scope of the present invention. Those skilled in the art will also recognize improvements to the embodiments of the present disclosure. All such improvements are considered to fall within the scope of the claims disclosed herein. Therefore, this description is to be regarded as illustrative rather than limiting.

Claims

1. A multi-resolution cache, characterized in that: include: a first cache segment, a second cache segment, and a third cache segment, the first cache segment, the second cache segment, and the third cache segment having a first resolution, a second resolution, and a third resolution, respectively, the second resolution being smaller than the first resolution and the third resolution being smaller than the second resolution, the first cache segment, the second cache segment, and the third cache segment being communicatively coupled to an off-chip memory, the first cache segment, the second cache segment, and the third cache segment being configured to receive cache lines of data having the first resolution, the second resolution, and the third resolution; a fourth cache segment and a fifth cache segment, the fourth cache segment and the fifth cache segment having the second resolution and a third resolution, respectively; a first resolution reducer communicatively coupled to the first cache segment and a fourth cache segment and configured to reduce the resolution when the resolution cache line is shifted from the first cache segment to the fourth cache segment; a second resolution reducer communicatively coupled to the fourth cache segment and the fifth cache segment and configured to further reduce a resolution of the reduced-resolution cache data line as the reduced-resolution cache data line is shifted from the fourth cache segment to the fifth cache segment; A first resolution upscaling device and a second resolution upscaling device are communicatively coupled to the second cache segment and the third cache segment, respectively, and are also communicatively coupled to the fourth cache segment and the fifth cache segment, respectively, and are configured to upscale the reduced-resolution cache data and the further reduced-resolution buffered data to the first resolution and output the upscaled-resolution cache data.

2. The multi-resolution cache of claim 1, wherein: The second resolution is half of the first resolution, and the third resolution is one quarter of the first resolution.

3. The multi-resolution cache of claim 2, wherein: The first resolution is full resolution.

4. The multi-resolution cache of claim 1, wherein: The second cache segment, the third cache segment, the fourth cache segment, and the fifth cache segment are arranged in a symmetrical configuration around the first cache segment.

5. The multi-resolution cache of claim 1, wherein: The cache data allocation of the second cache segment is not equal to the cache data allocation of the fourth cache segment.

6. The multi-resolution cache of claim 1, wherein: The cache data size allocations and resolutions of all cache segments are dynamically or unequally allocated, so that the downconverter is adjusted accordingly to generate a reduced-resolution target resolution from a data source resolution.

7. The multi-resolution cache of claim 1, wherein: The current pixel row is not centered in the first cache segment.

8. The multi-resolution cache of claim 1, wherein: Also included is a sixth cache segment having a resolution less than the first resolution and overlapping the first cache segment.

9. A method of operating a multi-resolution cache as claimed in claim 1, characterized in that: include: Reading data of one cache line at full resolution from the off-chip memory; storing the read data in the first cache segment of the cache; reducing the resolution of data of the first cache segment to a resolution lower than the full resolution; shifting reduced-resolution data to said fourth cache segment of said cache; reading data of a second cache line at full resolution from the off-chip memory; storing the read data of the second cache line in the first cache segment; Upscale the reduced-resolution data to full resolution; as well as Outputs data with increased resolution.

10. A multi-resolution cache, characterized in that include: a first cache segment, a second cache segment, and a third cache segment, the first cache segment having a first resolution and the second cache segment and the third cache segment having a second resolution, the second resolution being less than the first resolution, the first cache segment and the third cache segment being communicatively coupled to an off-chip memory, the first cache segment and the third cache segment being configured to receive cache lines of data having the first resolution and the second resolution; a fourth cache segment and a fifth cache segment, the fourth cache segment and the fifth cache segment having the second resolution; a first resolution reducer communicatively coupled to the first cache segment and a fourth cache segment and configured to reduce the resolution when a cache data line at the first resolution is shifted from the first cache segment to the fourth cache segment; A first resolution upscaling device is communicatively coupled to the fourth cache segment and the fifth cache segment and is configured to upscale the reduced-resolution cache data to the first resolution and output the upscaled-resolution cache data.

11. The multi-resolution cache of claim 10, wherein: The second cache segment is configured to receive cached data having the second resolution from the third cache segment when data is shifted from the third cache segment to the second cache segment.

12. The multi-resolution cache of claim 10, wherein: The second resolution is half of the first resolution.

13. The multi-resolution cache of claim 10, wherein: The second cache segment, the third cache segment, the fourth cache segment, and the fifth cache segment are arranged in a symmetrical configuration around the first cache segment.

14. The multi-resolution cache of claim 10, wherein: The cache data distribution is unequal across all cache segments.

15. The multi-resolution cache of claim 10, wherein: Also included is a sixth cache segment having a resolution less than the first resolution and overlapping the first cache segment.

16. A multi-resolution cache, characterized in that include: a first cache segment, a second cache segment, and a third cache segment, the first cache segment, the second cache segment, and the third cache segment having a first resolution, the first cache segment being communicatively coupled to an off-chip memory, the first cache segment being configured to receive cache lines of data having the first resolution; a fourth cache segment and a fifth cache segment, the fourth cache segment and the fifth cache segment having a second resolution and a third resolution, respectively, the second resolution being smaller than the first resolution and the third resolution being smaller than the second resolution; a first resolution reducer communicatively coupled to the fourth cache segment and configured to reduce the resolution of a cache line of a first resolution when the cache line is shifted from the third cache segment to the fourth cache segment; a second resolution reducer communicatively coupled to the fourth cache segment and the fifth cache segment and configured to further reduce a resolution of the reduced-resolution cache data line as the reduced-resolution cache data line is shifted from the fourth cache segment to the fifth cache segment; as well as A first resolution upscaling device and a second resolution upscaling device are communicatively coupled to the fourth cache segment and the fifth cache segment, respectively, and are configured to upscale the reduced-resolution cache data and the further reduced-rate cache data to the first resolution and output the upscaled-resolution cache data.

17. The multi-resolution cache of claim 16, wherein: The second resolution is half of the first resolution, and the third resolution is one quarter of the first resolution.

18. The multi-resolution cache of claim 16, wherein: The current pixel row is not centered in the third cache segment.

19. A method of operating the multi-resolution cache according to claim 16, characterized in that: include: Reading data of one cache line at full resolution from the off-chip memory; storing the read data in the first cache segment of the cache; reducing the resolution of data of the first cache segment to a resolution lower than the full resolution; shifting reduced-resolution data to said fourth cache segment of said cache; reading data of a second cache line at full resolution from the off-chip memory; storing the read data of the second cache line in the first cache segment; Upscale the reduced-resolution data to full resolution; as well as Outputs data with increased resolution.

20. A multi-resolution cache, characterized in that include: a first cache segment and a second cache segment, the first cache segment having a first resolution and the second segment having a second resolution, the second resolution being less than the first resolution, the first cache segment being communicatively coupled to an off-chip memory, the first cache segment being configured to receive cache lines of data having the first resolution; a first resolution reducer communicatively coupled to the first cache segment and the second cache segment and configured to reduce a resolution of a received cache line of data at a first resolution as the received cache line of data is shifted from the first cache segment to the second cache segment; A first resolution upscaling device is communicatively coupled to the second cache segment and configured to upscale the reduced-resolution cached data to the first resolution and output the upscaled-resolution cached data.

21. The multi-resolution cache of claim 20, wherein: The cache data size allocations and resolutions of all cache segments are dynamically or unequally allocated, so that the downconverter is adjusted accordingly to generate a reduced-resolution target resolution from a data source resolution.

22. The multi-resolution cache of claim 20, wherein: The second cache segment is communicatively coupled to the off-chip memory and is further configured to receive the cache line of data from the off-chip memory when the cache line of data is not available in the first cache segment.

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