Method and apparatus for initial placement of FPGA hard macrocells

Abstract

This invention discloses a method and apparatus for initial placement of FPGA hard macrocells. The method includes: establishing a timing hypergraph for all target logic devices in the FPGA circuit; wherein the target logic devices include hard macrocells, registers, and input / output units; based on the timing hypergraph, combining two hard macrocells with at least one signal transmission path as a single hard macrocell combination to obtain several hard macrocell combinations, and obtaining the timing proximity of each hard macrocell combination; based on the timing proximity of each hard macrocell combination and the current physical position of each hard macrocell, using a simulated annealing algorithm to obtain the optimal physical position of each hard macrocell, and using the optimal physical position of each hard macrocell as the initial position of each hard macrocell. This invention can rationally place the initial positions of hard macrocells based on the timing hypergraph, which is beneficial for optimizing FPGA placement and routing effects.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a method and apparatus for initial position layout of FPGA hard macrocells. Background Technology

[0002] The placement and routing phase of a Field-Programmable Gate Array (FPGA) involves placing the logic devices in the circuit, allocating routing resources, and optimizing timing to achieve a physical-level implementation of the circuit that meets timing requirements. Logic devices in an FPGA circuit include look-up tables (LUTs), hard macrocells, registers, and input / output units. Hard macrocells mainly include random access memory (RAM) and digital signal processors (DSPs). The placement process involves placing these logic devices in legal locations while minimizing the length of the interconnect bus and uniformly distributing the required routing resources.

[0003] Most existing FPGA integrated circuit automated design software uses analytical placement algorithms for logic device placement. Analytical placement algorithms comprehensively consider both total interconnect length optimization and device density uniformity. While minimizing the total interconnect length, they aim to distribute devices as evenly as possible across the chip area and minimize potential routing congestion. This algorithm is highly sensitive to the initial position of logic devices. Considering the large number of input / output pins on hard macrocells and the enormous number of timing paths associated with them, long, unoptimizable nets are likely to connect to hard macrocells, and local routing congestion areas are also likely to appear near hard macrocells. Therefore, different initial positions of logic devices, especially hard macrocells, can lead to significant differences in placement results. Suboptimal placement results, with unoptimizable long nets or local routing congestion areas, often result in timing non-convergence after routing, failing to meet frequency targets. Therefore, properly placing the initial position of hard macrocells is crucial.

[0004] Currently, the main approach is to simply place all hard macrocells in the center / lower left corner of the chip, or to randomly distribute hard macrocells in legal locations throughout the chip area. This approach does not take into account the circuit characteristics of different FPGA circuits, especially the timing path characteristics of data transmission. It is difficult to reasonably arrange the initial positions of hard macrocells, resulting in less than ideal layout results based on analytical placement algorithms, leading to problems such as routing difficulties or timing convergence. Summary of the Invention

[0005] To overcome the shortcomings of the prior art, the present invention provides a method and apparatus for initial position layout of FPGA hard macrocells, which can reasonably layout the initial position of hard macrocells based on the timing supergraph, which is beneficial to optimizing the FPGA layout and routing effect.

[0006] To address the aforementioned technical problems, in a first aspect, an embodiment of the present invention provides an initial position layout method for FPGA hard macrocells, comprising:

[0007] A timing hypergraph is established for all target logic devices in the FPGA circuit; wherein, the target logic devices include hard macrocells, registers, and input / output units;

[0008] Based on the aforementioned timing hypergraph, two hard macro units that have at least one signal transmission path are combined as a single hard macro unit combination to obtain several hard macro unit combinations, and the timing proximity of each hard macro unit combination is obtained.

[0009] Based on the timing proximity of each hard macrocell combination and the current physical position of each hard macrocell, a simulated annealing algorithm is used to obtain the optimal physical position of each hard macrocell, and the optimal physical position of each hard macrocell is used as the initial position of each hard macrocell.

[0010] Furthermore, before establishing the timing hypergraph for all target logic devices in the FPGA circuit, the following steps are also included:

[0011] Obtain the circuit netlist of the FPGA circuit, and select all the target logic devices from the circuit netlist.

[0012] Furthermore, the timing proximity of the hard macrocell combination is:

[0013]

[0014] Where M is the total number of registers on the target signal transmission path between the i-th hard macrounit and the j-th hard macrounit, and the target signal transmission path is the signal transmission path between the i-th hard macrounit and the j-th hard macrounit that passes through the most registers, m = {1, 2, ..., M}, n m is the total number of registers in the m-th level, and k is the preset exponential decay factor.

[0015] Furthermore, the step of obtaining the optimal physical position of each hard macrocell using a simulated annealing algorithm based on the temporal proximity of each hard macrocell combination and the current physical position of each hard macrocell specifically involves:

[0016] Based on the timing proximity of each hard macro unit combination and the current physical location of each hard macro unit, an objective function is constructed with the goal of minimizing the bus length between all hard macro units.

[0017] Based on the objective function, the simulated annealing algorithm is used to solve the problem and obtain the optimal physical location of each hard macrocell.

[0018] Furthermore, the objective function is:

[0019]

[0020] Where Y represents the FPGA layout scheme, A(i,j) represents the timing proximity between the i-th and j-th hard macrocells, D(i,j) represents the current Manhattan distance between the i-th and j-th hard macrocells, and D(i,j) = |x i -x j |+|y i -y j |,(x i ,y i (x) represents the current physical location of the i-th hard macrocell. j ,y j Let be the current physical location of the j-th hard macrocell, and N be the total number of all said hard macrocells, i = {1, 2, ..., N}, j = {1, 2, ..., N}.

[0021] Secondly, an embodiment of the present invention provides an initial position layout apparatus for FPGA hard macrocells, comprising:

[0022] The timing supergraph creation module is used to create a timing supergraph for all target logic devices in the FPGA circuit; wherein, the target logic devices include hard macrocells, registers, and input / output units;

[0023] The timing proximity acquisition module is used to combine two hard macro units that have at least one signal transmission path as a single hard macro unit based on the timing hypergraph, to obtain several hard macro unit combinations, and to acquire the timing proximity of each hard macro unit combination.

[0024] The initial position layout module is used to obtain the optimal physical position of each hard macro unit by using a simulated annealing algorithm based on the temporal proximity of each hard macro unit combination and the current physical position of each hard macro unit, so as to use the optimal physical position of each hard macro unit as the initial position of each hard macro unit.

[0025] Furthermore, the timing supergraph establishment module is also used to obtain the circuit netlist of the FPGA circuit before establishing the timing supergraph for all target logic devices in the FPGA circuit, and select all the target logic devices from the circuit netlist.

[0026] Furthermore, the timing proximity of the hard macrocell combination is:

[0027]

[0028] Where M is the total number of registers on the target signal transmission path between the i-th hard macrounit and the j-th hard macrounit, and the target signal transmission path is the signal transmission path between the i-th hard macrounit and the j-th hard macrounit that passes through the most registers, m = {1, 2, ..., M}, n m is the total number of registers in the m-th level, and k is the preset exponential decay factor.

[0029] Furthermore, the initial position layout module is specifically used for:

[0030] Based on the timing proximity of each hard macro unit combination and the current physical location of each hard macro unit, an objective function is constructed with the goal of minimizing the bus length between all hard macro units.

[0031] Based on the objective function, the simulated annealing algorithm is used to solve the problem and obtain the optimal physical location of each hard macrocell.

[0032] Furthermore, the objective function is:

[0033]

[0034] Where Y represents the FPGA layout scheme, A(i,j) represents the timing proximity between the i-th and j-th hard macrocells, D(i,j) represents the current Manhattan distance between the i-th and j-th hard macrocells, and D(i,j) = |x i -x j |+|y i -y j |,(x i ,y i (x) represents the current physical location of the i-th hard macrocell. j ,y j Let be the current physical location of the j-th hard macrocell, and N be the total number of all said hard macrocells, i = {1, 2, ..., N}, j = {1, 2, ..., N}.

[0035] Compared with the prior art, the embodiments of the present invention have the following beneficial effects:

[0036] A timing hypergraph is established for all target logic devices in the FPGA circuit. These target logic devices include hard macrocells, registers, and input / output units. Based on the timing hypergraph, two hard macrocells with at least one signal transmission path are grouped together to obtain several hard macrocell combinations. The timing proximity of each hard macrocell combination is then determined. Based on the timing proximity of each hard macrocell combination and the current physical position of each hard macrocell, a simulated annealing algorithm is used to obtain the optimal physical position of each hard macrocell. The optimal physical position of each hard macrocell is then used as its initial position. This allows for the rational placement of the initial positions of hard macrocells based on the timing hypergraph, which is beneficial for optimizing FPGA placement and routing. Attached Figure Description

[0037] Figure 1 This is a flowchart illustrating an initial position layout method for FPGA hard macrocells according to a first embodiment of the present invention.

[0038] Figure 2 This is a schematic diagram of a timing hypergraph exemplified in the first embodiment of the present invention;

[0039] Figure 3 This is another schematic diagram of the timing hypergraph exemplified in the first embodiment of the present invention;

[0040] Figure 4 The data flow diagram illustrating the use of simulated annealing algorithm to obtain the optimal physical location of each hard macrocell is shown in the first embodiment of the present invention.

[0041] Figure 5 This is a schematic diagram of the initial position layout device for FPGA hard macrocells in the second embodiment of the present invention. Detailed Implementation

[0042] The technical solutions of this invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0043] It should be noted that the step numbers in this document are only for the convenience of explaining the specific embodiments and are not intended to limit the order in which the steps are executed. The method provided in this embodiment can be executed by relevant terminal devices, and the following description uses a processor as the execution subject.

[0044] like Figure 1As shown, the first embodiment provides an initial location layout method for FPGA hard macrocells, including steps S1 to S3:

[0045] S1. Establish a timing hypergraph for all target logic devices in the FPGA circuit; the target logic devices include hard macrocells, registers, and input / output units.

[0046] S2. Based on the time-series hypergraph, two hard macro units that have at least one signal transmission path are combined as a single hard macro unit to obtain several hard macro unit combinations, and the time-series proximity of each hard macro unit combination is obtained.

[0047] S3. Based on the timing proximity of each hard macrocell combination and the current physical position of each hard macrocell, the simulated annealing algorithm is used to obtain the optimal physical position of each hard macrocell, and the optimal physical position of each hard macrocell is used as the initial position of each hard macrocell.

[0048] As an example, in step S1, all hard macrocells, all registers, and all input / output units in the FPGA circuit are taken as target logic devices, and a timing hypergraph is established for all target logic devices in the FPGA circuit.

[0049] The timing hypergraph ignores combinational logic units such as lookup tables in FPGA circuits, only including hard macrocells, registers, and input / output units. If there is a signal transmission path, i.e., a timing path, between any two target logic devices, then a timing connection exists between these two target logic devices in the timing hypergraph. The timing hypergraph reflects the timing connection information between hard macrocells and input / output units in the FPGA circuit, including whether there is signal transmission between the two devices, how many paths the signal transmission traverses, and how many registers are passed through on each path. The timing hypergraph can be used to efficiently obtain this timing connection information to calculate the timing proximity between two devices.

[0050] Assuming the established temporal hypergraph is as follows Figure 2 As shown, in Figure 2 In the diagram, horizontal rectangles represent hard macrocells, vertical rectangles represent registers, and squares represent input / output units. Figure 2 It can be seen that all the hard macro cells in the FPGA circuit are BRAM1, BRAM2, and DSP1. There are two signal transmission paths between BRAM1 and BRAM2, which pass through 3 and 1 registers respectively; there is one signal transmission path between BRAM1 and DSP1, which passes through 1 register.

[0051] There are three signal transmission paths between BRAM2 and DSP1, which pass through 1, 2, and 4 registers respectively.

[0052] In step S2, based on the established timing hypergraph, two hard macro units that have at least one signal transmission path are combined as a single hard macro unit combination to obtain several hard macro unit combinations. The timing proximity of each hard macro unit combination is calculated to obtain the timing proximity of each hard macro unit combination.

[0053] The temporal proximity between two hard macrocells reflects the strength of their temporal correlation. The higher the temporal proximity value, the stronger the temporal correlation between the two hard macrocells.

[0054] For example, based on such Figure 2 The timing hypergraph shown calculates the timing proximity between BRAM1 and BRAM2 as a single hard macrocell combination; it also calculates the timing proximity between BRAM1 and DSP1 as a single hard macrocell combination; and it calculates the timing proximity between BRAM2 and DSP1 as a single hard macrocell combination, thus obtaining the timing proximity of each hard macrocell combination.

[0055] In step S3, the current physical position of each hard macrocell is obtained according to the FPGA layout scheme. Based on the timing proximity of each hard macrocell combination and the current physical position of each hard macrocell, the optimal physical position of each hard macrocell is obtained by using the simulated annealing algorithm. The optimal physical position of each hard macrocell is used as the initial position of each hard macrocell. Thus, the FPGA logic device layout can be performed based on the analytical layout algorithm for the optimal physical position of each hard macrocell.

[0056] This embodiment calculates the timing proximity between any two hard macrocells based on the timing connection information between any two hard macrocells in the timing hypergraph, thereby quantifying the timing correlation between any two hard macrocells. Considering the timing correlation between any two hard macrocells, the initial positions of each hard macrocell are laid out. This allows for a reasonable layout of the initial positions of hard macrocells based on the timing hypergraph, resulting in a more ideal layout result based on the analytical placement algorithm. This effectively avoids problems such as routing difficulties or timing convergence, and is beneficial for optimizing the FPGA placement and routing effect.

[0057] In a preferred embodiment, before establishing a timing supergraph for all target logic devices in the FPGA circuit, the method further includes: obtaining the circuit netlist of the FPGA circuit and selecting all target logic devices from the circuit netlist.

[0058] As an example, the circuit netlist of the front-end integrated FPGA circuit is obtained, and all hard macrocells, all registers, and all input / output units are selected from the circuit netlist to obtain all target logic devices.

[0059] In a preferred embodiment, the timing proximity of the hard macrocell combination is:

[0060]

[0061] Where M is the total number of registers on the target signal transmission path between the i-th and j-th hard macrocells, and the target signal transmission path is the signal transmission path between the i-th and j-th hard macrocells that passes through the most registers, m = {1, 2, ..., M}, n m is the total number of registers in the m-th level, and k is the preset exponential decay factor.

[0062] As an example, each hard macro unit combination is traversed. For the currently traversed hard macro unit combination, such as the i-th hard macro unit and the j-th hard macro unit, the temporal proximity between the i-th hard macro unit and the j-th hard macro unit is calculated according to the defined temporal proximity calculation formula. The temporal proximity between the i-th hard macro unit and the j-th hard macro unit is:

[0063]

[0064] In equation (1), M represents the total number of registers on the target signal transmission path between the i-th and j-th hard macrocells, and the target signal transmission path is the signal transmission path between the i-th and j-th hard macrocells that passes through the most registers, m = {1, 2, ..., M}, n m is the total number of registers in the m-th level, and k is the preset exponential decay factor.

[0065] For example, based on such Figure 3 The temporal hypergraph shown, in Figure 3 In the diagram, horizontal rectangles represent hard macrocells, and vertical rectangles represent registers. With k=2, the timing proximity between BRAM1 and BRAM2 is:

[0066]

[0067] The timing proximity between BRAM1 and DSP1 is:

[0068] A(BRAM1,DSP1) = 1;

[0069] The timing proximity between BRAM2 and DSP1 is:

[0070]

[0071] This embodiment calculates the timing proximity of hard macrocell combinations according to the defined timing proximity calculation formula, which is beneficial for quickly and accurately quantifying the timing correlation between any two hard macrocells.

[0072] The timing proximity between a hard macro unit and an input / output unit, as well as the timing proximity between two input / output units, can also be calculated according to the defined timing proximity calculation formula.

[0073] In a preferred embodiment, the step of obtaining the optimal physical position of each hard macrocell using a simulated annealing algorithm based on the timing proximity of each hard macrocell combination and the current physical position of each hard macrocell specifically involves: constructing an objective function with the goal of minimizing the bus length between all hard macrocells based on the timing proximity of each hard macrocell combination and the current physical position of each hard macrocell; and solving the objective function using a simulated annealing algorithm to obtain the optimal physical position of each hard macrocell.

[0074] In a preferred embodiment, the objective function is:

[0075]

[0076] Where Y represents the FPGA layout scheme, A(i,j) represents the timing proximity between the i-th and j-th hard macrocells, D(i,j) represents the current Manhattan distance between the i-th and j-th hard macrocells, and D(i,j) = |x i -x j |+|y i -y j |,(x i ,y i (x) represents the current physical location of the i-th hard macrocell. j ,y j Let be the current physical location of the j-th hard macrocell, and N be the total number of all hard macrocells, i = {1, 2, ..., N}, j = {1, 2, ..., N}.

[0077] As an example, the goal of the simulated annealing algorithm is to determine the optimal physical location of each hard macrocell in the FPGA circuit. Based on the timing proximity of the combinations of hard macrocells and the current physical location of each hard macrocell, an objective function is constructed with the goal of minimizing the bus length between all hard macrocells. The objective function is:

[0078]

[0079] In equation (2), Y represents the FPGA layout scheme, A(i,j) represents the timing proximity between the i-th and j-th hard macrocells, D(i,j) represents the current Manhattan distance between the i-th and j-th hard macrocells, and D(i,j) = |x i -x j |+|y i -y j |,(x i ,y i (x) represents the current physical location of the i-th hard macrocell. j ,y j Let be the current physical location of the j-th hard macrocell, and N be the total number of all hard macrocells, i = {1, 2, ..., N}, j = {1, 2, ..., N}.

[0080] The advantage of the objective function lies in using the temporal proximity between any two hard macrocells to quantify the temporal correlation between them, with the temporal proximity serving as the weight for the distance. Optimization is performed by minimizing the bus length between hard macrocells after weighting for temporal correlation, resulting in more time-friendly optimal physical locations for each hard macrocell.

[0081] Based on the above objective function, the simulated annealing algorithm is used to solve for the optimal physical location of each hard macrocell. The algorithm flow of the simulated annealing algorithm is as follows: Figure 4 As shown, the optimal physical location of each hard macrocell can be used as the initial location of each hard macrocell required for logic device placement using analytical placement algorithms, resulting in a more ideal placement outcome, which is beneficial for the routing process and final timing convergence.

[0082] Based on the same inventive concept as the first embodiment, the second embodiment provides as follows: Figure 5 The diagram illustrates an initial position placement device for FPGA hard macrocells, comprising: a timing hypergraph establishment module 21, used to establish a timing hypergraph for all target logic devices in the FPGA circuit; wherein the target logic devices include hard macrocells, registers, and input / output units; a timing proximity acquisition module 22, used to combine two hard macrocells with at least one signal transmission path as a single hard macrocell based on the timing hypergraph, to obtain several hard macrocell combinations, and to acquire the timing proximity of each hard macrocell combination; and an initial position placement module 23, used to obtain the optimal physical position of each hard macrocell using a simulated annealing algorithm based on the timing proximity of each hard macrocell combination and the current physical position of each hard macrocell, so as to use the optimal physical position of each hard macrocell as the initial position of each hard macrocell.

[0083] In a preferred embodiment, the timing supergraph building module 21 is further configured to obtain the circuit netlist of the FPGA circuit and select all target logic devices from the circuit netlist before building the timing supergraph for all target logic devices in the FPGA circuit.

[0084] In a preferred embodiment, the timing proximity of the hard macrocell combination is:

[0085]

[0086] Where M is the total number of registers on the target signal transmission path between the i-th and j-th hard macrocells, and the target signal transmission path is the signal transmission path between the i-th and j-th hard macrocells that passes through the most registers, m = {1, 2, ..., M}, n m is the total number of registers in the m-th level, and k is the preset exponential decay factor.

[0087] In a preferred embodiment, the initial position layout module 23 is specifically used to: construct an objective function based on the timing proximity of each hard macro unit combination and the current physical position of each hard macro unit, with the optimization goal of minimizing the bus length between all hard macro units; and solve the objective function using a simulated annealing algorithm to obtain the optimal physical position of each hard macro unit.

[0088] In a preferred embodiment, the objective function is:

[0089]

[0090] Where Y represents the FPGA layout scheme, A(i,j) represents the timing proximity between the i-th and j-th hard macrocells, D(i,j) represents the current Manhattan distance between the i-th and j-th hard macrocells, and D(i,j) = |x i -x j |+|y i -y j |,(x i ,y i (x) represents the current physical location of the i-th hard macrocell. j ,y j Let be the current physical location of the j-th hard macrocell, and N be the total number of all hard macrocells, i = {1, 2, ..., N}, j = {1, 2, ..., N}.

[0091] In summary, implementing the embodiments of the present invention has the following beneficial effects:

[0092] A timing hypergraph is established for all target logic devices in the FPGA circuit. These target logic devices include hard macrocells, registers, and input / output units. Based on the timing hypergraph, two hard macrocells with at least one signal transmission path are grouped together to obtain several hard macrocell combinations. The timing proximity of each hard macrocell combination is then determined. Based on the timing proximity of each hard macrocell combination and the current physical position of each hard macrocell, a simulated annealing algorithm is used to obtain the optimal physical position of each hard macrocell. The optimal physical position of each hard macrocell is then used as its initial position. This allows for the rational placement of the initial positions of hard macrocells based on the timing hypergraph, which is beneficial for optimizing FPGA placement and routing.

[0093] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications are also considered to be within the scope of protection of the present invention.

[0094] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes described in the above embodiments. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

Claims

1. A method for initial position layout of FPGA hard macrocells, characterized in that, include: A timing hypergraph is established for all target logic devices in the FPGA circuit; wherein, the target logic devices include hard macrocells, registers, and input / output units; Based on the aforementioned timing hypergraph, two hard macro units that have at least one signal transmission path are combined as a single hard macro unit combination to obtain several hard macro unit combinations, and the timing proximity of each hard macro unit combination is obtained. Based on the timing proximity of each hard macro unit combination and the current physical position of each hard macro unit, the optimal physical position of each hard macro unit is obtained by using the simulated annealing algorithm, so as to use the optimal physical position of each hard macro unit as the initial position of each hard macro unit. The timing proximity of the hard macrocell combination is: Where M is the total number of registers on the target signal transmission path between the i-th hard macrounit and the j-th hard macrounit, and the target signal transmission path is the signal transmission path between the i-th hard macrounit and the j-th hard macrounit that passes through the most registers, m = {1, 2, ..., M}, n m is the total number of registers in the m-th level, and k is the preset exponential decay factor.

2. The initial position layout method for FPGA hard macrocells as described in claim 1, characterized in that, Before establishing the timing hypergraph for all target logic devices in the FPGA circuit, the following steps are also included: Obtain the circuit netlist of the FPGA circuit, and select all the target logic devices from the circuit netlist.

3. The initial position layout method for FPGA hard macrocells as described in claim 1, characterized in that, The optimal physical position of each hard macrocell is obtained by using a simulated annealing algorithm based on the temporal proximity of each hard macrocell combination and the current physical position of each hard macrocell. Specifically: Based on the timing proximity of each hard macro unit combination and the current physical location of each hard macro unit, an objective function is constructed with the goal of minimizing the bus length between all hard macro units. Based on the objective function, the simulated annealing algorithm is used to solve the problem and obtain the optimal physical location of each hard macrocell.

4. The initial position layout method for FPGA hard macrocells as described in claim 3, characterized in that, The objective function is: Where Y represents the FPGA layout scheme, A(i,j) represents the timing proximity between the i-th and j-th hard macrocells, D(i,j) represents the current Manhattan distance between the i-th and j-th hard macrocells, and D(i,j) = |x i -x j |+|y i -y j |,(x i ,y i (x) represents the current physical location of the i-th hard macrocell. j ,y j Let be the current physical location of the j-th hard macrocell, and N be the total number of all said hard macrocells, i = {1, 2, ..., N}, j = {1, 2, ..., N}.

5. An initial position layout device for FPGA hard macrocells, characterized in that, include: The timing supergraph creation module is used to create a timing supergraph for all target logic devices in the FPGA circuit; wherein, the target logic devices include hard macrocells, registers, and input / output units; The timing proximity acquisition module is used to combine two hard macro units that have at least one signal transmission path as a single hard macro unit based on the timing hypergraph, to obtain several hard macro unit combinations, and to acquire the timing proximity of each hard macro unit combination. The initial position layout module is used to obtain the optimal physical position of each hard macro unit by using a simulated annealing algorithm based on the temporal proximity of each hard macro unit combination and the current physical position of each hard macro unit, so as to use the optimal physical position of each hard macro unit as the initial position of each hard macro unit. The timing proximity of the hard macrocell combination is: Where M is the total number of registers on the target signal transmission path between the i-th hard macrounit and the j-th hard macrounit, and the target signal transmission path is the signal transmission path between the i-th hard macrounit and the j-th hard macrounit that passes through the most registers, m = {1, 2, ..., M}, n m is the total number of registers in the m-th level, and k is the preset exponential decay factor.

6. The initial position layout apparatus for FPGA hard macrocells as described in claim 5, characterized in that, The timing supergraph building module is further configured to obtain the circuit netlist of the FPGA circuit and select all the target logic devices from the circuit netlist before building the timing supergraph for all target logic devices in the FPGA circuit.

7. The initial position layout apparatus for FPGA hard macrocells as described in claim 5, characterized in that, The initial position layout module is specifically used for: Based on the timing proximity of each hard macro unit combination and the current physical location of each hard macro unit, an objective function is constructed with the goal of minimizing the bus length between all hard macro units. Based on the objective function, the simulated annealing algorithm is used to solve the problem and obtain the optimal physical location of each hard macrocell.

8. The initial position layout apparatus for FPGA hard macrocells as described in claim 7, characterized in that, The objective function is: Where Y represents the FPGA layout scheme, A(i,j) represents the timing proximity between the i-th and j-th hard macrocells, D(i,j) represents the current Manhattan distance between the i-th and j-th hard macrocells, and D(i,j) = |x i -x j |+|y i -y j |,(x i ,y i (x) represents the current physical location of the i-th hard macrocell. j ,y j Let be the current physical location of the j-th hard macrocell, and N be the total number of all said hard macrocells, i = {1, 2, ..., N}, j = {1, 2, ..., N}.

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