A system and method for verifying SoC chip GPIO pins

Abstract

The application discloses a kind of SoC chip GPIO pin verification system and method, including to-be-tested SoC chip and programmable logic device, the verification module is connected with to-be-tested SoC chip by communication bus;Second GPIO module matched with the first GPIO module in to-be-tested SoC chip is configured in the programmable logic device, each pin of the second GPIO module is respectively connected with each pin of the first GPIO module one-to-one;The memory device of to-be-tested SoC chip stores GPIO configuration program, test case and the preset value of GPIO parameter;The programmable logic device is used to configure the state of each pin of second GPIO module according to the GPIO configuration program, and then the input and output functions of each GPIO pin of to-be-tested SoC chip are verified according to the test data.The to-be-tested SoC chip of the application can complete the self-test of GPIO interface, without the intervention of external host device, simplifies the verification architecture and process, saves cost and time, and improves the verification efficiency.

Description

A System and Method for Verifying GPIO Pins of a SoC Chip Technical Field

[0001] This invention relates to the field of IC verification technology, and in particular to a SoC chip GPIO pin verification system and method. Background Technology

[0002] A System-on-a-Chip (SoC) chip integrates digital, analog, and processor functions onto a single silicon chip. SoC chips have become a critical technology in the field of information technology, serving as the main technology for the rapidly developing VLSI (Very Large Scale Integration) and a natural result of the continuous integration of electronic devices. GPIO (General Purpose / Input Output), as a universal I / O interface for SoC chips, can be applied to all peripheral components, resolving application uncertainties. Therefore, GPIO interfaces are important products for many integrated circuit companies; most SoC chip products support 8, 16, or 32 GPIOs, and some support even more. Thus, during chip development, it is necessary to fully verify the GPIO functional modules of the SoC chip to ensure the correctness of the final chip product.

[0003] Currently, there are two main methods for verifying GPIOs. One is the traditional input function verification, which involves manually turning a button on or off to control the external high or low voltage level. Software reads the GPIO status to verify the correctness of the input signal. The software sets the GPIO output level to drive an LED to turn on or off, demonstrating its output function. This method of verifying input and output requires manual intervention and is inefficient. Most SoC chips have multiple GPIO interfaces. To simplify the verification process, all GPIOs are connected together, and the input and output functions are verified using only a switch signal or an LED. Although the process is simplified, this method is not sufficient for verification and cannot verify the mutual influence between the various GPIO interfaces. It also requires a small amount of manual intervention. Another method involves verification via an external host computer (microcontroller chip). This method configures the SoC chip's GPIO to output mode, allowing it to output high or low levels. The microcontroller chip then reads the GPIO level values ​​and observes whether the SoC chip can output high or low levels correctly, thus eliminating the low efficiency and reliability issues of traditional manual verification. However, since both the SoC chip under test and the microcontroller chip are master devices and there are no slave devices, additional hardware is required for communication between the chips, increasing costs. The test program needs to be downloaded to the verification module via the host computer and then transferred to the SoC chip under test. Moreover, the communication bus between devices is generally a low-speed computer bus, resulting in low efficiency in both program loading steps and data transmission speed. Furthermore, the microcontroller chip program development workload is large, and the efficiency of verification platform setup needs improvement. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide a SoC chip GPIO pin verification system and method. It does not require an external host computer to configure the SoC chip program. The preset test program is stored in the memory device of the SoC chip under test. Verification can be achieved by using a programmable device, which simplifies the verification architecture and process, saves costs and time, and improves verification efficiency.

[0005] To achieve the above objectives, the present invention is implemented using the following technical solution:

[0006] In a first aspect, the present invention provides a SoC chip GPIO pin verification system, including a SoC chip under test and a programmable logic device, wherein the verification module is communicatively connected to the SoC chip under test via a communication bus.

[0007] The programmable logic device is configured with a second GPIO module that matches the first GPIO module in the SoC chip under test, and each pin of the second GPIO module is connected to each pin of the first GPIO module in a one-to-one correspondence.

[0008] The SoC chip under test stores GPIO configuration programs, test cases, and preset values ​​of GPIO parameters in its memory device.

[0009] The programmable logic device is used to configure the state of each pin of the second GPIO module according to the GPIO configuration program, and then verify the input and output functions of each GPIO pin of the SoC chip under test according to the test data.

[0010] In conjunction with the first aspect, preferably, when verifying the input function, each pin of the first GPIO module is set as an input, and each pin of the second GPIO module is set as an output;

[0011] The SoC chip under test is used to send test cases to the programmable logic device via a communication bus;

[0012] The programmable logic device is used to send test data from the second GPIO module to the first GPIO module according to the test case, so as to test the input function of each pin of the first GPIO module;

[0013] The storage device is used to compare the data received by each pin of the first GPIO module with the preset values ​​of the corresponding GPIO parameters to verify whether the input parameters of each GPIO pin of the SoC chip under test are incorrect.

[0014] In conjunction with the first aspect, preferably, when verifying the output function, each pin of the first GPIO module is set as an output, and each pin of the second GPIO module is set as an input;

[0015] The SoC chip under test is used to send test data to the second GPIO module through the first GPIO module according to the test case, so as to test the output function of each pin of the first GPIO module;

[0016] The programmable logic device is used to feed back the data received by each pin of the second GPIO module to the memory device of the SoC chip under test through the communication bus;

[0017] The storage device is used to compare the data fed back by the programmable logic device with the preset values ​​of the corresponding GPIO parameters to verify whether the output parameters of each GPIO pin of the SoC chip under test are incorrect.

[0018] In conjunction with the first aspect, preferably, the programmable logic device is a CPLD or FPGA chip.

[0019] In conjunction with the first aspect, preferably, the test cases include verifying the floating input function, input disable function, pull-up input function, pull-down input function, interrupt input function, push-pull output function, output disable function, and open-drain output function of each GPIO pin of the SoC chip under test.

[0020] In conjunction with the first aspect, preferably, the communication bus interface of the programmable logic device is configured as follows: Universal Asynchronous Receiver / Transmitter (UART), Integrated Circuit Bus Interface (IIC), Serial Peripheral Interface (SPI), Low Pin Count Bus Interface (LPC), Enhanced Series Peripheral Interface (eSPI), or Boundary Scan Test Interface (JTAG).

[0021] In conjunction with the first aspect, preferably, the programmable logic device includes an LED display; the LED display is connected to the second GPIO module and is used to display whether the verification passed or failed.

[0022] In a second aspect, the present invention provides a method for verifying GPIO pins of a SoC chip, applied to a SoC chip GPIO pin verification system as described in any of the first aspects, characterized in that the method includes:

[0023] The state of each pin of the first GPIO module and the state of each pin of the second GPIO module are set according to the GPIO configuration program. The state of each pin of the second GPIO module is opposite to the state of each pin in the first GPIO module to which it is connected.

[0024] Based on the test cases, test data is sent from each pin in the second GPIO module that is in the output state to each pin in the first GPIO module that is in the input state.

[0025] The data received by each pin in the first GPIO module that is in the input state are compared with the preset value of the corresponding GPIO parameter to verify whether the input parameters of each GPIO pin of the SoC chip under test are incorrect.

[0026] Based on the test cases, test data is sent from each pin in the first GPIO module that is in the output state to each pin in the second GPIO module that is in the input state.

[0027] The data received by each pin in the second GPIO module that is in the input state are compared with the preset values ​​of the corresponding GPIO parameters to verify whether the output parameters of each GPIO pin of the SoC chip under test are incorrect.

[0028] In conjunction with the second aspect, preferably, setting the state of each pin of the first GPIO module and the state of each pin of the second GPIO module according to the GPIO configuration program includes: setting all pins of the first GPIO module to input, all pins to output, or a portion of pins to output and a portion of pins to input; correspondingly, setting all pins of the second GPIO module to output, all pins to input, or a portion of pins to input and a portion of pins to output.

[0029] In conjunction with the second aspect, preferably, before verification, the SoC chip under test and the programmable logic device are mounted on the same circuit board, or the SoC chip under test and the programmable logic device are mounted on two separate circuit boards.

[0030] Compared with the prior art, the beneficial effects achieved by the present invention are as follows:

[0031] The SoC chip GPIO pin verification system provided by this invention allows the SoC chip under test and the programmable logic device to interact with each other through a first GPIO module and a second interface connected to the first GPIO module, thereby completing the functional verification of the GPIO. ； The GPIO configuration program, test cases, and preset values ​​of GPIO parameters are stored in the memory device of the SoC chip under test. The SoC chip under test runs the program in the memory device and uses the communication bus to complete the initialization configuration of itself and the programmable logic device, as well as the test program for GPIO function verification. Since the system of the present invention omits the host computer and does not require programming of the host computer, the process is also simplified. Verification can be achieved by using programmable devices, which simplifies the verification architecture and process, saves costs and time, and improves verification efficiency.

[0032] The SoC chip GPIO pin verification method provided by this invention differs from existing methods. In the verification environment where the SoC is used as the chip under test, the test program needs to be downloaded from a host computer to the verification module and then transferred to the chip under test. This method is inefficient in terms of both program loading steps and data transmission speed. The invention places the test program directly on the SoC chip under test, eliminating the need for downloading from a host computer. The SoC chip itself loads its local program to complete the self-test of the GPIO interface, resulting in fast loading speed and significantly improved verification efficiency. Furthermore, in this invention, the communication bus is only used for configuring the GPIO interface of the programmable logic device. The configuration program code is small and does not affect the overall verification efficiency. Moreover, if the SoC chip under test has multiple GPIO pins, this invention can avoid setting them as output / input simultaneously, and can randomly select some as inputs and others as outputs. This ensures that the influence between the pins of the first GPIO module can be verified, and it can also satisfy the function of GPIO simulating other bus interfaces, such as UART and IIC, enhancing the comprehensiveness of the verification of the interface functions of each pin of the first GPIO module.

[0033] The method of this invention can also be applied to the verification of interrupt input functions, while the verification methods in the prior art cannot be well applied in this situation. Attached Figure Description

[0034] Figure 1 is a structural principle block diagram of a SoC chip GPIO pin verification system provided in an embodiment of the present invention;

[0035] Figure 2 is a structural principle block diagram of a SoC chip GPIO pin verification system provided in an embodiment of the present invention when verifying input functions;

[0036] Figure 3 is a structural principle block diagram of a SoC chip GPIO pin verification system provided in an embodiment of the present invention when verifying output functions;

[0037] Figure 4 is a flowchart illustrating a SoC chip GPIO pin verification method provided in an embodiment of the present invention. Detailed Implementation

[0038] The technical solution of the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the embodiments and specific features in the embodiments are detailed descriptions of the technical solution of the present application, rather than limitations thereof. In the absence of conflict, the embodiments and technical features in the embodiments can be combined with each other.

[0039] In this article, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0040] SOC chips are typically equipped with GPIO functionality and integrate a central processing unit (CPU). Due to the integration of the CPU, the SOC chip under test can run program code itself. Therefore, the SOC can directly run test programs and configure the GPIO interface status of the editable logic device. Thus, the verification system provided in this embodiment of the invention only requires setting up the SOC chip under test and the editable logic device.

[0041] As shown in Figure 1, this embodiment introduces a SoC chip GPIO pin verification system, including a SoC chip under test (DUT) and a programmable logic device (PLD). A verification module is communicatively connected to the DUT via a communication bus. The PLD is configured with a second GPIO module that matches a first GPIO module in the DUT, with each pin of the second GPIO module corresponding to a pin of the first GPIO module. The DUT and the PLD interact through the interface between the first and second GPIO modules to complete the GPIO function verification. The DUT's memory stores a GPIO configuration program, test cases, and preset values ​​for GPIO parameters. The PLD configures the state of each pin of the second GPIO module according to the GPIO configuration program and then verifies the input / output functions of each GPIO pin of the DUT based on the test data. Furthermore, the PLD includes an LED display connected to the second GPIO module to indicate whether the verification passed or failed.

[0042] As one embodiment of the present invention, the programmable logic device adopts a CPLD or FPGA chip; the communication bus interface configuration of the programmable logic device is: Universal Asynchronous Receiver / Transmitter (UART), Integrated Circuit Bus Interface (IIC), Serial Peripheral Interface (SPI), Low Pin Count Bus Interface (LPC), Enhanced Series Peripheral Interface (eSPI), or Boundary Scan Test Interface (JTAG).

[0043] It should be noted that both the SoC under test (DUT) and the programmable logic device (PLD) have their own GPIO function modules. When using them, if the first GPIO module pin of the DUT is set to output, the corresponding second GPIO module pin of the PLD should be set to input; if the first GPIO module pin of the DUT is set to input, the corresponding second GPIO module pin of the PLD should be set to output. The communication bus is used by the DUT to send GPIO configuration information and test data to the PLD, and also to collect GPIO pin interface status data of the PLD for the PLD.

[0044] In this embodiment, when verifying the input function, each pin of the first GPIO module is set as an input, and each pin of the second GPIO module is set as an output. The SoC chip under test is used to send test cases to the programmable logic device via a communication bus. The programmable logic device is used to send test data to the first GPIO module using the second GPIO module according to the test cases to test the input function of each pin of the first GPIO module. The storage device is used to compare the data received by each pin of the first GPIO module with the preset values ​​of the corresponding GPIO parameters to verify whether the input parameters of each GPIO pin of the SoC chip under test are incorrect. Furthermore, in this embodiment, when verifying the output function, each pin of the first GPIO module is set as an output, and each pin of the second GPIO module is set as an input. The SoC chip under test is used to send test data to the second GPIO module through the first GPIO module according to the test case to test the output function of each pin of the first GPIO module. The programmable logic device is used to feed back the data received by each pin of the second GPIO module to the memory device of the SoC chip under test through the communication bus. The memory device is used to compare the data fed back by the programmable logic device with the preset values ​​of the corresponding GPIO parameters to verify whether the output parameters of each GPIO pin of the SoC chip under test are incorrect.

[0045] Specifically, as shown in Figure 2, the input function verification block diagram of the SoC chip under test (SoC) indicates the data transmission direction. During verification, the SoC chip under test first configures the pin interfaces of its first GPIO module to the input state. The SoC chip under test then uses the communication bus to configure the pin interfaces of the second GPIO module of the programmable logic device (PLD) to the output state. The SoC chip under test sends test data to the GPIO module register of the PLD via the communication bus. Then, the PLD's GPIO module sets the level of each pin of the second GPIO module to high or low according to the register value. At this time, each GPIO pin on the SoC chip under test reads the high or low level of the interface and compares the obtained data result with the preset value of the GPIO parameter sent to the PLD via the communication bus. If they match, the input function verification is successful; if they do not match, the input function is faulty.

[0046] Furthermore, Figure 3 is a block diagram for verifying the output function of the SoC under test (SoC). The data transmission direction is indicated in the figure. During verification, the SoC under test first configures the pin interfaces of its first GPIO module to the output state. The SoC under test then uses the communication bus to configure the pin interfaces of the second GPIO module of the programmable logic device to the input state. The SoC under test sets its first GPIO module register and then sets the level of each pin of the first GPIO module to high or low. At this time, the SoC under test collects the GPIO register values ​​of the programmable logic device through the communication bus and compares the obtained data results with the preset values ​​of the GPIO parameters in the memory device of the SoC under test. If they match, the output function verification is successful; if they do not match, the output function is faulty.

[0047] As an embodiment of the present invention, the test cases include verifying the floating input function, input disable function, pull-up input function, pull-down input function, interrupt input function, push-pull output function, output disable function, and open-drain output function of each GPIO pin of the SoC chip under test.

[0048] The SoC chip GPIO pin verification system provided by this invention allows the test program to be stored in the memory device of the SoC chip under test, eliminating the need for external master device intervention, thereby simplifying the verification architecture and saving costs. The communication bus interface of the programmable logic device can be configured as: Universal Asynchronous Receiver / Transmitter (UART), Integrated Circuit Bus Interface (IIC), Serial Peripheral Interface (SPI), Boundary Scan Test Interface (JTAG), Low Pin Count Bus Interface (LPC), Enhanced Series Peripheral Interface (eSPI), etc., thereby meeting the communication interface scenarios of different SoC chips under test GPIO pins.

[0049] This invention provides a method for verifying GPIO pins of a SoC chip, applied to the aforementioned SoC chip GPIO pin verification system. Before verification, the SoC chip under test (UTP) stores its own configuration initialization file, and the programmable logic device (PLD) also stores its own configuration initialization file. The UTP and PLD can be designed on a single circuit board or as two separate circuit boards. The UTP can be a circuit board for placing the chip under test, or the IP code of the chip under test can be integrated into an FPGA simulation platform. The method includes:

[0050] Step A: Set the state of each pin of the first GPIO module and the state of each pin of the second GPIO module according to the GPIO configuration program. The state of each pin of the second GPIO module is opposite to the state of each pin in the first GPIO module to which it is connected.

[0051] Step B: Based on the test cases, send test data to each pin in the first GPIO module that is in the state of input through each pin in the second GPIO module that is in the state of output;

[0052] Step C: Compare the data received by each pin in the first GPIO module that is in the input state with the preset value of the corresponding GPIO parameter to verify whether the input parameters of each GPIO pin of the SoC chip under test are incorrect;

[0053] Step D: Based on the test cases, send test data to each pin in the second GPIO module that is in the state of input through each pin in the first GPIO module that is in the state of output;

[0054] Step D: Compare the data received by each pin in the second GPIO module that is in the input state with the preset values ​​of the corresponding GPIO parameters to verify whether the output parameters of each GPIO pin of the SoC chip under test are incorrect.

[0055] As an embodiment of the present invention, setting the state of each pin of the first GPIO module and the state of each pin of the second GPIO module according to the GPIO configuration program includes: setting all pins of the first GPIO module to input, all pins to output, or a portion of pins to output and a portion of pins to input; correspondingly, setting all pins of the second GPIO module to output, all pins to input, or a portion of pins to input and a portion of pins to output.

[0056] Specifically, referring to Figure 4, the specific process of implementing the SoC chip GPIO pin verification method provided by the present invention includes:

[0057] Mount the SoC chip under test on the circuit board, and connect the physical path between the SoC chip under test and the programmable logic device as shown in Figure 1;

[0058] The pre-programmed programs include: GPIO configuration programs and test cases, which are programmed into the SoC chip's memory via a programmer or in-circuit programming; the configuration programs for programmable logic devices are programmed into their own memory via a programmer or in-circuit programming.

[0059] When the circuit board is powered on, the SoC chip under test and the programmable logic device load the program in their respective memory devices and complete their respective initialization work.

[0060] After the SoC chip under test is initialized, the GPIO interface status configuration program in the storage device is loaded. The pin status of the first GPIO module of the SoC chip under test and the second GPIO module of the programmable logic device are configured as input or output. Then, the test program is run according to the test cases. Data is sent to the GPIO pin configured as output and then data is collected from the GPIO pin configured as input. Finally, the sent data and the collected data are compared. If they match, the input and output functions are considered to be normal.

[0061] It should be noted that the SoC chip under test provided in this embodiment of the invention uses preset information and data from the receiving end for comparison. As described in Figure 4, the comparison can be performed once for each round of testing; or the comparison can be performed all at once after all tests are completed.

[0062] As an embodiment of the present invention, the following is a detailed description of the different input and output target verification contents of each GPIO pin of the SoC chip under test based on pre-set test cases:

[0063] 1. Verification of floating input function:

[0064] The SoC under test sets all pins of the first GPIO module to floating input state, and configures the pins of the second GPIO module of the programmable logic device to output state through the communication bus. The SoC under test sends test data (all 1s) to the register of the programmable logic device through the communication bus. According to the value of the register, the programmable logic device sets all pins of the second GPIO module of the programmable logic device to high. The SoC under test reads the register data value of the first GPIO module. If the result is all 1s, it is correct; if there are any non-1s, the incorrect pins in the first GPIO module are recorded in memory, FLASH or external storage device.

[0065] The SoC chip under test then sends test data (all zeros) to the register of the programmable logic device via the communication bus. At this time, the GPIO pin level of the programmable logic device is set to all low. The SoC chip under test reads the register data value of the first GPIO module. If the result is all zeros, it is correct; if there are any non-zero values, the incorrect pins in the first GPIO module are recorded in memory, FLASH or peripheral storage device.

[0066] 2. Disable input verification:

[0067] The SoC under test (SoC) sets all pins of its first GPIO module to an input-disabled state. The SoC then configures the GPIO module pins of its programmable logic device (PLD) to output state via the communication bus. The SoC sets all register data in the first GPIO module to 0. The SoC sends test data (all 1s) to the PLD register via the communication bus. Based on the register value, the PLD sets all pins of its second GPIO module to high. The SoC reads the register data from the first GPIO module; a result of all 0s indicates a correct reading. If any pins are not 0, the erroneous pins in the first GPIO module are recorded in memory, flash memory, or an external storage device.

[0068] The SoC chip under test sets all register data of the first GPIO module to 1, and then sends test data (all 0) to the register of the programmable logic device via the communication bus. At this time, the pin level of the second GPIO module of the programmable logic device is set to low. The SoC chip under test reads the register data value of the first GPIO module. If the result is all 1, it is correct; if there is any non-1, the incorrect pin in the first GPIO module will be recorded in memory, FLASH or peripheral storage device.

[0069] 3. Verification of the pull-up input function:

[0070] The SoC under test (SoC) sets all pins of its first GPIO module to pull-up input and configures all pins of its second GPIO module to output via the communication bus. The SoC sends test data (all zeros) to the registers of the programmable logic device (PLD) via the communication bus. Based on the register value, the PLD sets all pins of its second GPIO module to low. The SoC reads the register data from the first GPIO module; a result of all zeros indicates a correct reading. If any pins are not zero, the erroneous pins in the first GPIO module are recorded in memory, flash memory, or an external storage device.

[0071] The SoC under test (DUT) configures the GPIO module pins of its programmable logic device to an disabled output state via the communication bus. The DUT reads the register data of its own GPIO module; if all read values ​​are 1, the operation is correct. If any value is not 1, the erroneous pin in the first GPIO module is recorded in memory, FLASH, or an external storage device.

[0072] 4. Verification of drop-down input function:

[0073] The SoC under test (SoC) sets all pins of its first GPIO module to pull-down input and configures all pins of its second GPIO module to push-pull output via the communication bus. The SoC sends test data (all 1s) to the register of the programmable logic device (PLD) via the communication bus. Based on the register value, the PLD sets all pins of its second GPIO module to high. The SoC reads the register data from the first GPIO module; a result of all 1s indicates a correct reading. If any pins are not 1s, the erroneous pins in the first GPIO module are recorded in memory, flash memory, or an external storage device.

[0074] The SoC under test configures the GPIO module pins of the programmable logic device to the disabled output state through the communication bus; the SoC under test reads the register data of the first GPIO module, and the result of all readings being 0 indicates that it is correct; if there are any non-zero values, the erroneous pins in the first GPIO module are recorded in memory, FLASH or peripheral storage device.

[0075] 5. Verification of interrupted input function:

[0076] (1) Verification of high-level interrupt function

[0077] The SoC under test sets the first pin of the first GPIO module to a high-level interrupt input state, and configures the pin of the second GPIO module of the programmable logic device to a pull-down output state through the communication bus. The SoC under test sends test data through the communication bus, sets the first GPIO pin of the programmable logic device to a high level, and the other pins to a low level. If the SoC under test receives an interrupt signal, it indicates that the function is normal; otherwise, the function is incorrect, and the error is recorded.

[0078] The SoC chip under test is verified by setting the second pin of the first GPIO module to high level and the rest to low level, following the above method, until the last GPIO pin; and recording any erroneous pins encountered during the process.

[0079] (2) Verification of low-level interrupt function

[0080] The SoC under test (DUT) sets the first pin of its first GPIO module to a low-level interrupt input state and configures the second GPIO module pin of the programmable logic device to a pull-up output state via the communication bus. The DUT sends test data via the communication bus, setting the first GPIO pin of the programmable logic device to a low level and the remaining pins to a high level. If the DUT receives an interrupt signal at this time, it indicates normal function; otherwise, it indicates a functional error, and this is recorded.

[0081] The SoC chip under test is set to the second pin of the first GPIO module as low and the rest as high, following the above method, until the last GPIO pin is verified; and any erroneous pins encountered during the process are recorded.

[0082] (3) Verification of rising edge interrupt function

[0083] The SoC under test (SoC) sets the first pin of its first GPIO module to a rising-edge interrupt input state and configures all pins of the second GPIO module of the programmable logic device to a pull-down output state via the communication bus. The SoC under test sends test data via the communication bus, setting the first GPIO pin of the programmable logic device to a high level while leaving the other pins unchanged. If the SoC under test receives an interrupt signal at this time, it indicates normal function; otherwise, it indicates a functional error, and this is recorded.

[0084] The SOC chip under test is configured by setting the second pin of the first GPIO module in sequence according to the above method, while keeping the other pins unchanged, until the last GPIO pin is verified; and any erroneous pins encountered during the process are recorded.

[0085] (4) Verification of falling edge interrupt function

[0086] The SOC chip under test sets the first pin of its first GPIO module to a falling-edge interrupt input state, and configures all pins of the second GPIO module of the programmable logic device to a pull-up output state via the communication bus. The SOC chip under test sends test data via the communication bus, setting the first GPIO pin of the programmable logic device to a low level while leaving the other pins unchanged. If the SOC chip under test receives an interrupt signal at this time, it indicates normal function; otherwise, it indicates a functional error, and this is recorded.

[0087] The SOC chip under test is configured by setting the second pin of the first GPIO module in sequence according to the above method, while keeping the other pins unchanged, until the last GPIO pin is verified; and any erroneous pins encountered during the process are recorded.

[0088] 6. Push-pull output function verification:

[0089] The SOC chip under test sets all pins of the first GPIO module to push-pull output state, and configures each pin of the second GPIO module of the programmable logic device to input state through the communication bus.

[0090] The SOC chip under test sets all register data of the first GPIO module to 0, and reads the register data of the second GPIO module in the programmable device through the communication bus. If all read results are 0, it is correct; if there are any non-zero results, the incorrect GPIO pins are recorded in memory, FLASH or peripheral storage devices.

[0091] The SOC chip under test sets all register data of its own GPIO module to 1, and reads the register data of the second GPIO module in the programmable device through the communication bus. If all read results are 1, it is correct; if there are any non-1, the incorrect GPIO pin is recorded in memory, FLASH or peripheral storage device.

[0092] 7. Disable output function verification:

[0093] The SOC chip under test sets all pins of the first GPIO module to the output disabled state, and configures each pin of the second GPIO module of the programmable logic device to the pull-down input state through the communication bus.

[0094] The SOC chip under test sets all register data of the first GPIO module to 1, and reads the register data of the programmable device GPIO module through the communication bus. If all read results are 0, it is correct; if there are any non-zero results, the incorrect GPIO pin is recorded in memory, FLASH or peripheral storage device.

[0095] The SOC chip under test configures each pin of the second GPIO module of the programmable logic device to a pull-up input state through the communication bus.

[0096] The SOC chip under test sets all register data of its own GPIO module to 0, and reads the register data of the second GPIO module of the programmable device through the communication bus. If all read results are 1, it is correct; if there are any non-1s, the incorrect GPIO pin is recorded in memory, FLASH or peripheral storage device.

[0097] 8. Verification of open-leak output function:

[0098] The SOC chip under test sets all pins of its first GPIO module to open-drain output and configures all pins of the second GPIO module of the programmable logic device to floating input via the communication bus. The SOC chip under test enables the open-drain output of its first GPIO module and reads the register data of the second GPIO module of the programmable logic device via the communication bus. A read result of all zeros indicates a correct result; if any result is not zero, the incorrect GPIO pin is recorded in memory, FLASH, or an external storage device.

[0099] The SOC chip under test configures each pin of the second GPIO module of the programmable logic device to pull-up input state through the communication bus; the SOC chip under test sets the open-drain output of the first GPIO module to be disabled, and reads the register data of the GPIO module of the programmable device through the communication bus. If all the read results are 1, it is correct; if there are any non-1, the erroneous GPIO pin is recorded in memory, FLASH or peripheral storage device.

[0100] After all functional tests are completed, the verification results are written to the data storage device through the SoC chip under test, and the final result is displayed on the LED display of the circuit board to show whether it is correct or not.

[0101] In summary, the SoC chip GPIO pin verification method provided by this invention allows the SoC chip under test to not only configure and collect its own GPIO information, but also configure and collect data from programmable logic devices. This method enables the SoC chip under test to complete self-testing of the GPIO interface, thereby simplifying the process and saving costs and time. For SoC chips under test with multiple GPIO pins, it allows for different settings to be configured as output / input simultaneously, and allows for random selection of a few as inputs or outputs for verification. This ensures that the influence between the pin interfaces of the first GPIO module can be verified, and it can also meet the function of GPIO simulating other bus interfaces, such as UART and IIC, thereby enhancing the comprehensiveness of interface function verification.

[0102] When the GPIO pins of the SoC chip under test are used as interrupt inputs, a certain duration of high or low level is required. The duration can be controlled by setting the pin function of the programmable logic device, thus enabling functional verification under different conditions, such as when the duration is not met and when it is. The programmable logic device can send multiple interrupt signals with different timing requirements to the SoC chip under test. When used in conjunction with the communication bus, the SoC chip under test can clear the interrupt source, which meets the requirements of multi-scenario verification with adjustable parameters.

[0103] Furthermore, since programmable logic devices have a rich set of pins, almost all of them can be used to test GPIO functions. This method can satisfy the GPIO function verification of almost all SoC chips.

[0104] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0105] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0106] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in one or more flowchart illustrations and / or one or more block diagrams.

[0107] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means that implement the functions specified in one or more flowcharts and / or one or more block diagrams.

[0108] These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, such that the instructions, which execute on the computer or other programmable apparatus, provide steps for implementing the functions specified in one or more flowcharts and / or one or more block diagrams.

[0109] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A SoC chip GPIO pin verification system, characterized in that, The system includes a SoC under test (DUT), a programmable logic device (PLD), and a verification module. The verification module is communicatively connected to the DUT via a communication bus. The PLD is configured with a second GPIO module that matches a first GPIO module in the DUT, with each pin of the second GPIO module connected to a corresponding pin of the first GPIO module. The DUT's memory stores GPIO configuration programs, test cases, and preset values ​​for GPIO parameters. The PLD is used to configure the state of each pin of the second GPIO module according to the GPIO configuration program, and then verify the input / output functions of each GPIO pin of the DUT according to the following steps: When verifying the input function of each GPIO pin of the DUT, the register of the second GPIO module is connected... The system receives test data from the SoC under test (SoC) and sets the voltage levels of each pin of the second GPIO module to high or low based on the test data. It reads the voltage level of each GPIO pin on the SoC under test side and compares the reading result with the preset values ​​of the GPIO parameters of the programmable device. If they match, the input function verification is successful; otherwise, the input function is faulty. When verifying the output function of each GPIO pin of the SoC under test, the SoC under test sets its own first GPIO module register, and then sets the voltage levels of each pin of the first GPIO module to high or low. The SoC under test reads the GPIO register value of the programmable logic device and compares the reading result with the preset values ​​of the GPIO parameters in the SoC under test's memory device. If they match, the output function verification is successful. If they are inconsistent, the output function is faulty.

2. The SoC chip GPIO pin verification system according to claim 1, characterized in that, When verifying the input function, each pin of the first GPIO module is set as an input, and each pin of the second GPIO module is set as an output. The SoC chip under test is used to send test cases to the programmable logic device via the communication bus. The programmable logic device is used to send test data to the first GPIO module using the second GPIO module according to the test cases, so as to test the input function of each pin of the first GPIO module. The storage device is used to compare the data received by each pin of the first GPIO module with the preset value of the corresponding GPIO parameter to verify whether the input parameters of each GPIO pin of the SoC chip under test are incorrect.

3. The SoC chip GPIO pin verification system according to claim 1, characterized in that, When verifying the output function, each pin of the first GPIO module is set as an output, and each pin of the second GPIO module is set as an input. The SoC chip under test is used to send test data to the second GPIO module through the first GPIO module according to the test case to test the output function of each pin of the first GPIO module. The programmable logic device is used to feed back the data received by each pin of the second GPIO module to the memory device of the SoC chip under test through the communication bus. The memory device is used to compare the data fed back by the programmable logic device with the preset values ​​of the corresponding GPIO parameters to verify whether the output parameters of each GPIO pin of the SoC chip under test are incorrect.

4. The SoC chip GPIO pin verification system according to claim 1, characterized in that, The programmable logic device uses a CPLD or FPGA chip.

5. The SoC chip GPIO pin verification system according to claim 1, characterized in that, The test cases include verifying the floating input function, input disable function, pull-up input function, pull-down input function, interrupt input function, push-pull output function, output disable function, and open-drain output function of each GPIO pin of the SoC chip under test.

6. The SoC chip GPIO pin verification system according to claim 1, characterized in that, The communication bus interface configuration of the programmable logic device is as follows: Universal Asynchronous Receiver / Transmitter (UART), Integrated Circuit Bus Interface (IIC), Serial Peripheral Interface (SPI), Low Pin Count Bus Interface (LPC), Enhanced Series Peripheral Interface (eSPI), or Boundary Scan Test Interface (JTAG).

7. The SoC chip GPIO pin verification system according to claim 1, characterized in that, The programmable logic device is equipped with an LED display; the LED display is connected to the second GPIO module and is used to display whether the verification is successful or not.

8. A method for verifying GPIO pins of a SoC chip, applied to the SoC chip GPIO pin verification system as described in any one of claims 1 to 7, characterized in that, The method includes: setting the states of each pin of a first GPIO module and each pin of a second GPIO module according to a GPIO configuration program, wherein the states of each pin of the second GPIO module are opposite to the states of each pin in the first GPIO module to which they are respectively connected; based on the test cases, sending test data from each pin in the second GPIO module that is in the output state to each pin in the first GPIO module that is in the input state; comparing the data received by each pin in the first GPIO module that is in the input state with the preset values ​​of the corresponding GPIO parameters to verify whether the input parameters of each GPIO pin of the SoC chip under test are incorrect; based on the test cases, sending test data from each pin in the first GPIO module that is in the output state to each pin in the second GPIO module that is in the input state; comparing the data received by each pin in the second GPIO module that is in the input state with the preset values ​​of the corresponding GPIO parameters to verify whether the output parameters of each GPIO pin of the SoC chip under test are incorrect.

9. The SoC chip GPIO pin verification method according to claim 8, characterized in that, The step of setting the state of each pin of the first GPIO module and the state of each pin of the second GPIO module according to the GPIO configuration program includes: setting all pins of the first GPIO module to input, all pins to output, or a portion of pins to output and a portion of pins to input; correspondingly, setting all pins of the second GPIO module to output, all pins to input, or a portion of pins to input and a portion of pins to output.

10. The SoC chip GPIO pin verification method according to claim 8, characterized in that, Before verification, the SoC chip under test and the programmable logic device are placed on the same circuit board, or the SoC chip under test and the programmable logic device are placed on two separate circuit boards.

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