Complement calculation method, unit circuit and storage and calculation device based on resistive memory

Abstract

An embodiment of the present application provides a complement calculation method, unit circuit and storage and calculation device based on resistive random access memory, and the above-mentioned circuit includes: a data bit current generation unit, including a data bit current input terminal, a positive weight current output terminal, a negative weight low bit current output terminal and a negative weight high bit current output terminal, and the data bit current input terminal is used to be electrically connected to the data bit line; a sign bit current comparison unit, including a sign bit current input terminal and a data output terminal, the sign bit current input terminal is used to be electrically connected to the sign bit line, and the sign bit current comparison unit is electrically connected to the positive weight current output terminal, the negative weight low bit current output terminal and the negative weight high bit current output terminal; the data bit current generation unit is used to divide the bit line current of the data bit line into mirror currents based on weights; the sign bit current comparison unit is used to output the mirror currents of different weights according to the size of the bit line current of the sign bit line.

Description

Technical Field

[0001] The present invention relates to the field of memory calculation, and specifically to a complement calculation method, unit circuit and storage and calculation device based on resistive random access memory. Background Art

[0002] The traditional von Neumann architecture has separate computing units and memory, but with the advancement of technology, the reading speed of memory has not been improved, making it difficult to further improve the performance of the processor. In-memory computing is an effective way to improve processor performance under the non-von Neumann architecture.

[0003] RRAM (Resistance Random Access Memory) has attracted widespread attention and application in the field of in-memory computing due to its high integration and low power consumption. However, existing RRAM-based complement calculation circuits have problems such as too many functional modules and long current paths, resulting in low operating efficiency and high energy consumption. Summary of the Invention

[0004] The embodiments of the present application provide a method, unit circuit, and storage and computing device for calculating the complement of a resistive memory, which can solve the problem that the existing circuit for calculating the complement of a resistive memory has too many functional modules and a long current path, resulting in low operating efficiency and high energy consumption.

[0005] A first aspect of an embodiment of the present application provides a complement calculation unit circuit based on a resistive random access memory, the circuit comprising:

[0006] A data bit current generating unit, the data bit current generating unit comprising a data bit current input terminal, a positive weight current output terminal, a negative weight low bit current output terminal and a negative weight high bit current output terminal,

[0007] The data bit current input terminal is used to be electrically connected to the data bit line;

[0008] A sign bit current comparison unit, the sign bit current comparison unit comprising a sign bit current input terminal and a data output terminal,

[0009] The sign bit current input terminal is used to be electrically connected to the sign bit line,

[0010] The sign bit current comparison unit is electrically connected to the positive weight current output terminal, the negative weight low bit current output terminal and the negative weight high bit current output terminal;

[0011] The data bit current generating unit is used to divide the bit line current of the data bit line into mirror currents based on weights;

[0012] The sign bit current comparison unit is configured to output the mirror currents with different weights according to the bit line current of the sign bit bit line.

[0013] Optionally, the sign bit current comparison unit includes:

[0014] A current comparator, the current comparator comprising a first level output terminal and a second level output terminal;

[0015] A first level-triggered switch K1 is electrically connected to the positive weighted current output terminal.

[0016] The first level trigger switch K1 is electrically connected to the second level output end;

[0017] A second level trigger switch K2 is electrically connected to the negative weight low current output terminal.

[0018] The second level trigger switch K2 is electrically connected to the first level output end;

[0019] A third level trigger switch K3 is electrically connected to the negative weight high current output terminal.

[0020] The third level trigger switch K3 is electrically connected to the first level output end;

[0021] A shunt circuit, the shunt circuit comprising a first current inflow end and a second current inflow end,

[0022] The first current inflow end is electrically connected to the first level trigger switch K1 and the third level trigger switch K3.

[0023] The second current inflow end is electrically connected to the second level trigger switch K2,

[0024] The shunt circuit is used to shunt the mirror current according to the on-off status of the level-triggered switch.

[0025] Optionally, the data bit current generating unit includes:

[0026] The first current mirror circuit includes an input-side PMOS transistor M P0 and the first mirror side PMOS tube M P1 , the second mirror side PMOS tube M P2 , the third mirror side PMOS tube M P3 ,

[0027] The M P0 、The M P1 、The M P2 and the MP3 The source is used to be electrically connected to the power supply terminal,

[0028] The M P0 The gate and the M P1 、The M P2 、The M P3 The gate is electrically connected to

[0029] The M P0 The drain and gate are short-circuited.

[0030] The M P0 The drain is electrically connected to the data bit line,

[0031] The M P1 The drain is electrically connected to the first level trigger switch K1,

[0032] The M P2 The drain is electrically connected to the second level trigger switch K2,

[0033] The M P3 The drain is electrically connected to the third level triggered switch K3.

[0034] Optionally, the data bit current generating unit includes:

[0035] The first current mirror circuit includes an input-side PMOS transistor M P0 and M P4 , the first mirror side PMOS tube M P1 and M P5 , the second mirror side PMOS tube M P2 and M P6 , the third mirror side PMOS tube M P3 and M P7 ,

[0036] The M P0 、The M P1 、The M P2 and the M P3 The source is used to be electrically connected to the power supply terminal,

[0037] The M P0 The gate and the M P1 、The M P2 and the M P3 The gate is electrically connected to

[0038] The M P0 The gate and the M P4 The drain is electrically connected to

[0039] The M P4 The gate and the MP5 、The M P6 、The M P7 The gate is electrically connected to

[0040] The M P4 The drain is electrically connected to the data bit line,

[0041] The M P5 The drain is electrically connected to the first level trigger switch K1,

[0042] The M P6 The drain is electrically connected to the second level trigger switch K2,

[0043] The M P7 The drain is electrically connected to the third level triggered switch K3.

[0044] Optionally, the shunt circuit includes:

[0045] The second current mirror circuit includes an input-side NMOS transistor M N3 and the mirror side NMOS tube M N2 ,

[0046] The M N3 and the M N2 The source is used to be electrically connected to the ground terminal,

[0047] The M N3 The drain and gate are short-circuited.

[0048] The M N3 The drain is electrically connected to the second level trigger switch K2,

[0049] The M N2 The drain is electrically connected to the first level trigger switch K1 and the third level trigger switch K3.

[0050] Optionally, the shunt circuit includes:

[0051] The second current mirror circuit includes an input-side NMOS transistor M N3 and the mirror side NMOS tube M N2 ,

[0052] The M N3 and the M N2 The source is used to be electrically connected to the ground terminal,

[0053] The M N3 The drain and gate are short-circuited.

[0054] The M N3 The drain is electrically connected to the second level trigger switch K2,

[0055] The M N2 The drain is electrically connected to the first level trigger switch K1 and the third level trigger switch K3.

[0056] Optionally, the shunt circuit includes:

[0057] The second current mirror circuit includes an input-side NMOS transistor M N1 and M N3 and the mirror side NMOS tube M N0 and M N2 ,

[0058] The M N3 and the M N2 The source is used to be electrically connected to the ground terminal,

[0059] The M N1 The drain and the M N3 The gate is electrically connected to

[0060] The M N1 The drain is electrically connected to the second level trigger switch K2,

[0061] The M N0 The drain is electrically connected to the first level trigger switch K1 and the third level trigger switch K3.

[0062] Optionally, the M P1 、M P2 and M P3 The channel width-to-length ratio is 1:1:2.

[0063] A second aspect of an embodiment of the present application provides a method for calculating a complement based on a resistive random access memory, which is used in the circuit according to any one of the first aspects. The method includes:

[0064] Using a data bit current generating unit to generate a mirror current based on the weight of the bit line current of the data bit, wherein the mirror current includes a positive weight mirror current, a negative weight low bit mirror current and a negative weight high bit mirror current;

[0065] Comparing the current of the sign bit line with the threshold current using a sign bit current comparison unit;

[0066] Based on the comparison result, the sign bit current comparison unit is controlled to output the mirror current.

[0067] Optionally, controlling the sign bit current comparison unit to output the mirror current based on the comparison result includes:

[0068] When the comparison result shows that the current of the sign bit line is less than the threshold current, controlling the sign bit current comparison unit to output the positive weighted mirror current;

[0069] When the comparison result shows that the current of the sign bit line is greater than the threshold current, the sign bit current comparison unit is controlled to output the difference between the negative weighted high bit mirror current and the negative weighted low bit mirror current.

[0070] A third aspect of an embodiment of the present application provides a storage and computing device based on a resistive random access memory, the device comprising:

[0071] A resistive switching memory array and a circuit as described above in any one of the first aspects.

[0072] In summary, an embodiment of the present application provides a complement calculation unit circuit based on a resistive memory, and the above circuit includes: a data bit current generation unit, including a data bit current input terminal, a positive weight current output terminal, a negative weight low bit current output terminal and a negative weight high bit current output terminal, and the data bit current input terminal is used to be electrically connected to the data bit line; a sign bit current comparison unit, including a sign bit current input terminal and a data output terminal, the sign bit current input terminal is used to be electrically connected to the sign bit line, and the sign bit current comparison unit is electrically connected to the positive weight current output terminal, the negative weight low bit current output terminal and the negative weight high bit current output terminal; the data bit current generation unit is used to divide the bit line current of the data bit line into mirror currents based on weights; the sign bit current comparison unit is used to output mirror currents of different weights according to the size of the bit line current of the sign bit line. The data bit current representing the data is mirrored into a positive weight mirror current, a negative weight low bit mirror current and a negative weight high bit mirror current through the set data bit current generation unit. The sign bit current comparison unit outputs different weight mirror currents based on the size of the sign bit current representing the sign. The data bit current representing the data is mirrored into mirror currents of different weights through the data bit current generation unit. The sign bit current comparison unit determines whether the signed data is positive weighted or negative weighted, and outputs mirror currents of different weights based on the positive weight or negative weight of the sign data. The above circuit completes the complement calculation of the sign data by setting only two functional units, shortens the current path, improves the operating efficiency of the complement calculation, and reduces the power consumption of the RRAM storage and computing system. BRIEF DESCRIPTION OF THE DRAWINGS

[0073] Various other advantages and benefits will become apparent to those skilled in the art upon reading the detailed description of the preferred embodiments below. The accompanying drawings are for illustration purposes only and are not to be considered as limiting the present application. The same reference numerals are used throughout the accompanying drawings to denote the same components. In the accompanying drawings:

[0074] Figure 1A schematic structural block diagram of a complement calculation unit circuit based on a resistive random access memory provided in an embodiment of the present application;

[0075] Figure 2 A schematic structural block diagram of another complementary code calculation unit circuit based on resistive memory provided in an embodiment of the present application;

[0076] Figure 3 A schematic structural block diagram of another complementary code calculation unit circuit based on resistive memory provided in an embodiment of the present application;

[0077] Figure 4 A schematic structural block diagram of another complementary code calculation unit circuit based on resistive memory provided in an embodiment of the present application;

[0078] Figure 5 A schematic structural block diagram of a complement calculation unit circuit based on a resistive random access memory provided in an embodiment of the present application;

[0079] Figure 6 A schematic structural block diagram of a complement calculation unit circuit based on a resistive random access memory provided in an embodiment of the present application;

[0080] Figure 7 A schematic flowchart of a method for calculating a complement of a resistive random access memory is provided in an embodiment of the present application. DETAILED DESCRIPTION

[0081] In order to better understand the technical solutions provided by the embodiments of this specification, the technical solutions of the embodiments of this specification are described in detail below through the accompanying drawings and specific embodiments. It should be understood that the embodiments of this specification and the specific features in the embodiments are detailed descriptions of the technical solutions of the embodiments of this specification, rather than limitations on the technical solutions of this specification. In the absence of conflict, the embodiments of this specification and the technical features in the embodiments can be combined with each other.

[0082] In this article, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also include elements inherent to such process, method, article or equipment. In the absence of further restrictions, the elements defined by the statement "comprising a ..." do not exclude the presence of other identical elements in the process, method, article or equipment comprising the elements. The term "two or more" includes two or more than two cases.

[0083] In order to break through the traditional von Neumann architecture and improve processor performance, in-memory computing is an effective approach. RRAM has attracted widespread attention and application in the field of in-memory computing due to its high integration and low power consumption. However, existing RRAM-based complement calculation circuits have too many functional modules and too long current paths, resulting in low operating efficiency and high energy consumption.

[0084] In view of this, the present application provides a complement calculation unit circuit based on resistive random access memory that can at least solve the above problems.

[0085] See also Figure 1 , which is a schematic structural block diagram of a complement calculation unit circuit based on resistive memory provided in an embodiment of the present application.

[0086] like Figure 1 As shown, the above circuit includes:

[0087] The data bit current generating unit includes a data bit current input terminal, a positive weight current output terminal, a negative weight low bit current output terminal and a negative weight high bit current output terminal.

[0088] The data bit current input terminal is used for being electrically connected to the data bit line;

[0089] The sign bit current comparison unit includes a sign bit current input terminal and a data output terminal.

[0090] The sign bit current input terminal is used to be electrically connected to the sign bit line.

[0091] The sign bit current comparison unit is electrically connected to the positive weight current output terminal, the negative weight low bit current output terminal and the negative weight high bit current output terminal;

[0092] The data bit current generating unit is used for dividing the bit line current of the data bit line into a mirror current based on the weight;

[0093] The sign bit current comparison unit is used to output mirror currents with different weights according to the magnitude of the bit line current of the sign bit bit line.

[0094] For example, combined Figure 1 , the data bit current generating unit 100 can generate the data bit current I BLD Mirrored into a positive weight mirror current I LSBP , negative weight low-bit mirror current I LSBN and negative weight high-order mirror current I MSBN , the above data bit current I BLDThe data bit current generating unit 100 is electrically connected to the data bit line. It can be explained that the signed data includes a sign bit and a data bit. When the sign bit is a positive weight, the complement of the signed data is itself. When the sign bit is a negative weight, the complement of the signed data is the inverse of the data bit and then added 1. The data bit current generating unit 100 divides the data bit current into a positive weight mirror current I according to the positive and negative weights. LSBP , negative weight low-bit mirror current I LSBN and negative weight high-order mirror current I MSBN The sign bit current comparison unit 200 can determine whether the signed data is positive weighted or negative weighted according to the size of the sign bit current, and output the data bit current I with weight based on whether the sign data is positive weighted or negative weighted. SUM , the above weighted data bit current I SUM The positive weight mirror current I LSBP , negative weight low-bit mirror current I LSBN and negative weight high-order mirror current I MSBN produce.

[0095] The embodiment of the present application provides a complement calculation unit circuit based on resistive random access memory, in which the data bit current representing the data is mirrored into mirror currents of different weights by a data bit current generation unit, and the sign bit current comparison unit determines whether the signed data is positively weighted or negatively weighted, and outputs mirror currents of different weights based on the positive or negative weight of the sign data. The above circuit completes the complement calculation of the sign data by setting only two functional units, shortening the current path, improving the operating efficiency of the complement calculation, and reducing the power consumption of the RRAM storage and computing system.

[0096] According to some embodiments, the sign bit current comparison unit includes:

[0097] A current comparator comprising a first level output terminal and a second level output terminal;

[0098] The first level trigger switch K1 is electrically connected to the positive weight current output terminal.

[0099] The first level trigger switch K1 is electrically connected to the second level output terminal;

[0100] The second level trigger switch K2 is electrically connected to the negative weight low current output terminal.

[0101] The second level trigger switch K2 is electrically connected to the first level output terminal;

[0102] The third level trigger switch K3 is electrically connected to the negative weight high current output terminal.

[0103] The third level trigger switch K3 is electrically connected to the first level output end;

[0104] The shunt circuit includes a first current inflow terminal and a second current inflow terminal,

[0105] The first current inflow terminal is electrically connected to the first level trigger switch K1 and the third level trigger switch K3.

[0106] The second current inflow terminal is electrically connected to the second level trigger switch K2.

[0107] The shunt circuit is used to shunt the mirror current according to the on-off status of the level-triggered switch.

[0108] For example, the embodiment of the present application provides a schematic structural block diagram of another complementary code calculation unit circuit based on resistive memory, such as Figure 2 As shown, the sign bit current comparison unit includes a current comparator 210, a shunt circuit 220, and a first level trigger switch K1, a second level trigger switch K2, and a third level trigger switch K3. The first level output terminal of the current comparator 210 is electrically connected to K2 and K3, and the second level output terminal is electrically connected to K1. K1 and K3 are connected to the first current inflow terminal of the shunt circuit 220, and K2 is connected to the second current inflow terminal of the shunt circuit 220. K1, K2, and K3 are electrically connected to the positive weight current output terminal, the negative weight low-bit current output terminal, and the negative weight high-bit current output terminal, respectively. It should be noted that the above-mentioned current comparator can be a single-ended input current comparator, which is not specifically limited.

[0109] It can be explained that, for the sake of convenience, an example is given, where the symbol is the current I BLS When the current is greater than the threshold current of the current comparator 210, the first level output terminal outputs a high level, the second level output terminal outputs a low level, K2 and K3 are closed, and K1 is disconnected. At this time, the positive weight mirror current I LSBP The branch is disconnected, and the negative weight low current I LSBN Flowing into the shunt circuit 220, the negative weighted high current I MSBN A portion of the current flows into the shunt circuit 220, and the magnitude of the current flowing into the shunt circuit 220 is the same as I LSBN The magnitudes of the weighted data bit current I SUM The value of I MSBN Subtract I LSBN , that is to say, the output data bit current is the data bit current with negative weight.

[0110] The symbol is the current I BLSWhen the current is less than the threshold current of the current comparator 210, the first level output terminal outputs a low level, the second level output terminal outputs a high level, K2 and K3 are disconnected, and K1 is closed. At this time, the negative weight low current I LSBN and negative weight high current I MSBN The branch is disconnected, and the data bit current I SUM The value is the positive weight mirror current I LSBP , that is to say, the output data bit current is a positive weighted data bit current.

[0111] According to some embodiments, the data bit current generating unit includes:

[0112] The first current mirror circuit includes an input-side PMOS transistor M P0 and the first mirror side PMOS tube M P1 , the second mirror side PMOS tube M P2 , the third mirror side PMOS tube M P3 ,

[0113] M P0 、M P1 、M P2 and M P3 The source is used to be electrically connected to the power supply terminal,

[0114] M P0 The gate and M P1 、M P2 、M P3 The gate is electrically connected to

[0115] M P0 The drain and gate are short-circuited.

[0116] M P0 The drain is used to be electrically connected to the data bit line.

[0117] M P1 The drain is electrically connected to the first level trigger switch K1,

[0118] M P2 The drain is electrically connected to the second level trigger switch K2,

[0119] M P3 The drain is electrically connected to the third level trigger switch K3.

[0120] For example, Figure 3 or Figure 5 As shown, the data bit current unit includes an input side PMOS tube M P0 and the first mirror side PMOS tube M P1 , the second mirror side PMOS tube M P2 , the third mirror side PMOS tube M P3, M P0 The data bit current I BLD Mirror to M respectively P1 、M P2 and M P3 In the branch, M P1 The positive weight mirror current I LSBP , M P2 The negative weight low-order mirror current I flows through LSBN , M P3 The negative weight high-order mirror current I MSBN .

[0121] It can be explained that the data bit current generation unit includes a current mirror circuit on multiple mirror sides, which can ensure the stability of the output current, that is, the weighted mirror current, and can also change with the change of the input side current, thereby improving the adaptability of the complement calculation unit circuit based on resistive memory provided in the embodiment of the present application.

[0122] According to some embodiments, the data bit current generating unit includes:

[0123] The first current mirror circuit includes an input-side PMOS transistor M P0 and M P4 , the first mirror side PMOS tube M P1 and M P5 , the second mirror side PMOS tube M P2 and M P6 , the third mirror side PMOS tube M P3 and M P7 ,

[0124] M P0 、M P1 、M P2 and M P3 The source is used to be electrically connected to the power supply terminal,

[0125] M P0 The gate and M P1 、M P2 and M P3 The gate is electrically connected to

[0126] M P0 The gate and M P4 The drain is electrically connected to

[0127] M P4 The gate and M P5 、M P6 、M P7 The gate is electrically connected to

[0128] M P4 The drain is electrically connected to the data bit line,

[0129] M P5 The drain is electrically connected to the first level trigger switch K1,

[0130] M P6 The drain is electrically connected to the second level trigger switch K2,

[0131] M P7 The drain is electrically connected to the third level trigger switch K3.

[0132] For example, Figure 4 or Figure 6 As shown, the data bit current generating unit includes an input side PMOS tube M P0 and M P4 , the first mirror side PMOS tube M P1 and M P5 , the second mirror side PMOS tube M P2 and M P6 , the third mirror side PMOS tube M P3 and M P7 , you can P4 、M P5 、M P6 and M P7 The gate of M is set to bias voltage to meet the working conditions of the current mirror circuit. P1 and M P5 The branch flows through the positive weight mirror current I LSBP , M P2 and M P6 The branch flows through the negative weight low-order mirror current I LSBN , M P3 and M P7 The negative weight high-order mirror current I MSBN .

[0133] It can be explained that the data bit current generation unit includes a cascode (common source and common gate) current mirror circuit on multiple mirror sides, which effectively reduces the influence of the channel length modulation coefficient on the mirror current compared to a single-layer current mirror circuit, and improves the stability of the weighted data bit current.

[0134] According to some embodiments, the shunt circuit includes:

[0135] The second current mirror circuit includes an input side NMOS tube M N3 and the mirror side NMOS tube M N2 ,

[0136] M N3 and M N2 The source is used to be electrically connected to the ground terminal,

[0137] M N3The drain and gate are short-circuited.

[0138] M N3 The drain is electrically connected to the second level trigger switch K2,

[0139] M N2 The drain is electrically connected to the first level trigger switch K1 and the third level trigger switch K3.

[0140] For example, Figure 3 or Figure 4 As shown, the shunt circuit includes an input side NMOS tube M N3 and the mirror side NMOS tube M N2 , M N3 The drain of M is electrically connected to the second level trigger switch K2. N2 The drain is electrically connected to the first level trigger switch K1 and the third level trigger switch K3.

[0141] It can be explained that, in the current comparator, the sign bit current I BLS When the current is greater than the threshold value, the first level output terminal outputs a high level, K2 and K3 are closed, the second level output terminal outputs a low level, K1 is disconnected, and the positive weight mirror current I LSBP The branch is disconnected, M N3 On, negative weight low mirror current I LSBN M N3 Flowing into the ground terminal GND, the negative weight high-order mirror current I MSBN Part of the M N2 Flowing into the ground terminal GND, it can be understood that M N2 and M N3 The channel width-to-length ratio is set to 1:1, so that the negative weight high-bit mirror current I MSBN Flowing through M N2 The current is the same as the negative weight low mirror current I LSBN The same size, so the weighted data bit current I SUM The value of can be the negative weight high mirror current I MSBN With the negative weight low mirror current I LSBN That is to say, the output data bit current is the data bit current with negative weight.

[0142] In the current comparator, the sign bit current I BLS When the current is less than the threshold value, the first level output terminal outputs a low level, K2 and K3 are disconnected, the second level output terminal outputs a high level, K1 is closed, and the negative weight low-bit mirror current I LSBN and negative weight high-order mirror current I MSBN The branch is disconnected, and the data bit current I SUMThe value of can be the positive weight mirror current I LSBP , that is to say, the output data bit current is a positive weighted data bit current.

[0143] By setting the shunt unit as a current mirror circuit, when the sign data has a negative weight, it can be ensured that the branch current flowing out of the negative weight high-bit mirror current is the same as the negative weight low-bit mirror current, so that the weighted data bit current output can be the difference between the negative weight high-bit mirror current and the negative weight low-bit mirror current.

[0144] According to some embodiments, the shunt circuit includes:

[0145] The second current mirror circuit includes an input side NMOS tube M N1 and M N3 and the mirror side NMOS tube M N0 and M N2 ,

[0146] M N3 and M N2 The source is used to be electrically connected to the ground terminal,

[0147] M N1 The drain and M N3 The gate is electrically connected to

[0148] M N1 The drain is electrically connected to the second level trigger switch K2,

[0149] M N0 The drain is electrically connected to the first level trigger switch K1 and the third level trigger switch K3.

[0150] For example, Figure 5 or Figure 6 As shown, the shunt circuit includes an input side NMOS tube M N1 and M N3 and the mirror side NMOS tube M N0 and M N2 , M N1 The drain of M is electrically connected to the second level trigger switch K2. N0 The drain of M is electrically connected to the first level trigger switch K1 and the third level trigger switch K3. N0 The gate and M N1 A bias voltage is set between the gates to meet the working conditions of the current mirror circuit.

[0151] It can be explained that the shunt circuit includes a cascode (common source and common gate) current mirror circuit, which effectively reduces the influence of the channel length modulation coefficient on the mirror current compared to the single-layer current mirror circuit. When the sign data is a negative weight, the negative weight high-bit mirror is transmitted through M. N0、M N2 The stability of the current flowing into the ground terminal is increased, thereby improving the stability of the current of the weighted data bits.

[0152] According to some embodiments, M P1 、M P2 and M P3 The channel width-to-length ratio is 1:1:2.

[0153] For example, Figures 3 to 6 As shown, because the flow through M P1 、M P2 and M P3 The current in the branch passes through M P0 The image is generated and flows through M P1 The mirror current is the positive weight mirror current I LSBP , flows through M P2 The mirror current is the negative weight low-order mirror current I LSBN , flows through the negative weight high-order mirror current I MSBN , M P1 、M P2 and M P3 The channel width-to-length ratio is set to 1:1:2, that is, the positive weight mirror current I LSBP , negative weight low-bit mirror current I LSBN and negative weight high-order mirror current I MSBN The size is set to 1:1:2.

[0154] It can be explained that when the signed data has a positive weight, the output data bit current I SUM The magnitude is the positive weight mirror current I LSBP , when the signed data has a negative weight, the output weighted data bit current I SUM is the negative weight high-order mirror current I MSBN With the negative weight low mirror current I LSBN The difference between the positive weight mirror current I LSBP , negative weight low-bit mirror current I LSBN and negative weight high-order mirror current I MSBN The size is set to 1:1:2, which ensures that the data bit current I with weight is the same regardless of whether the signed data has positive weight or negative weight. SUM The values ​​are the same.

[0155] In a second aspect, an embodiment of the present application provides a method for calculating a complement based on a resistive random access memory, which is used in the circuit described in any one of the first aspects, and may specifically include S110-S130:

[0156] S110, using a data bit current generating unit to generate a mirror current based on a weight from a bit line current of a data bit line,

[0157] Exemplarily, the mirror current includes a positive weight mirror current, a negative weight low bit mirror current and a negative weight high bit mirror current. The data bit current generation unit can mirror the bit line current representing the data bit into a positive weight mirror current, a negative weight low bit mirror current and a negative weight high bit mirror current based on the positive and negative weights.

[0158] S120, using a sign bit current comparison unit to compare the current of the sign bit line with a threshold current;

[0159] Exemplarily, the threshold current can be a reference current, which can be provided by an external circuit or generated by a sign bit current comparison unit, without limitation. The sign bit current comparison unit compares the bit line current representing the sign bit with the threshold current to determine whether the signed data has a positive weight or a negative weight.

[0160] S130 , based on the comparison result, controlling the sign bit current comparison unit to output the mirror current.

[0161] Exemplarily, the sign bit current comparison unit is controlled to output a mirror current based on the magnitude relationship between the bit line current of the sign bit and the threshold current. The mirror current may be a weighted mirror current mirrored by the data bit current generation unit.

[0162] According to the aforementioned embodiment, a method for calculating the two's complement in a resistive random access memory (RRAM) is provided. A data bit current generation unit generates a mirror current based on the weight of the data bit line current. A sign bit current comparison unit compares the current of the sign bit line with a threshold current. Based on the comparison result, the sign bit current comparison unit is controlled to output the mirror current. This method can complete the two's complement calculation of the sign data with only two functional units, shortening the current path, improving the efficiency of the two's complement calculation, and reducing the power consumption of the RRAM storage and computing system.

[0163] According to some embodiments, controlling the sign bit current comparison unit to output the mirror current based on the comparison result includes:

[0164] When the comparison result shows that the current of the sign bit line is less than the threshold current, the sign bit current comparison unit is controlled to output a positive weighted mirror current;

[0165] When the comparison result shows that the current of the sign bit line is greater than the threshold current, the sign bit current comparison unit is controlled to output the difference between the negative weighted high bit mirror current and the negative weighted low bit mirror current.

[0166] For example, if the comparison result shows that the current of the sign bit line is less than the threshold current, it indicates that the signed data has a positive weight, and the sign bit current comparison unit can be controlled to output a positive weight mirror current. If the comparison result shows that the current of the sign bit line is greater than the threshold current, it indicates that the signed data has a negative weight, and the sign bit current comparison unit can be controlled to output the difference between the negative weight high bit mirror current and the negative weight low bit mirror current.

[0167] In a third aspect, an embodiment of the present application provides a storage and computing device based on resistive random access memory, the device comprising:

[0168] A resistive switching memory array and a circuit as described above in any one of the first aspects.

[0169] Illustratively, an embodiment of the present application provides a storage and computing device based on resistive random access memory, including the above-mentioned complement calculation unit circuit. The above-mentioned circuit can make the data bit current representing the data mirrored into mirror currents of different weights through the data bit current generation unit, and judge whether the signed data is positive weighted or negative weighted through the sign bit current comparison unit, and output mirror currents of different weights based on the positive weight or negative weight of the sign data. The above-mentioned circuit completes the complement calculation of the sign data only through the setting of two functional units, shortens the current path, improves the operating efficiency of the complement calculation, and reduces the power consumption of the RRAM storage and computing system.

[0170] Although the preferred embodiments of this specification have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of this specification.

[0171] Obviously, those skilled in the art may make various changes and modifications to this specification without departing from the spirit and scope of this specification. Thus, if such changes and modifications fall within the scope of the claims of this specification and their equivalents, this specification is intended to include such changes and modifications.

Claims

1. A complement calculation unit circuit based on resistive random access memory, characterized in that: include: A data bit current generating unit, the data bit current generating unit comprising a data bit current input terminal, a positive weight current output terminal, a negative weight low bit current output terminal and a negative weight high bit current output terminal, The data bit current input terminal is used to be electrically connected to the data bit line; A sign bit current comparison unit, the sign bit current comparison unit comprising a sign bit current input terminal and a data output terminal, The sign bit current input terminal is used to be electrically connected to the sign bit line, The sign bit current comparison unit is electrically connected to the positive weight current output terminal, the negative weight low bit current output terminal and the negative weight high bit current output terminal; The data bit current generating unit is used to divide the bit line current of the data bit line into mirror currents based on weights; The sign bit current comparison unit is configured to output the mirror currents with different weights according to the bit line current of the sign bit bit line.

2. The circuit according to claim 1, wherein: The sign bit current comparison unit includes: A current comparator, the current comparator comprising a first level output terminal and a second level output terminal; A first level-triggered switch K1 is electrically connected to the positive weighted current output terminal. The first level trigger switch K1 is electrically connected to the second level output end; A second level trigger switch K2 is electrically connected to the negative weight low current output terminal. The second level trigger switch K2 is electrically connected to the first level output end; A third level trigger switch K3 is electrically connected to the negative weight high current output terminal. The third level trigger switch K3 is electrically connected to the first level output end; A shunt circuit, the shunt circuit comprising a first current inflow end and a second current inflow end, The first current inflow end is electrically connected to the first level trigger switch K1 and the third level trigger switch K3. The second current inflow end is electrically connected to the second level trigger switch K2, The shunt circuit is used to shunt the mirror current according to the on-off status of the level-triggered switch.

3. The circuit according to claim 2, characterized in that The data bit current generating unit includes: The first current mirror circuit includes an input-side PMOS transistor M P0 and the first mirror side PMOS tube M P1 , the second mirror side PMOS tube M P2 , the third mirror side PMOS tube M P3 , The M P0 、The M P1 、The M P2 and the M P3 The source is used to be electrically connected to the power supply terminal, The M P0 The gate and the M P1 、The M P2 、The M P3 The gate is electrically connected to The M P0 The drain and gate are short-circuited. The M P0 The drain is electrically connected to the data bit line, The M P1 The drain is electrically connected to the first level trigger switch K1, The M P2 The drain is electrically connected to the second level trigger switch K2, The M P3 The drain is electrically connected to the third level triggered switch K3.

4. The circuit according to claim 2, characterized in that The data bit current generating unit includes: The first current mirror circuit includes an input-side PMOS transistor M P0 and M P4 , the first mirror side PMOS tube M P1 and M P5 , the second mirror side PMOS tube M P2 and M P6 , the third mirror side PMOS tube M P3 and M P7 , The M P0 、The M P1 、The M P2 and the M P3 The source is used to be electrically connected to the power supply terminal, The M P0 The gate and the M P1 、The M P2 and the M P3 The gate is electrically connected to The M P0 The gate and the M P4 The drain is electrically connected to The M P4 The gate and the M P5 、The M P6 、The M P7 The gate is electrically connected to The M P4 The drain is electrically connected to the data bit line, The M P5 The drain is electrically connected to the first level trigger switch K1, The M P6 The drain is electrically connected to the second level trigger switch K2, The M P7 The drain is electrically connected to the third level triggered switch K3.

5. The circuit according to claim 3 or 4, characterized in that The shunt circuit comprises: The second current mirror circuit includes an input-side NMOS transistor M N3 and the mirror side NMOS tube M N2 , The M N3 and the M N2 The source is used to be electrically connected to the ground terminal, The M N3 The drain and gate are short-circuited. The M N3 The drain is electrically connected to the second level trigger switch K2, The M N2 The drain is electrically connected to the first level trigger switch K1 and the third level trigger switch K3.

6. The circuit according to claim 3 or 4, characterized in that The shunt circuit comprises: The second current mirror circuit includes an input-side NMOS transistor M N1 and M N3 and the mirror side NMOS tube M N0 and M N2 , The M N3 and the M N2 The source is used to be electrically connected to the ground terminal, The M N1 The drain and the M N3 The gate is electrically connected to The M N1 The drain is electrically connected to the second level trigger switch K2, The M N0 The drain is electrically connected to the first level trigger switch K1 and the third level trigger switch K3.

7. The circuit according to claim 3 or 4, characterized in that The M P1 、The M P2 and the M P3 The channel width-to-length ratio is 1:1:

2.

8. A method for calculating a complement based on a resistive random access memory, characterized in that: For use in a circuit as claimed in any one of claims 1 to 7, the method comprising: Using a data bit current generating unit to generate a mirror current based on the weight of the bit line current of the data bit, wherein the mirror current includes a positive weight mirror current, a negative weight low bit mirror current and a negative weight high bit mirror current; Comparing the current of the sign bit line with the threshold current using a sign bit current comparison unit; Based on the comparison result, the sign bit current comparison unit is controlled to output the mirror current.

9. The method according to claim 8, characterized in that The step of controlling the sign bit current comparison unit to output the mirror current based on the comparison result includes: When the comparison result shows that the current of the sign bit line is less than the threshold current, controlling the sign bit current comparison unit to output the positive weighted mirror current; When the comparison result shows that the current of the sign bit line is greater than the threshold current, the sign bit current comparison unit is controlled to output the difference between the negative weighted high bit mirror current and the negative weighted low bit mirror current.

10. A storage and computing device based on resistive random access memory, characterized in that: include: A resistive memory array and a circuit as claimed in any one of claims 1 to 7.

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