Electronic package and method of making the same

Abstract

The present application discloses an electronic package and its manufacturing method. The electronic package comprises a functional pad, a surface treatment layer formed on a part of the surface of the functional pad, and an electronic component. The electronic component is contacted and combined with the functional pad and the surface treatment layer through a bonding layer. The surface treatment layer of the electronic package has a buffering effect when the electronic package is subjected to cold and hot impact, thereby improving the packaging reliability of the electronic package.

Description

Technical Field

[0001] This invention relates to a semiconductor packaging structure and its process, and more particularly to an electronic package that can improve packaging reliability and its manufacturing method. Background Technology

[0002] With the booming development of the electronics industry, electronic products are gradually moving towards multifunctionality and high performance. In order to meet the packaging requirements of miniaturization of electronic packaging structures, wafer-level packaging (WLP) or chip-scale packaging (CSP) technologies have been developed.

[0003] Figure 1A This is a cross-sectional schematic diagram of an existing CSP semiconductor package. (Example:) Figure 1A As shown, in the process of the semiconductor package 1, a copper pad 10 and a plurality of electrical contact pads 11 are formed on a carrier (not shown). Adhesive 13 is then applied to the copper pad 10 to bond the semiconductor chip 12 to the copper pad 10, and conductive pillars 14 are formed on the plurality of electrical contact pads 11. Next, the semiconductor chip 12, the copper pad 10, the electrical contact pads 11 and the conductive pillars 14 are covered by an encapsulation layer 15. After that, a circuit structure 16 is formed on the encapsulation layer 15 so that the circuit structure 16 electrically connects the conductive pillars 14 and the semiconductor chip 12. Finally, the carrier is removed.

[0004] However, in the existing semiconductor package 1, the adhesive 13 is located between the copper pad 10 and the semiconductor chip 12. Since the copper pad 10 and the semiconductor chip 12 are rigid materials of different materials, while the adhesive 13 is a flexible material, the bonding between the upper and lower sides of the adhesive 13 is prone to unidirectional abnormality due to thermal expansion and contraction during the process. This results in poor adhesion between the copper pad 10 and the adhesive 13, making it easy for the semiconductor chip 12 to shift or even fall off at the weak bonding interface of the adhesive 13, leading to reliability problems in the semiconductor package 1.

[0005] Furthermore, the industry has thus formed a reinforcing layer 18 on the entire top surface of the copper pad 10, such as other metal materials (e.g., electroplated nickel-gold, electroplated silver, or chemically deposited non-copper metal materials, etc.). Figure 1B As shown, this is done to strengthen the bond between the semiconductor chip 12 and the adhesive 13, but it also makes the adhesive 13 relatively weak on the semiconductor chip 12 side, resulting in reliability problems between the semiconductor chip 12 and the adhesive 13 (e.g., separation between the semiconductor chip 12 and the adhesive 13 under thermal shock processes). Furthermore, adding the reinforcing layer 18 will increase production costs.

[0006] Therefore, overcoming the various problems of the existing technologies has become a pressing issue that the industry urgently needs to address. Summary of the Invention

[0007] In view of the various shortcomings of the prior art, the purpose of the present invention is to provide an electronic package and its manufacturing method, which can improve the packaging reliability of the electronic package.

[0008] The electronic package of the present invention includes: a patterned metal layer including at least one functional pad and a first circuit layer; a surface treatment layer disposed on a portion of the surface of the functional pad; a bonding layer disposed on the functional pad and the surface treatment layer; an electronic component disposed on the bonding layer and bonded to the functional pad and the surface treatment layer by the bonding layer, and the electronic component having a plurality of electrical connection pads; an encapsulation layer covering the electronic component and the patterned metal layer, and exposing a portion of the bottom surface of the first circuit layer to the encapsulation layer as an external pad; and an add-in circuit structure bonded to the encapsulation layer and electrically connecting the electrical connection pads of the electronic component and the first circuit layer.

[0009] In the aforementioned electronic package, the surface treatment layer is uniformly or non-uniformly distributed on a portion of the surface of the functional pad.

[0010] In the aforementioned electronic package, the functional pad and the surface treatment layer are made of different metal materials.

[0011] In the aforementioned electronic package, the bonding layer is a conductive adhesive or an insulating adhesive.

[0012] In the aforementioned electronic package, the added-layer circuitry structure electrically connects the electrical connection pads of the electronic component via fan-out conductors. For example, the fan-out conductor is formed as a column adapted to the geometry of the electrical connection pads of the electronic component.

[0013] The present invention also provides a method for manufacturing an electronic package, comprising: providing a carrier having at least a metal surface; electroplating a patterned metal layer on the carrier using a patterned exposure and development method, wherein the patterned metal layer includes at least one functional pad and a first circuit layer; forming a surface treatment layer on a portion of the surface of the functional pad; forming a bonding layer on the functional pad and the surface treatment layer; attaching an electronic component on the bonding layer, wherein the electronic component has a plurality of electrical connection pads; forming a plurality of conductive pillars on a portion of the first circuit layer using a patterned exposure and development method; covering the electronic component and the plurality of conductive pillars with an encapsulation layer; electroplating a second circuit layer on the encapsulation layer using a patterned exposure and development method to electrically connect the electronic component and the plurality of conductive pillars; and removing the carrier to expose a portion of the bottom surface of the first circuit layer as an external pad.

[0014] In the aforementioned manufacturing method, the surface treatment layer is formed uniformly or non-uniformly on a portion of the surface of the functional pad.

[0015] In the aforementioned manufacturing method, the functional pad and the surface treatment layer are made of different metal materials.

[0016] The aforementioned manufacturing method also includes simultaneously forming columnar fan-out conductors on the electrical connection pads of the electronic component while forming the plurality of conductive pillars. For example, the fan-out conductor is a pillar adapted to the geometry of the electrical connection pads of the electronic component.

[0017] The aforementioned manufacturing method also includes, after forming the encapsulation layer, using laser to open holes to expose the electrical connection pad of the electronic component, and simultaneously forming conductive blind vias when forming the second circuit layer, so that the conductive blind vias electrically connect the second circuit layer and the electrical connection pad of the electronic component.

[0018] As can be seen from the above, the electronic package and its manufacturing method of the present invention mainly rely on the formation of a surface treatment layer on a portion of the surface of the functional pad, so that the bonding layer can contact two different materials (the surface treatment layer and the functional pad). Therefore, compared with the prior art, the surface treatment layer of the electronic package of the present invention has a buffering effect when subjected to thermal shock, thereby improving the reliability of the electronic package.

[0019] Furthermore, compared to existing copper pads with a reinforcing layer applied to the entire top surface, the method of this invention forms a surface treatment layer only on a portion of the functional pad surface, thus reducing production costs. Attached Figure Description

[0020] Figure 1A This is a cross-sectional schematic diagram of an existing semiconductor package.

[0021] Figure 1B This is a cross-sectional schematic diagram of another existing semiconductor package.

[0022] Figures 2A to 2G This is a cross-sectional schematic diagram of the electronic package of the present invention.

[0023] Figure 2E-1 for Figure 2E A cross-sectional schematic diagram of another embodiment.

[0024] Figure 2G-1 for Figure 2G A cross-sectional schematic diagram of another embodiment.

[0025] Figure 2H This is a cross-sectional schematic diagram of another embodiment of the electronic package of the present invention and its application.

[0026] Figures 3A to 3C for Figure 2BA partial top-view diagram.

[0027] The attached figures are labeled as follows:

[0028] 1: Semiconductor package

[0029] 10: Copper Pad

[0030] 11: Electrical contact pad

[0031] 12: Semiconductor chips

[0032] 13: Adhesive

[0033] 14, 24, 34: Conductive pillars

[0034] 15, 25: Encapsulation layer

[0035] 16: Circuit Structure

[0036] 18: Reinforcement Layer

[0037] 2,2a: Electronic package

[0038] 20: Functional Pad

[0039] 21: First Line Layer

[0040] 22: Electronic components

[0041] 22a: Surface of Action

[0042] 22b: Non-acting surface

[0043] 220: Electrical connection pad

[0044] 23: Bonding layer

[0045] 24a: End face

[0046] 25a: First surface

[0047] 25b: Second surface

[0048] 250: Through hole

[0049] 251: Opening

[0050] 26,261: Second line layer

[0051] 26a, 26b: Add-on circuit structure

[0052] 260: Dielectric layer

[0053] 262,36: Conductive blind vias

[0054] 27: Conductive elements

[0055] 28: Surface treatment layer

[0056] 29: Fan-out conductor

[0057] 8: Electronic devices

[0058] 9: Load-bearing components

[0059] 90: Release layer Detailed Implementation

[0060] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

[0061] It should be understood that the structures, proportions, sizes, etc., shown in the accompanying drawings are only for illustrative purposes to aid those skilled in the art in understanding and reading the content disclosed herein, and are not intended to limit the conditions under which the invention can be implemented. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to the size, without affecting the effects and objectives achieved by the invention, should still fall within the scope of the technical content disclosed herein. Furthermore, the terms such as "first," "second," "above," and "a" used in this specification are merely for clarity of description and are not intended to limit the scope of the invention. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of the invention's implementation.

[0062] Figures 2A to 2G This is a cross-sectional schematic diagram illustrating the manufacturing method of the electronic package 2 of the present invention.

[0063] like Figure 2A As shown, a carrier 9 having at least a metal surface is provided, and a patterned metal layer including at least one functional pad 20 and a first circuit layer 21 is formed on the carrier 9.

[0064] In this embodiment, the carrier 9 is, for example, a copper foil substrate, on which the first circuit layer 21 and the functional pad 20 are disposed on the copper material of the copper foil substrate, and a release layer 90 may be formed on the carrier 9 as required, on which the first circuit layer 21 and the functional pad 20 are disposed.

[0065] Furthermore, the first circuit layer 21 and the functional pad 20 are fabricated simultaneously using a patterned exposure and development method. For example, a patterned copper layer is formed on the copper foil substrate (or the release layer 90) by electroplating or other methods, so that the patterned copper layer includes the first circuit layer 21 and the functional pad 20. Specifically, the electroplating process uses a redistribution layer (RDL) process to fabricate the first circuit layer 21 and the functional pad 20.

[0066] like Figure 2B As shown, a selective metallization process is performed on a portion of the top surface of the functional pad 20 to form a surface treatment layer 28.

[0067] In this embodiment, the material of the functional pad 20 is different from the material of the surface treatment layer 28. For example, the functional pad 20 and the surface treatment layer 28 are made of different metals. Specifically, the material forming the surface treatment layer 28 is one of the alloys or multilayer metals of the group consisting of silver, nickel, palladium, and gold, such as electroplated nickel / gold, electroless nickel / gold, immersion nickel in gold (ENIG), immersion nickel in palladium in gold (ENEPIG), electroless tin plating, etc., but not limited to the above.

[0068] Furthermore, the surface treatment layer 28 is formed uniformly or non-uniformly on a portion of the surface of the functional pad 20. For example, the surface treatment layer 28 can be arranged in at least one sheet (e.g., Figure 3A As shown), multi-point (such as) Figure 3B (as shown in the dot pattern) or other patterns (such as) Figure 3C As shown in the grid pattern, only a portion of the surface of the functional pad 20 needs to be exposed (or the top surface of the functional pad 20 not completely covered).

[0069] like Figure 2C As shown, a bonding layer 23 is formed on the functional pad 20 and the surface treatment layer 28, and an electronic component 22 is attached to the bonding layer 23 so that the electronic component 22 is disposed on the functional pad 20 and the surface treatment layer 28 through the bonding layer 23, and the bonding layer 23 covers the surface treatment layer 28 so that the bonding layer 23 simultaneously contacts the functional pad 20 and the surface treatment layer 28.

[0070] In this embodiment, the electronic component 22 is an active component, a passive component, or a combination of both. The active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor, or an inductor. For example, the electronic component 22 is a semiconductor chip with opposing active surfaces 22a and non-active surfaces 22b. The active surface 22a has a plurality of electrical connection pads 220, and the electronic component 22 is fixed to the functional pad 20 and the surface treatment layer 28 by means of the bonding layer 23 via its non-active surface 22b.

[0071] Furthermore, the bonding layer 23 is an insulating adhesive or a conductive adhesive such as silver paste, which adheres to the two metal materials (i.e., the functional pad 20 and the surface treatment layer 28). This allows the bonding interface of the bonding layer 23 to have a buffering effect, ensuring that the bonding layer 23 and the functional pad 20 can pass the reliability test. For example, the adhesive of the bonding layer 23 can only harden at high temperatures, but at high temperatures, the copper material of the functional pad 20 is prone to oxidation, causing the functional pad 20 to deteriorate and affecting its adhesion to the bonding layer 23. Therefore, by forming a metal material (i.e., the surface treatment layer 28) suitable for bonding the bonding layer 23 on the functional pad 20, the surface treatment layer 28 has a buffering effect during the reliability test, thus avoiding quality deterioration.

[0072] In addition, the functional pad 20 serves not only as a die-placement pad but also as a heat dissipation pad for the electronic component 22.

[0073] like Figure 2D As shown, a plurality of conductive pillars 24 are formed on at least a portion of the first circuit layer 21 by patterned exposure and development.

[0074] In this embodiment, the material forming the plurality of conductive pillars 24 is a metal such as copper or solder.

[0075] Furthermore, during the formation of the plurality of conductive pillars 24, columnar fan-out conductors 29 are simultaneously fanned out on the electrical connection pads 220 of the electronic component 22. For example, the fan-out conductors 29 are pillars adapted to the geometry of the electrical connection pads 220 of the electronic component 22, such as square pillars, cylindrical pillars, or short pillars of other cross-sectional shapes, without particular limitation.

[0076] like Figure 2E As shown, an encapsulation layer 25 is formed on the carrier 9 so that the encapsulation layer 25 covers the first circuit layer 21, the functional pad 20, the electronic component 22 and the plurality of conductive pillars 24.

[0077] In this embodiment, the encapsulation layer 25 is defined with opposing first surfaces 25a and second surfaces 25b, such that the second surface 25b of the encapsulation layer 25 is bonded to the carrier 9 (or the release layer 90).

[0078] Furthermore, the material forming the encapsulation layer 25 is an insulating material, which can be an organic dielectric material (such as solder resist) or an inorganic dielectric material (such as insulating oxide). For example, the types of organic dielectric materials may include ABF (Ajinomoto Build-up Film), prepreg, molding compound, epoxy molding compound (EMC), or primer.

[0079] In addition, by using a leveling process, such as grinding, a portion of the material of the encapsulation layer 25 is removed so that the first surface 25a of the encapsulation layer 25 is flush with the end face 24a of the conductive post 24, so that the end face 24a of the conductive post 24 is exposed on the first surface 25a of the encapsulation layer 25.

[0080] Additionally, in other embodiments, such as Figure 2E-1 As shown, the encapsulation layer 25 can also be formed first, and then the electrical connection pad 220 of the electronic component 22 can be exposed by laser-drilled holes 251, and through holes 250 can be formed on the first surface 25a of the encapsulation layer 25. Afterwards, conductive material can be formed in the holes 251 and through holes 250, making the conductive material a conductive blind hole 36 and a tapered conductive pillar 34, as shown. Figure 2G-1 As shown.

[0081] like Figure 2F As shown, the continuation is as follows Figure 2E The process shown involves electroplating a second circuit layer 26 onto the first surface 25a of the packaging layer 25 using a patterned exposure and development method, so that the second circuit layer 26 electrically connects the electronic component 22 and the plurality of conductive pillars 24.

[0082] In this embodiment, the second line layer 26 is a fan-out redistribution layer (RDL). In another embodiment, if connected as follows... Figure 2E-1 The process shown, during the formation of the second circuit layer 26, is as follows: Figure 2G-1 As shown, multiple conductive blind vias 36 and conductive posts 34 are formed simultaneously, so that the multiple conductive blind vias 36 electrically connect the second circuit layer 26 and the electrical connection pad 220 of the electronic component 22.

[0083] Furthermore, the second circuit layer 26 contacts the end face 24a of the conductive post 24 to electrically connect to the conductive post 24. It should be understood that if the end face 24a of the conductive post 24 is not exposed on the first surface 25a of the encapsulation layer 25, the second circuit layer 26 can electrically connect to the conductive post 24 through the conductive blind via 260.

[0084] like Figure 2G As shown, the carrier 9 and its release layer 90 are removed to expose the second surface 25b of the encapsulation layer 25, the functional pad 20 and the bottom surface of the first circuit layer 21, so that the bottom surface of the first circuit layer 21 serves as an external pad.

[0085] Furthermore, in other embodiments, at least one additive circuit structure 26a can also be formed on the second circuit layer 26 (or the first surface 25a of the encapsulation layer 25) using an additive layer method, such as... Figure 2HThe electronic package 2a shown has an added-layer circuit structure 26a that electrically connects the electronic component 22 and the conductive post 24. The added-layer circuit structure 26a has multiple dielectric layers 260, multiple second circuit layers 261 disposed on the dielectric layers 260, and multiple conductive blind vias 262 disposed in the dielectric layers 260 and electrically connected to each of the second circuit layers 261. The dielectric material of the dielectric layer 260 is such as polybenzoxazole (PBO), polyimide (PI), prepreg (PP), or others.

[0086] In subsequent processes, the electronic package 2,2a may form a plurality of conductive elements 27, such as solder balls, on the second circuit layer 26,261. Figure 2H As shown), for connecting at least one external electronic device 8, such as a semiconductor chip, passive components (such as multi-layer ceramic capacitors or low-inductance ceramic capacitors), circuit board, or another package. Figure 2H (As shown). It should be understood that another layered circuit structure 26b can also be formed on the second surface 25b of the encapsulation layer 25 and the first circuit layer 21 (as shown). Figure 2H (as shown), for connecting external electronic devices such as semiconductor chips, passive components, circuit boards, or other packages (not shown).

[0087] The manufacturing method of this invention mainly involves forming a surface treatment layer 28 on a portion (partial) of the top surface of the functional pad 20, so that the bonding layer 23 simultaneously contacts two different metal materials (the surface treatment layer 28 and the functional pad 20). Therefore, when the electronic package 2,2a is subjected to thermal shock, the surface treatment layer 28 has a buffering effect, thereby improving the reliability of the electronic package 2,2a. For example, if the chemical bonding force between the functional pad 20 and the bonding layer 23 is not as expected, the surface treatment layer 28 can act as a buffer layer between the functional pad 20 and the bonding layer 23 to enhance the reliability of the electronic package 2,2a under thermal shock.

[0088] Furthermore, compared to the existing method of coating the entire top surface of the copper pad with a reinforcing layer, the method of the present invention forms a surface treatment layer 28 only on a portion (partial) of the top surface of the functional pad 20, thereby reducing production costs.

[0089] The present invention also provides an electronic package 2a, comprising: a patterned metal layer including at least one functional pad 20 and a first circuit layer 21, a surface treatment layer 28 disposed on a portion of the surface of the functional pad 20, a bonding layer 23, an electronic component 22 disposed on the bonding layer 23, an encapsulation layer 25, and an add-in circuit structure 26a.

[0090] The encapsulation layer 25 covers the electronic component 22 and the patterned metal layer and has opposing first surfaces 25a and second surfaces 25b, and exposes a portion of the bottom surface of the first circuit layer 21 to the encapsulation layer 25 as an external pad.

[0091] The functional pad 20 is embedded in the encapsulation layer 25 from the second surface 25b.

[0092] The surface treatment layer 28 is disposed on a portion of the surface of the functional pad 20.

[0093] The bonding layer 23 is disposed on the functional pad 20 and the surface treatment layer 28.

[0094] The electronic component 22 is disposed on the functional pad 20 and the surface treatment layer 28 via the bonding layer 23 and is provided with a plurality of electrical connection pads 220.

[0095] The added-layer circuit structure 26a is combined with the encapsulation layer 25 and electrically connected to the electrical connection pad 220 of the electronic component 22 and the first circuit layer 21.

[0096] In one embodiment, the surface treatment layer 28 is uniformly or non-uniformly distributed on a portion of the surface of the functional pad 20.

[0097] In one embodiment, the material of the functional pad 20 is different from the material of the surface treatment layer 28. For example, the functional pad 20 and the surface treatment layer 28 are made of different metals.

[0098] In one embodiment, the bonding layer 23 is a conductive adhesive or an insulating adhesive.

[0099] In one embodiment, the layered circuit structure 26a is electrically connected to the electrical connection pad 220 of the electronic component 22 by a plurality of fan-out conductors 29, and the fan-out conductors 29 are formed as cylinders adapted to the geometry of the electrical connection pad 220 of the electronic component 22.

[0100] In summary, the electronic package and its manufacturing method of the present invention, by forming the surface treatment layer 28 on a portion of the top surface of the functional pad 20, allows the bonding layer 23 to simultaneously contact two different metals, and the surface treatment layer 28 serves as a buffer layer. Therefore, the reliability of the electronic package of the present invention meets the requirements.

[0101] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Those skilled in the art can make modifications to the above embodiments without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the claims.

Claims

1. An electronic package, comprising: A patterned metal layer, comprising at least one functional pad and a first circuit layer; A surface treatment layer is disposed on a portion of the surface of the functional pad; A bonding layer is disposed on the functional pad and the surface treatment layer; An electronic component is disposed on the bonding layer and bonded to the functional pad and the surface treatment layer by the bonding layer, and the electronic component is provided with a plurality of electrical connection pads. An encapsulation layer covers the electronic component and the patterned metal layer, and exposes a portion of the bottom surface of the first circuit layer to the encapsulation layer as an external pad. as well as An add-in circuit structure is combined with the encapsulation layer and electrically connects the electrical connection pad of the electronic component and the first circuit layer.

2. The electronic package as claimed in claim 1, wherein, The surface treatment layer is uniformly or non-uniformly distributed on a portion of the surface of the functional pad.

3. The electronic package as described in claim 1, wherein, The functional pad and the surface treatment layer are made of different metal materials.

4. The electronic package as claimed in claim 1, wherein, The bonding layer is a conductive adhesive or an insulating adhesive.

5. The electronic package as claimed in claim 1, wherein, The added-layer circuit structure electrically connects the electrical connection pad of the electronic component via a fan-out conductor.

6. The electronic package as claimed in claim 5, wherein, The fan-out conductor is formed as a column adapted to the geometry of the electrical connection pad of the electronic component.

7. A method for manufacturing an electronic package, comprising: Provide a carrier having at least a metallic surface; A patterned metal layer is electroplated on the carrier using a patterned exposure and development method, wherein the patterned metal layer includes at least one functional pad and a first circuit layer. A surface treatment layer is formed on a portion of the surface of the functional pad; An bonding layer is formed on the functional pad and the surface treatment layer; An electronic component is attached to the bonding layer, wherein the electronic component has multiple electrical connection pads; Multiple conductive pillars are formed on a portion of the first circuit layer using a patterned exposure and development method; The electronic component and the plurality of conductive pillars are encapsulated in a packaging layer; A second circuit layer is electroplated on the packaging layer using a patterned exposure and development method, so that the second circuit layer electrically connects the electronic component and the plurality of conductive pillars; and Remove the carrier to expose the bottom surface of the first circuit layer as an outer pad.

8. The method for manufacturing an electronic package as described in claim 7, wherein, The surface treatment layer is formed uniformly or non-uniformly on a portion of the surface of the functional pad.

9. The method for manufacturing an electronic package as described in claim 7, wherein, The functional pad and the surface treatment layer are made of different metal materials.

10. The method for manufacturing an electronic package as described in claim 7, wherein, The manufacturing method also includes forming columnar fan-out conductors on the electrical connection pads of the electronic component simultaneously when forming the plurality of conductive pillars.

11. The method for manufacturing an electronic package as described in claim 10, wherein, The fan-out conductor is a cylinder adapted to the geometry of the electrical connection pad of the electronic component.

12. The method for manufacturing an electronic package as described in claim 7, wherein, The method also includes, after forming the encapsulation layer, exposing the electrical connection pad of the electronic component by laser drilling, and simultaneously forming a conductive blind via when forming the second circuit layer, so that the conductive blind via electrically connects the second circuit layer and the electrical connection pad of the electronic component.

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