TSV-based parallel line directional coupler

Abstract

The invention discloses a parallel line directional coupler based on TSV, comprising a Si substrate, two parallel coupling lines composed of a plurality of TSVs are arranged in the Si substrate, an upper SiO2 layer is arranged above the Si substrate, an upper RDL is buried in the upper SiO2 layer, a lower SiO2 layer is arranged below the Si substrate, a lower RDL is buried in the lower SiO2 layer, the upper RDL and the lower RDL are respectively connected to the upper and lower ends of the TSV; the four upper RDLs of the TSVs connecting the ends of the two parallel coupling lines are respectively connected to the input port, the through port, the coupling port, and the isolation port of the coupler, the input port and the through port are respectively located at the ends of the same coupling line; the coupling port and the isolation port are respectively located at the ends of the same coupling line. The invention realizes the miniaturization of the parallel line directional coupler based on the TSV technology, and the coupling degree is good.

Description

Technical Field

[0001] The invention belongs to the technical field of three-dimensional integrated passive devices and relates to a TSV-based parallel line directional coupler. Background Art

[0002] A parallel line coupler is a special type of directional coupler. The strength of the coupling of a parallel line directional coupler is mainly related to the distance between the two parallel lines. The smaller the distance, the stronger the coupling. However, too strong a coupling cannot be achieved in the manufacturing process. Therefore, a parallel line directional coupler with a stronger coupling can be obtained by connecting coupling lines in series. As a result, the size of the components becomes larger while the coupling degree increases. Since traditional directional couplers play a vital role in signal processing systems, communications and other fields, designing directional couplers with better performance, more miniaturization and integration has always been a key research direction that people have been working hard to break through.

[0003] In the field of three-dimensional integrated circuits, a new technology, Through Silicon Via (TSV), is the only vertical electrical interconnection technology. Therefore, TSV technology can be used to miniaturize directional couplers and greatly improve the reliability of integrated circuits. Summary of the invention

[0004] The object of the present invention is to provide a TSV-based parallel line directional coupler, wherein the coupler structure is based on the TSV technology to realize the miniaturization of the parallel line directional coupler and has a good coupling degree.

[0005] The technical solution adopted by the present invention is a TSV-based parallel line directional coupler, comprising a Si substrate, in which two parallel coupling lines composed of a plurality of TSVs are arranged, an upper layer of SiO2 is arranged above the Si substrate, an upper layer of RDL is buried in the upper layer of SiO2, a lower layer of SiO2 is arranged below the Si substrate, a lower layer of RDL is buried in the lower layer of SiO2, the upper layer of RDL and the lower layer of RDL are respectively connected to the upper and lower ends of the TSV; the four upper layer of RDLs of the TSVs connecting the ends of the two parallel coupling lines are respectively connected to the input port, the through port, the coupling port and the isolation port of the coupler, the input port and the through port are respectively located at the two end ends of the same coupling line; the coupling port and the isolation port are respectively located at the two end ends of the same coupling line.

[0006] The present invention is also characterized in that:

[0007] On each coupling line, the TSVs are arranged in sequence with equal intervals, and the TSVs are connected end to end through the upper RDL and the lower RLD.

[0008] The number and arrangement of TSVs on the two parallel coupling lines are exactly the same.

[0009] The input port and the coupled port are located at the same end of the Si substrate, and the through port and the isolated port are located at the same end of the Si substrate.

[0010] The materials of the upper RDL layer and the lower RDL layer are both copper metal.

[0011] The beneficial effect of the present invention is that the present invention adopts RDL rewiring technology and TSV silicon through-via technology in a folding manner, and on the premise of ensuring that the coupler has good isolation, the physical size of the parallel line directional coupler is greatly reduced, miniaturization is achieved, and the high-frequency characteristics of the parallel line coupler are improved. In addition, while ensuring the advantage of miniaturization, the special folding structure of the present invention can be used to connect the coupling lines in series to obtain couplers with different coupling degrees. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a schematic structural diagram of a TSV-based parallel line directional coupler of the present invention;

[0013] Figure 2 It is a schematic diagram of the extended structure of the parallel line directional coupler based on TSV of the present invention;

[0014] Figure 3 The figure is a simulation result diagram of the return loss S(1, 1) and insertion loss S(2, 1) of the parallel line directional coupler based on TSV of the present invention;

[0015] Figure 4 It is a simulation result diagram of the coupling degree S(3, 1) and isolation degree S(4, 1) of the TSV-based parallel line directional coupler of the present invention.

[0016] In the figure, 1. input port, 2. through port, 3. coupling port, 4. isolation port, 5. upper layer SiO2, 6. Si substrate, 7. lower layer SiO2. DETAILED DESCRIPTION

[0017] The present invention is described in detail below with reference to the accompanying drawings and specific embodiments.

[0018] The present invention is based on TSV parallel line directional coupler, such as Figure 1 As shown, it includes an upper SiO25, a Si substrate 6 and a lower SiO27 arranged in sequence from top to bottom, and a plurality of upper RDLs are buried in the upper SiO25. Figure 1 Take the four upper RDLs as an example, namely P1, P2, P3, and P4; several lower RDLs are buried in the lower SiO27. Figure 1 Take two lower RDL layers as an example, namely: P5 and P6; the upper RDL and the lower RDL are made of copper. Two parallel coupling lines composed of TSVs are arranged in the Si substrate 6. Figure 1Take four TSVs as an example, namely: TSV1, TSV2, TSV3, TSV4;

[0019] The structure of one of the coupled lines is as follows: the upper end of TSV1 is connected to one end of P1, the other end of P1 is connected to input port 1, the lower end of TSV1 is connected to the lower end of TSV3 through P5, the upper end of TSV3 is connected to one end of P3, and the other end of P3 is connected to through port 2;

[0020] The structure of another coupling line is as follows: the upper end of TSV2 is connected to one end of P2, the other end of P2 is connected to isolation port 4, the lower end of TSV2 is connected to the lower end of TSV4 through P6, the upper end of TSV4 is connected to one end of P4, and the other end of P4 is connected to coupling port 3.

[0021] TSV1, TSV2, TSV3, and TSV4 have the same structure, with the inner layer being copper metal and the outer layer being a silicon dioxide isolation layer to prevent mutual diffusion between copper and silicon substrate;

[0022] Figure 2 FIG. 1 is a schematic diagram of the structure of the extended parallel line coupler of the present invention. Figure 1 On the basis of this, the upper and lower extended RDLs in the horizontal direction are: P7, P8, P9, and P10, all of which are made of metal copper materials and buried in the upper SiO25 and the lower SiO27; the TSVs added in the vertical direction are: TSV5, TSV6, TSV7, and TSV8; the input port 1 is connected to P1, the through port 2 is connected to P9, the coupling port 3 is connected to P10, and the isolation port 4 is connected to P2.

[0023] In order to test the performance of the proposed 1:1 coupler, the present invention was modeled and simulated. Figure 1 The provided structural model is used for simulation. The dimensions of TSV1, TSV2, TSV3, and TSV4 are all: 50μm in height and 10μm in diameter. The dimensions of the upper and lower RDL are the same. The dimensions of P1, P2, P3, and P4 are all: 1μm in thickness, 10μm in width, and 50μm in length. The dimensions of the upper SiO25 and lower SiO27 are: 5μm in thickness, 210μm in length, and 50μm in width. The dimensions of the silicon substrate 6 are: 210μm in length, 50μm in width, and 50μm in height.

[0024] By performing a 1:1 simulation on the coupler, the simulation results of the present invention are obtained as shown in the attached figure. Figure 3 , 4As shown: its center frequency is 235GHz, and within the frequency band range of 234-237GHz, the input and output reflection coefficients are less than -25dB; within the frequency band range of 210-220GHz, the isolation is greater than 30dB, and the maximum can reach -36.81dB; its coupling is greater than 10dB, and the maximum can reach -23.86dB. Compared with the traditional planar parallel line coupler structure, the present invention, due to its special folding structure, has good component performance while greatly reducing the size of the component so as to better integrate with active devices and better realize the miniaturization and integration of the coupler.

[0025] The present invention is a parallel line directional coupler based on through silicon via (TSV) technology. The parallel line directional coupler is a strictly symmetrical structure. Under the condition of ensuring that the coupler has good isolation, the coupling line is rewired by using the folding idea. An upper and lower redistribution layer (RDL) structure is used in the horizontal direction. Two pairs of TSVs are used as coupling lines in the vertical direction, which are connected with the upper and lower RDLs to realize the function of the coupler. Since different communication systems nowadays require couplers with different coupling degrees to better realize the transmission of signals and energy, the coupling degree of the parallel line coupler can be changed by connecting the coupling lines in series, as shown in the attached figure. Figure 2 As shown, the present invention can change the coupling degree by continuing to extend the RDL structure in the horizontal direction, and continuing to add more TSVs in the horizontal reverse direction to connect the upper and lower RDLs to perform multiple foldings. No matter how many times it is folded, the resulting parallel line directional coupler only has four ports: input port, through port, coupling port, and isolation port.

[0026] The process size of the parallel line directional coupler is in the micron order. With the miniaturization of the components, the present invention has better high-frequency characteristics. Compared with the traditional parallel line coupler, the present invention has a higher center frequency and can meet the requirements of today's cutting-edge technology for high-frequency couplers.

Claims

1. TSV-based parallel line directional coupler, characterized by: The invention comprises a Si substrate (6), wherein two parallel coupling lines composed of a plurality of TSVs are arranged in the Si substrate (6), an upper SiO2 layer (5) is arranged above the Si substrate (6), an upper RDL is buried in the upper SiO2 layer (5), a lower SiO2 layer (7) is arranged below the Si substrate (6), a lower RDL is buried in the lower SiO2 layer (7), and the upper RDL and the lower RDL are respectively connected to the upper and lower ends of the TSVs; the four upper RDLs connecting the TSVs at the ends of the two parallel coupling lines are respectively connected to the input port (1), the through port (2), the coupling port (3), and the isolation port (4) of the coupler, the input port (1) and the through port (2) are respectively located at the ends of the same coupling line; the coupling port (3) and the isolation port (4) are respectively located at the ends of the same coupling line; On each of the coupling lines, the TSVs are arranged in sequence with equal intervals, and the TSVs are connected end to end through the upper RDL and the lower RLD in sequence; The number and arrangement of TSVs on the two parallel coupling lines are exactly the same; The input port (1) and the coupling port (3) are located at the same end of the Si substrate (6), and the through port (2) and the isolation port (4) are located at the same end of the Si substrate (6); The materials of the upper RDL layer and the lower RDL layer are both copper metal.

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