Bridgeless dual-stage PFC circuit based on gallium nitride-based device and surge suppression circuit

Abstract

The application relates to a circuit application based on a gallium nitride device, comprising a bridgeless two-stage boost power factor correction (PFC) circuit and a surge suppression circuit. The bridgeless PFC circuit adopts a control chip to control the two-stage PFC circuit, and only one power inductor is needed. The former stage is a sub-PFC, and the latter stage is a main PFC, and the power input of the latter stage circuit is derived from the coupling inductor of the boost inductor of the former stage. The sub-PFC adopts a Cz capacitor network to replace the traditional single-capacitor filter, and provides more flexible output voltage for the latter stage. The control part also adjusts the working frequency and duty cycle of the power circuit, realizes the optimization of the working efficiency of the PFC circuit, and simultaneously realizes the dynamic optimization of the overall efficiency of the PFC circuit and the PFC latter stage circuit. In addition, the surge suppression resistor is moved from the traditional series in the main power circuit to the lower end of the energy storage capacitor and is connected in series with the energy storage capacitor, and a transistor delay short circuit is adopted, so that the power consumption is greatly reduced, and a relay is no longer needed.

Description

Technical Field

[0001] This invention relates to a bridgeless two-stage PFC circuit and surge suppression circuit based on gallium nitride-based devices. Background Technology

[0002] With the rapid development of science and technology and the continuous upgrading of technology, the harmonic problem of the power grid must be well controlled. In power supply products, the need for high-capacity, high-voltage energy storage capacitors to maintain a current level for about 20ms causes the AC input current to exhibit a sharp pulse shape due to the smaller conduction angle of the rectifier bridge. Under the same power conditions, the peak value of the pulse current increases several times, and the high di / dt generates abundant harmonic interference, thus affecting the quality of the power grid. To improve power grid quality, active power factor correction (PFC) circuits are widely used to correct the waveform of the AC input current, making it a more perfect sine wave, similar to the AC input voltage. Common input-side solutions include... Figure 1 As shown, the PFC solution is as follows: Figure 2 The diagram shows a single-stage boost converter structure. However, this type of boost converter PFC circuit first requires a bridge rectifier for rectification, which generates high losses, severely impacting the PFC efficiency. Therefore, bridgeless PFC solutions were developed, with the totem-pole bridgeless PFC circuit being a typical example, such as... Figure 3 As shown, Q1 and Q2 operate at the power frequency and are commonly known as "slow transistors," while Q3 and Q4 operate at high frequencies, typically 50kHz-200kHz, and are commonly known as "fast transistors." This topology is particularly suitable for next-generation gallium nitride (GaN) semiconductor devices with good high-frequency characteristics and no reverse recovery issues.

[0003] The circuit employs a single-stage boost converter topology with a large output filter capacitor and an output voltage of approximately 380V. Generally, the lower the output voltage of this stage, the higher its efficiency. However, the opposite is true for subsequent stages; higher PFC output voltages result in higher efficiency. A single-stage boost PFC solution struggles to achieve optimal design between the PFC circuit and the subsequent stage, requiring a compromise in PFC output voltage. Therefore, a two-stage boost converter solution comprising a main PFC circuit and a sub-PFC circuit has been proposed, such as... Figure 4 As shown, its implementation circuit schematic is as follows: Figure 5As shown, the first stage is the main PFC, and the second stage is the sub-PFC. The output filter capacitor of the main PFC circuit has a small capacitance, while the output filter capacitor of the sub-PFC circuit has a large capacitance. Initially, the two-stage structure was conceived solely to reduce the size of the energy storage capacitor, as the first stage could extend the input voltage range of the second stage. However, a two-stage boost circuit requires two independent control chips, which significantly increases the complexity and cost of the circuit. Moreover, currently, this two-stage PFC structure only uses a two-stage boost circuit, resulting in low efficiency; a dual-stage bridgeless PFC circuit has not yet been implemented.

[0004] On the other hand, traditional surge suppression circuits are connected in series between the bridge rectifier and the energy storage capacitor, using a surge suppression limiting resistor RT in parallel with a relay. The circuit is placed at positions A, B, or C. This circuit is simple, easy to drive, low in cost, and not complex to control. However, the relay is large, and its resistance after conduction is over 50mΩ, resulting in relatively high operating losses, which is not conducive to the design of high-power, high-density, and high-efficiency power supplies. RT commonly uses a thermistor to suppress the inrush current generated at the moment of power-on. After the power supply is operating normally, the relay delays and short-circuits the current-limiting current to reduce power consumption. Figure 5 As shown. However, since the relay's on-resistance of approximately 100 milliohms is still quite high, and the surge suppression circuit is connected in series in the main power circuit, its conduction current is very large. The losses generated by the relay are still not negligible. Moreover, the relay is also quite large, which is not conducive to the design requirements of high power density power supplies. The relay also requires additional drive and third-party power supply, making the circuit complex and costly. Therefore, designing a PFC circuit and surge suppression circuit without a relay is of great significance. Summary of the Invention

[0005] The purpose of this invention is to provide a bridgeless two-stage PFC circuit based on gallium nitride-based devices.

[0006] The objective of this invention is achieved through the following technical solution:

[0007] A bridgeless two-stage PFC circuit based on gallium nitride-based devices, characterized in that it includes: a sub-PFC circuit and a main PFC circuit;

[0008] The sub-PFC circuit includes a totem pole bridgeless PFC power circuit and a Cz capacitor network. 2-8 capacitors are connected in series and grounded, and then connected in parallel with C4 to form the Cz capacitor network. The totem pole bridgeless PFC power circuit is connected in parallel with the Cz capacitor network.

[0009] The main PFC circuit includes a pair of coupled inductors LPFC:A and LPFC:B, two diodes DPFC2 and DPFC3, and a capacitor C5. One end of the AC input signal is input to the first terminal of LPFC:A in the main PFC circuit, and the other end is input to the totem pole bridgeless PFC power circuit of the sub-PFC circuit. The second terminal of LPFC:A is connected to the totem pole bridgeless PFC power circuit. The first terminal of inductor LPFC:B is connected to the anode of DPFC2, and the second terminal is connected to any series capacitor in the Cz capacitor network. The cathode of DPFC2 is connected to the upper end of capacitor C5. The anode of DPFC3 is connected to the totem pole bridgeless PFC power circuit, and the cathode is also connected to the upper end of capacitor C5. The upper end of C4 is connected between the totem pole bridgeless PFC power circuit and the anode of DPFC3, and the lower end is connected to the lower end of C5 and grounded.

[0010] It also includes a control chip, an output voltage monitoring module, and an output power monitoring module. The output voltage monitoring module and the output power monitoring module monitor the signals output from the cathodes of DPFC2 and DPFC3. The monitoring signals are input to the control chip, and the control chip controls and drives the totem pole bridgeless PFC power circuit.

[0011] It also includes an input power monitoring module, which monitors the AC input signal and inputs the monitoring signal to the control chip.

[0012] Preferably, the totem pole bridgeless PFC power circuit includes four switching transistors Q1, Q2, Q3 and Q4. The negative terminals of switching transistors Q1 and Q3 are connected to the upper end of the Cz capacitor network, and the positive terminals of switching transistors Q2 and Q4 are connected to the lower end of the Cz capacitor network and grounded. The operating frequency of Q1 and Q2 is the power frequency, and the operating frequency of Q3 and Q4 is the high frequency. The second terminal of the inductor LPFC:A is connected to the positive terminal of Q3 and the negative terminal of Q4.

[0013] During the positive half-cycle, Q2 is turned on within the power frequency cycle. When Q4 is turned on, LPFC:A stores energy through Q4 and Q2. After Q4 is turned off, Q3 is turned on, and LPFC:A releases energy through Q3, the Cz capacitor network, and Q2.

[0014] During the negative half-cycle, Q1 is turned on within the power frequency cycle. When Q3 is turned on, LPFC:A stores energy through Q3 and Q1. After Q3 is turned off, Q4 is turned on, and LPFC:A releases energy through Q4, the Cz capacitor network, and Q1.

[0015] Preferably, it also includes a second output power monitoring module to monitor the output power of the subsequent stage circuit and input the monitoring signal into the control chip.

[0016] Preferably, the series capacitor in the Cz capacitor network is a high-voltage ceramic capacitor, and C4 is a high-voltage electrolytic capacitor.

[0017] Preferably, the series capacitor in the Cz capacitor network consists of three capacitors connected in series.

[0018] Preferably, the switching transistor is a gallium nitride-based MOSFET or a HEMT.

[0019] This invention also discloses a surge suppression circuit, used in conjunction with the aforementioned bridgeless double-stage PFC circuit. Its features include a rectifier circuit, a switching transistor Qr, a control and drive circuit for Qr, a diode Din, and a surge suppression resistor RT. The negative terminal of Qr is connected to the lower end of C5, and the positive terminal of Qr is connected to the aforementioned bridgeless double-stage PFC circuit and grounded. RT is connected in parallel with Qr. The input terminal of the AC input signal is connected to the rectifier circuit. One output terminal of the rectifier circuit is connected to the anode of diode Din and the bridgeless double-stage PFC circuit, and the other output terminal is connected to the bridgeless double-stage PFC circuit. The cathode of diode Din is connected to the upper end of C5.

[0020] This invention relates to the circuit application of a novel wide-bandgap semiconductor device, comprising a bridgeless two-stage boost power factor correction (PFC) circuit and a surge suppression circuit. This bridgeless PFC circuit uses a single control chip to control two stages of the PFC circuit and requires only one power inductor. The first stage is a sub-PFC, and the second stage is the main PFC. The power input of the second stage circuit comes from the coupling inductor of the boost inductor in the first stage. The sub-PFC uses a Cz capacitor network instead of the traditional single-capacitor filter, providing a more flexible output voltage for the second stage. The control section also optimizes the PFC circuit's operating efficiency by adjusting the operating frequency and duty cycle of the power circuit, achieving a dynamic optimization of the overall efficiency of the PFC circuit and the subsequent PFC stage circuit. Furthermore, the surge suppression resistor, traditionally connected in series in the main power circuit, is moved to the lower end of the energy storage capacitor, connected in series with it. A transistor delay short circuit is used, significantly reducing power consumption and eliminating the need for a relay. This solution features a simple circuit, easy control, and low cost.

[0021] The beneficial effects of this invention are as follows:

[0022] 1. A bridgeless two-stage topology circuit structure with the main and sub-stages having a master control PFC (in traditional schemes, the first stage is a master control PFC).

[0023] 2. The sub-PFC uses a Cz capacitor network to replace the traditional single capacitor filter, providing a more flexible output voltage for the next stage;

[0024] 3. This circuit requires only one coupling inductor and one control chip, making control simple;

[0025] 4. Add efficiency optimization intelligent control, by adjusting the working frequency and duty cycle of the power circuit, to achieve the optimal working efficiency of the PFC circuit, and at the same time achieve a dynamic optimization of the overall efficiency of the PFC circuit and the PFC downstream circuit.

[0026] 5. The surge suppression resistor has been moved from being connected in series in the main power circuit to the lower end of the energy storage capacitor and connected in series with the energy storage capacitor. At the same time, a transistor delay short circuit is used, which greatly reduces its power consumption and eliminates the need for a relay. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of a single-stage bridgeless PFC solution on the power input side.

[0028] Figure 2 This is a traditional single-stage boost PFC solution.

[0029] Figure 3 This is a traditional single-level totem pole-type bridgeless PFC solution.

[0030] Figure 4 This is a schematic diagram of a two-stage PFC solution with a rectifier bridge on the power input side.

[0031] Figure 5 This is a traditional two-stage boost PFC solution.

[0032] Figure 6 This is a traditional surge suppression solution.

[0033] Figure 7 This invention relates to a bridgeless two-stage PFC circuit based on gallium nitride-based devices.

[0034] Figure 8 This is an embodiment of the bridgeless two-stage PFC circuit of the present invention.

[0035] Figure 9 This is an embodiment of the surge suppression method of the present invention. Detailed Implementation Example

[0036] A bridgeless two-stage PFC circuit based on gallium nitride-based devices, characterized in that it includes: a sub-PFC circuit and a main PFC circuit;

[0037] The sub-PFC circuit includes a totem pole bridgeless PFC power circuit and a Cz capacitor network. Three capacitors C1, C2, and C3 are connected in series and grounded, and then connected in parallel with C4 to form the Cz capacitor network. The totem pole bridgeless PFC power circuit is connected in parallel with the Cz capacitor network.

[0038] The main PFC circuit includes a pair of coupled inductors LPFC:A and LPFC:B, two diodes DPFC2 and DPFC3, and a capacitor C5. One end of the AC input signal is input to the first terminal of LPFC:A in the main PFC circuit, and the other end is input to the totem pole bridgeless PFC power circuit of the sub-PFC circuit. The second terminal of LPFC:A is connected to the totem pole bridgeless PFC power circuit. The first terminal of inductor LPFC:B is connected to the anode of DPFC2, and the second terminal is connected to the upper end of any series capacitor C1, C2, or C3 in the Cz capacitor network. The cathode of DPFC2 is connected to the upper end of capacitor C5. The anode of DPFC3 is connected to the totem pole bridgeless PFC power circuit, and the cathode is also connected to the upper end of capacitor C5. The upper end of C4 is connected between the totem pole bridgeless PFC power circuit and the anode of DPFC3, and the lower end is connected to the lower end of C5 and grounded.

[0039] It also includes a control chip, an output voltage monitoring module, and an output power monitoring module. The output voltage monitoring module and the output power monitoring module monitor the signals output from the cathodes of DPFC2 and DPFC3. The monitoring signals are input to the control chip, and the control chip controls and drives the totem pole bridgeless PFC power circuit.

[0040] It also includes an input power monitoring module, which monitors the AC input signal and inputs the monitoring signal to the control chip.

[0041] The totem pole bridgeless PFC power circuit includes four switching transistors Q1, Q2, Q3 and Q4. The negative terminals of switching transistors Q1 and Q3 are connected to the upper end of the Cz capacitor network, and the positive terminals of switching transistors Q2 and Q4 are connected to the lower end of the Cz capacitor network and grounded. Q1 and Q2 operate at the power frequency and are commonly known as slow transistors, while Q3 and Q4 operate at the high frequency and are commonly known as fast transistors. The second terminal of the inductor LPFC:A is connected to the positive terminal of Q3 and the negative terminal of Q4.

[0042] During the positive half-cycle, Q2 is turned on within the power frequency cycle. When Q4 is turned on, LPFC:A stores energy through Q4 and Q2. After Q4 is turned off, Q3 is turned on, and LPFC:A releases energy through Q3, the Cz capacitor network, and Q2.

[0043] During the negative half-cycle, Q1 is turned on within the power frequency cycle. When Q3 is turned on, LPFC:A stores energy through Q3 and Q1. After Q3 is turned off, Q4 is turned on, and LPFC:A releases energy through Q4, the Cz capacitor network, and Q1.

[0044] It also includes a second output power monitoring module, which monitors the output power of the next stage circuit and inputs the monitoring signal into the control chip.

[0045] The series capacitors in the Cz capacitor network are high-voltage ceramic capacitors, and C4 is a high-voltage electrolytic capacitor.

[0046] The switching transistor is a gallium nitride-based MOSFET or HEMT.

[0047] Work process description:

[0048] C1-C3 are connected in series (the series connection of C1-C3 can be 2-8 capacitors in series, not limited to 3, all of which are high-voltage ceramic capacitors), and then connected in parallel with C4, which is a high-voltage electrolytic capacitor with a large capacitance. These series and parallel capacitors together form the Cz capacitor network.

[0049] The working principle of the sub-PFC is exactly the same whether the input AC current is in the positive or negative half-cycle. During the positive half-cycle, the slow transistor Q2 conducts within the power frequency cycle. When the fast transistor Q4 conducts, LPFC:A stores energy through Q4 and Q2. After Q4 is turned off, Q3 conducts, and LPFC:A releases energy through Q3, the Cz network, and Q2. During the negative half-cycle, the slow transistor Q1 conducts within the power frequency cycle. When the fast transistor Q3 conducts, LPFC:A stores energy through Q3 and Q1. After Q3 is turned off, Q4 conducts, and LPFC:A releases energy through Q4, the Cz network, and Q1.

[0050] Main PFC operating principle: During the positive half-cycle, when Q4 is turned on, LPFC:A stores energy, and the coupling coil LPFC:B also stores energy. At this time, DPFC1 and DPFC2 are both reverse-biased off. The Cz capacitor network and C5 jointly supply power to the output load, but C5 is the primary power supplier because when the AC input is normally providing energy, the voltage on C5 is higher than the voltage on the Cz capacitor network, causing DPFC3 to be reverse-biased off. Only when the AC input is removed or the voltage of C5 is abnormal, the voltage of C5 drops until it is lower than the voltage on the Cz capacitor network. At this time, DPFC3 turns on, and the Cz capacitor network and C5 jointly supply power to the output load. When Q4 is turned off, the energy stored in LPFC:A generates a reverse electromotive force, causing DPFC1 to turn on. The inductor energy of LPFC:A charges the Cz capacitor network, realizing the first-stage boost function (sub-PFC). One end of LPFC:B coil is connected to point a, b, c, or d of the series capacitor network, depending on the required output voltage on C5. When connected to point a, the voltage on C5 is the highest, decreasing sequentially, with the lowest voltage on C5 when connected to point d. LPFC:B stores energy to generate a back electromotive force, causing DPFC2 to conduct. The inductor energy of LPFC:B charges C5, realizing the second-stage boost function (main PFC).

[0051] The working principle of the main PFC is almost the same as that of the positive half-cycle, except that Q4 is replaced by Q3. The rest of the description is exactly the same.

[0052] The voltage of the first-stage sub-PFC, Va = Vin / (1 - D), where 0 < D < 1. Therefore, a boost function is achieved. At this time, the effective energy of inductor LPFC:A is 0.5·LPFC:A·i12. During steady-state operation, a small part of the energy of inductor LPFC:A charges the Cz capacitor network when QPFC is turned off, and most of the energy is transferred to the secondary-side coil LPFC:B when QPFC is turned off, that is, 0.5·LPFC:B·i22. The voltage difference at both ends is (Va - Vin). Assuming the turn ratio of LPFC:A and LPFC:B is 1:2, then Vo = Vc + 2(Va - Vin) = Vc + 2(Vin / (1 - D) - Vin) = Vc + 2Vin·D / (1 - D). Then, the difference between Vo and Va, Vo - Va = Vc + Vin / (1 - D)·(2D - 1).

[0053] Therefore, in this circuit architecture, since the relationship between Vo and Va (the voltage at point a) is very clear, controlling Vo can control Va, and at the same time, controlling the duty cycle D can control Vo. Therefore, by directly sampling the output voltage Vo and controlling the on and off of the power switch QPFC, the control of Vo and Va voltages can be achieved. For the current shaping part, it can be exactly the same as the traditional current shaping scheme.

[0054] This control chip simultaneously monitors the output power 1 and the input power, calculates the working efficiency, and adjusts the operating frequency of the PFC power circuit through the control chip to optimize the efficiency. When the output efficiency is low, the operating frequency is reduced to improve the working efficiency. This adjustment can only optimize the efficiency of the PFC-stage power circuit.

[0055] This control chip also simultaneously monitors the output power 1 and the output power 2 of the subsequent-stage circuit, calculates the working efficiency of the subsequent-stage circuit, and adjusts the duty cycle of the PFC power circuit through the control chip to achieve a dynamic optimization of the efficiency of the PFC circuit and the efficiency of the circuit after the PFC, that is, an optimal compromise value. Embodiment

[0056] A surge suppression circuit, which is used in conjunction with the bridgeless dual-stage PFC circuit described above, and is characterized by including a rectifier circuit, a switching transistor Qr, a control and drive circuit for the switching transistor Qr, a diode Din, and a surge suppression resistor RT. The negative terminal of Qr is connected to the lower end of C5, the positive terminal of Qr is connected to the above-mentioned bridgeless dual-stage PFC circuit and grounded, RT is connected in parallel with Qr, the input terminal of the AC input signal is connected to the rectifier circuit, one output terminal of the rectifier circuit is connected to the anode of the diode Din and the bridgeless dual-stage PFC circuit, the other output terminal is connected to the bridgeless dual-stage PFC circuit, and the cathode of the diode Din is connected to the upper end of C5.

[0057] This circuit places the surge suppression resistor RT at the lower end of C5, with the other end grounded. At power-on, because RT is connected in series with C5, it suppresses current. Once C5 is fully charged and the surge current returns to normal, Qr is turned on by the control and drive circuit, short-circuiting RT. Current then flows through Qr, eliminating power consumption on RT. Furthermore, Qr has very low on-resistance, resulting in very low power consumption. Simultaneously, since neither Qr nor RT is in the main power circuit, the current flowing through them is only 3%-20% of that in the main power circuit, further reducing power consumption.

[0058] The above embodiments are preferred embodiments of the present invention, but the embodiments of the present invention are not limited to the above embodiments. Any changes, modifications, substitutions, combinations, or simplifications made without departing from the spirit and principle of the present invention shall be considered equivalent substitutions and shall be included within the protection scope of the present invention.

Claims

1. A bridgeless two-stage PFC circuit based on gallium nitride-based devices, characterized in that... include: Sub-PFC circuit and main PFC circuit; The sub-PFC circuit includes a totem pole bridgeless PFC power circuit and a Cz capacitor network. 2-8 capacitors are connected in series and grounded, and then connected in parallel with C4 to form the Cz capacitor network. The totem pole bridgeless PFC power circuit is connected in parallel with the Cz capacitor network. The main PFC circuit includes a pair of coupled inductors LPFC:A and LPFC:B, two diodes DPFC2 and DPFC3, and a capacitor C5. One end of the AC input signal is input to the first terminal of LPFC:A in the main PFC circuit, and the other end is input to the totem pole bridgeless PFC power circuit of the sub-PFC circuit. The second terminal of LPFC:A is connected to the totem pole bridgeless PFC power circuit. The first terminal of inductor LPFC:B is connected to the anode of DPFC2, and the second terminal is connected to any series capacitor in the Cz capacitor network. The cathode of DPFC2 is connected to the upper end of capacitor C5. The anode of DPFC3 is connected to the totem pole bridgeless PFC power circuit, and the cathode is also connected to the upper end of capacitor C5. The upper end of C4 is connected between the totem pole bridgeless PFC power circuit and the anode of DPFC3, and the lower end is connected to the lower end of C5 and grounded. It also includes a control chip, an output voltage monitoring module, and an output power monitoring module. The output voltage monitoring module and the output power monitoring module monitor the signals output from the cathodes of DPFC2 and DPFC3. The monitoring signals are input to the control chip, and the control chip controls and drives the totem pole bridgeless PFC power circuit. It also includes an input power monitoring module, which monitors the AC input signal and inputs the monitoring signal to the control chip.

2. The bridgeless two-stage PFC circuit based on gallium nitride-based devices according to claim 1, characterized in that: The totem pole bridgeless PFC power circuit includes four switching transistors Q1, Q2, Q3 and Q4. The negative terminals of switching transistors Q1 and Q3 are connected to the upper end of the Cz capacitor network, and the positive terminals of switching transistors Q2 and Q4 are connected to the lower end of the Cz capacitor network and grounded. The operating frequency of Q1 and Q2 is the power frequency, and the operating frequency of Q3 and Q4 is the high frequency. The second terminal of the inductor LPFC:A is connected to the positive terminal of Q3 and the negative terminal of Q4. During the positive half-cycle, Q2 conducts within the power frequency cycle; when Q4 conducts, L... PFC:A Energy is stored through Q4 and Q2; after Q4 is turned off, Q3 is turned on, and LPFC:A releases energy through Q3, the Cz capacitor network, and Q2. During the negative half-cycle, Q1 conducts within the power frequency cycle; when Q3 conducts, L... PFC:A Energy is stored through Q3 and Q1; after Q3 is turned off, Q4 is turned on, and LPFC:A releases energy through Q4, the Cz capacitor network, and Q1.

3. The bridgeless two-stage PFC circuit based on gallium nitride-based devices according to claim 1, characterized in that: It also includes a second output power monitoring module, which monitors the output power of the next stage circuit and inputs the monitoring signal into the control chip.

4. The bridgeless two-stage PFC circuit based on gallium nitride-based devices according to claim 1, characterized in that: The series capacitors in the Cz capacitor network are high-voltage ceramic capacitors, and C4 is a high-voltage electrolytic capacitor.

5. The bridgeless two-stage PFC circuit based on gallium nitride-based devices according to claim 1, characterized in that: The series capacitor in the Cz capacitor network consists of three capacitors connected in series.

6. The bridgeless two-stage PFC circuit based on gallium nitride-based devices according to any one of claims 1-5, characterized in that: The switching transistor is a gallium nitride-based MOSFET or a HEMT.

7. A surge suppression circuit, used in conjunction with the bridgeless two-stage PFC circuit according to any one of claims 1-6, characterized in that... The circuit includes a rectifier circuit, a switching transistor Qr, a control and drive circuit for the switching transistor Qr, a diode Din, and a surge suppression resistor RT. The negative terminal of Qr is connected to the lower end of C5, and the positive terminal of Qr is connected to the bridgeless double-stage PFC circuit as described in any one of claims 1-6 and grounded. RT is connected in parallel with Qr. The input terminal of the AC input signal is connected to the rectifier circuit. One output terminal of the rectifier circuit is connected to the anode of the diode Din and the bridgeless double-stage PFC circuit, and the other output terminal is connected to the bridgeless double-stage PFC circuit. The cathode of the diode Din is connected to the upper end of C5.

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