An active clamp flyback circuit with graded driving and a graded driving method

Abstract

This invention discloses a graded-drive active clamp flyback circuit, comprising: an active clamp flyback converter with parallel synchronous rectifier MOSFETs M1 and M2 on the secondary side, and parallel primary-side low-end MOSFETs M3 and M5, and parallel primary-side high-end MOSFETs M4 and M6 on the primary side; a graded-drive circuit that outputs drive signals for each MOSFET according to the load conditions of the active clamp flyback converter; the active clamp flyback converter responds to the drive signals of each MOSFET, operating under light load conditions with primary-side low-end MOSFET M3, primary-side high-end MOSFET M4, and synchronous rectifier MOSFET M1 while other MOSFETs remain inactive, and operating under heavy load conditions with all MOSFETs active. This invention solves the problem that the increased drive loss of multiple parallel devices driven simultaneously under light load conditions in an active clamp flyback circuit exceeds the reduction in conduction loss.

Description

Technical Field

[0001] This invention belongs to the field of power electronics technology, specifically relating to a graded-drive active clamp flyback circuit and its driving method. Background Technology

[0002] In recent years, in order to achieve high power density, the operating frequency of MOSFETs has been increasing, and their drive losses have gradually become comparable to their conduction losses.

[0003] In active clamp flyback circuits using two or more MOSFETs in parallel, when the operating frequency is high (greater than 500kHz for silicon-based devices and greater than 100kHz for silicon carbide-based devices), and the conduction current is low (i.e., under light load), driving multiple devices in parallel simultaneously will cause the increase in drive loss to exceed the decrease in conduction loss, resulting in high loss and low efficiency of the flyback converter circuit. Summary of the Invention

[0004] To address the aforementioned problems in the prior art, this invention provides a graded-driven active clamp flyback circuit and its driving method.

[0005] The technical problem to be solved by this invention is achieved through the following technical solution:

[0006] A graded-drive active clamp flyback circuit includes: an active clamp flyback converter and a graded-drive circuit; wherein,

[0007] The active clamp flyback converter has a parallel synchronous rectifier MOSFET M1 and a synchronous rectifier MOSFET M2 on the secondary side, a parallel primary low-side MOSFET M3 and a primary low-side MOSFET M5 on the primary side, and a parallel primary high-side MOSFET M4 and a primary high-side MOSFET M6 on the primary side.

[0008] The graded drive circuit is used to output a first drive signal pair to the primary side low-end MOS transistor M3 and the primary side high-end MOS transistor M4 respectively, according to the load conditions of the active clamp flyback converter; output a second drive signal pair to the primary side low-end MOS transistor M5 and the primary side high-end MOS transistor M6 respectively; and output a third drive signal pair to the synchronous rectifier MOS transistor M1 and the synchronous rectifier MOS transistor M2 respectively.

[0009] The active clamp flyback converter, in response to the first drive signal pair, the second drive signal pair and the third drive signal pair, operates the primary-side low-end MOSFET M3, the primary-side high-end MOSFET M4 and the synchronous rectifier MOSFET M1 under light load conditions, while other MOSFETs do not operate at the same time; under heavy load conditions, all MOSFETs operate.

[0010] Optionally, the hierarchical driving circuit includes:

[0011] The secondary-side sampling circuit is used to detect and sample the magnitude of the output current of the active clamp flyback converter to obtain a sampling signal;

[0012] The comparator circuit is used to compare the sampled signal with the reference signal and output an enable control signal that indicates whether the active clamp flyback circuit is operating under light or heavy load conditions.

[0013] An RS flip-flop outputs a first enable signal in response to the enable control signal;

[0014] A digital isolator is used to transmit the first enable signal to the primary side to form a second enable signal;

[0015] The primary-side driving circuit is used to output the first driving signal pair according to the first external power supply signal, and to output the second driving signal pair according to the first enable signal;

[0016] The secondary drive circuit is used to output one of the drive signals in the third drive signal pair according to the second external power supply signal, and to output the other drive signal in the third drive signal pair according to the second enable signal.

[0017] Optionally, the graded driving circuit further includes: a gain amplifier circuit;

[0018] The gain amplifier circuit is used to amplify the sampled signal so that the comparison circuit compares the amplified sampled signal with a reference signal.

[0019] Optionally, the primary-side driving circuit includes: a first half-bridge driving circuit and a second half-bridge driving circuit.

[0020] The first half-bridge drive circuit is used to output the second drive signal pair according to the first enable signal and the external first square wave signal;

[0021] The second half-bridge drive circuit is used to output the first drive signal pair according to the first square wave signal and the first external power supply signal.

[0022] Optionally, the secondary-side driving circuit includes: a first secondary-side driving sub-circuit and a second secondary-side driving sub-circuit;

[0023] The first secondary-side driving sub-circuit is used to output the driving signal of the third driving signal pair for driving the synchronous rectifier MOS transistor M2 according to the external second square wave signal when enabled by the second enabling signal.

[0024] The second secondary-side driving sub-circuit is used to output the driving signal for driving the synchronous rectifier MOS transistor M1 in the third driving signal pair according to the second square wave signal when enabled by the second external power supply signal.

[0025] The first square wave signal and the second square wave signal have opposite signal levels.

[0026] The present invention also provides a hierarchical driving method for hierarchically driving an active clamp flyback converter; the active clamp flyback converter has a synchronous rectifier MOSFET M1 and a synchronous rectifier MOSFET M2 connected in parallel on the secondary side, a primary low-side MOSFET M3 and a primary low-side MOSFET M5 connected in parallel on the primary side, and a primary high-side MOSFET M4 and a primary high-side MOSFET M6 connected in parallel on the primary side.

[0027] The hierarchical driving method includes:

[0028] The load conditions of the active clamp flyback converter are tested;

[0029] The MOSFETs in the active clamp flyback converter are driven in stages according to the load condition detection results.

[0030] Specifically, in response to a light load condition detection result, the primary-side low-end MOSFET M3, the primary-side high-end MOSFET M4, and the synchronous rectifier MOSFET M1 are driven to work, while other MOSFETs are not working; in response to a heavy load condition detection result, all MOSFETs are driven to work.

[0031] Optionally, the load conditions of the active clamp flyback converter are detected, including:

[0032] The magnitude of the output current of the active clamp flyback converter is detected and sampled to obtain the sampled signal;

[0033] By comparing the sampled signal with the reference signal, an enable control signal is output that characterizes whether the active clamp flyback converter is operating under light or heavy load conditions.

[0034] Optionally, before comparing the sampled signal with the reference signal, the hierarchical driving method further includes amplifying the sampled signal using a gain amplifier circuit.

[0035] Optionally, the MOSFETs in the active clamp flyback converter are driven in stages according to the load condition detection results, including:

[0036] An RS flip-flop is used to output a first enable signal in response to the enable control signal;

[0037] A digital isolator is used to transmit the first enable signal to the primary side to form a second enable signal;

[0038] The primary-side driving circuit outputs a first driving signal pair to the primary-side low-end MOSFET M3 and the primary-side high-end MOSFET M4 based on the first external power supply signal, and outputs a second driving signal pair to the primary-side low-end MOSFET M5 and the primary-side high-end MOSFET M6 based on the first enable signal; at the same time, the secondary-side driving circuit outputs a third driving signal pair to the synchronous rectifier MOSFET M1 and the synchronous rectifier MOSFET M2 based on the second external power supply signal and the second enable signal.

[0039] The MOS transistors in the active clamp flyback converter are driven in stages using the first drive signal pair, the second drive signal pair, and the third drive signal pair.

[0040] Optionally, the method is used to drive silicon carbide-based active clamp flyback converters with operating frequencies above 100kHz in a hierarchical manner, or to drive silicon-based active clamp flyback converters with operating frequencies above 500kHz in a hierarchical manner.

[0041] In the graded-drive active clamp flyback circuit provided by this invention, the graded-drive circuit outputs drive signals for each MOSFET according to the load conditions of the active clamp flyback converter, thereby driving all MOSFETs of the active clamp flyback converter to work under heavy load conditions, thereby reducing conduction losses and improving the efficiency of the flyback converter circuit. Under light load conditions, only the primary-side low-end MOSFET M3, the primary-side high-end MOSFET M4, and the synchronous rectifier MOSFET M1 work, while other MOSFETs do not work. This avoids the problem that the increase in drive losses of multiple parallel devices under light load conditions is greater than the decrease in conduction losses, thus reducing the drive losses of the flyback converter circuit and improving its efficiency. Therefore, this invention reduces the total power consumption of the active clamp flyback circuit and improves the overall efficiency of the flyback converter circuit under light load conditions.

[0042] The present invention will now be described in further detail with reference to the accompanying drawings. Attached Figure Description

[0043] Figure 1 This is a schematic diagram of the structure of a graded-drive active clamp flyback circuit provided in an embodiment of the present invention;

[0044] Figure 2 The diagram shows the state switching points of the active clamp flyback converter under single-transistor and dual-transistor drive at 200kHz.

[0045] Figure 3 It shows Figure 2 A schematic diagram of a single-transistor driven active clamp flyback converter;

[0046] Figure 4 The figure shows a portion of the signal waveforms in the active clamp flyback circuit provided in an embodiment of the present invention;

[0047] Figure 5 This is a flowchart of a hierarchical driving method provided in an embodiment of the present invention. Detailed Implementation

[0048] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0049] To address the problem that the increased drive loss of active clamp flyback circuits simultaneously driving multiple parallel devices under light load conditions exceeds the reduced conduction loss, this invention provides a graded-drive active clamp flyback circuit. For example... Figure 1 As shown, the circuit includes an active clamp flyback converter and a hierarchical drive circuit.

[0050] The active clamp flyback converter has parallel synchronous rectifier MOSFETs M1 and M2 on the secondary side, parallel primary low-side MOSFETs M3 and M5 on the primary side, and parallel primary high-side MOSFETs M4 and M6 on the primary side.

[0051] The graded drive circuit is used to output a first drive signal pair (QL, QH) to the primary-side low-end MOSFET M3 and the primary-side high-end MOSFET M4 respectively, according to the load conditions of the active clamp flyback converter; output a second drive signal pair (QL', QH') to the primary-side low-end MOSFET M5 and the primary-side high-end MOSFET M6 respectively; and output a third drive signal pair (SR, SR') to the synchronous rectifier MOSFETs M1 and M2 respectively.

[0052] The active clamp flyback converter responds to the first drive signal pair, the second drive signal pair, and the third drive signal pair. Under light load conditions, the primary-side low-side MOSFET M3, the primary-side high-side MOSFET M4, and the synchronous rectifier MOSFET M1 operate, while other MOSFETs do not operate. Under light load conditions, the synchronous rectifier MOSFET M2, the primary-side low-side MOSFET M5, and the primary-side high-side MOSFET M6 do not operate. Under heavy load conditions, all MOSFETs operate.

[0053] In other words, under light load conditions, the primary-side low-side MOSFET M3, the primary-side high-side MOSFET M4, and the synchronous rectifier MOSFET M1 are turned on, while the synchronous rectifier MOSFET M2, the primary-side low-side MOSFET M5, and the primary-side high-side MOSFET M6 are turned off. Under heavy load conditions, all of the primary-side low-side MOSFETs M3 and M4, the synchronous rectifier MOSFETs M1 and M2, the primary-side low-side MOSFETs M5 and M6 are turned on.

[0054] in addition, Figure 1 V in S R represents the power supply voltage of the active clamp flyback converter. O This represents the output resistance of an active clamp flyback converter, in which the turns ratio of the primary winding to the secondary winding is n:1.

[0055] In the graded-drive active clamp flyback circuit provided in this embodiment of the invention, the graded-drive circuit outputs drive signals for each MOSFET according to the load conditions of the active clamp flyback converter, thereby driving all MOSFETs of the active clamp flyback converter to work under heavy load conditions, thereby reducing conduction losses and improving the efficiency of the flyback converter circuit. Under light load conditions, only the primary-side low-end MOSFET M3, the primary-side high-end MOSFET M4, and the synchronous rectifier MOSFET M1 work, while other MOSFETs do not work. This avoids the problem that the increase in drive losses of multiple parallel devices under light load conditions is greater than the decrease in conduction losses, thus reducing the drive losses of the flyback converter circuit and improving its efficiency. Therefore, this embodiment of the invention reduces the total power consumption of the active clamp flyback circuit and improves the overall efficiency of the flyback converter circuit under light load conditions.

[0056] Optionally, in one embodiment, the hierarchical driving circuit may include:

[0057] The secondary-side sampling circuit is used to detect and sample the magnitude of the output current of the active clamp flyback converter to obtain a sampled signal; in practical applications, such as... Figure 1 As shown, the secondary-side sampling circuit can be a secondary-side sampling detection resistor R. S Of course, it is not limited to this.

[0058] The comparator circuit AMP is used to compare the sampled signal with the reference signal V. ref The comparison outputs an enable control signal that indicates whether the active clamp flyback circuit is operating under light or heavy load conditions.

[0059] In practical applications, the state switching point between light load and heavy load conditions can be found by testing or calculating the conduction and drive losses of the MOSFETs in the active clamp flyback converter, and the magnitude of the reference signal can be set according to the state switching point.

[0060] Figure 2 The diagram illustrates the state switching points of an active clamp flyback converter under single-transistor and dual-transistor drive conditions at 200kHz. Dual-transistor drive refers to an active clamp flyback converter using MOSFETs connected in parallel; its structure is shown in [reference needed]. Figure 1 As shown, single-transistor drive refers to an active clamp flyback converter that does not use MOSFETs in parallel; its structure can be found in [reference needed]. Figure 3 As shown; it can be understood that by testing or calculating the state switching point, the dividing point of the output current of the active clamp flyback converter under light load and heavy load conditions can be determined, and the magnitude of the reference signal can be determined based on this current.

[0061] An RS flip-flop outputs a first enable signal V in response to an enable control signal. EN It is understandable that this RS flip-flop outputs the first enable signal V by sampling and storing the enable control signal. EN .

[0062] A digital isolator is used to convert the first enable signal V... EN Transmitted to the primary side, forming the second enable signal V EN1 It is understandable that this digital isolator can also achieve electrical isolation between the primary and secondary sides simultaneously.

[0063] The primary-side drive circuit is used to drive the primary side based on the first external power supply signal V. CC Output the first drive signal pair (QL, QH), and according to the first enable signal V EN Output the second drive signal pair (QL', QH').

[0064] The secondary-side drive circuit is used to drive the secondary-side drive circuit according to the second external power supply signal V. DD Output one of the drive signals SR from the third drive signal pair (SR, SR'), and according to the second enable signal V EN1 Output the other drive signal SR' in the third drive signal pair.

[0065] The primary-side driving circuit may specifically include: a first half-bridge driving circuit and a second half-bridge driving circuit.

[0066] The first half-bridge drive circuit is used to respond to the first enable signal V. EN and the external first square wave signal V L Output the second drive signal pair (QL', QH');

[0067] The second half-bridge drive circuit is used to drive the first square wave signal V. L and the first external power supply signal V CCOutput the first drive signal pair (QL, QH).

[0068] The secondary-side driving circuit may specifically include: a first secondary-side driving sub-circuit and a second secondary-side driving sub-circuit;

[0069] The first secondary-side driver circuit is used in the second enable signal V EN1 With the enable function, based on the external second square wave signal V SR Output the drive signal SR' from the third drive signal pair (SR,SR') used to drive the synchronous rectifier MOS transistor M2;

[0070] The second auxiliary side drive circuit is used for the second external power supply signal V DD With the enable function, based on the second square wave signal V SR Output the drive signal SR from the third drive signal pair (SR, SR') used to drive the synchronous rectifier MOS transistor M1; wherein, the first square wave signal V L Second square wave signal V SR The signal levels are opposite.

[0071] It is understandable that the second secondary-side drive sub-circuit and the second half-bridge drive circuit form a drive combination to drive MOSFETs M1, M3 and M4 to work normally; the first secondary-side drive sub-circuit and the first half-bridge drive circuit form a drive combination to drive MOSFETs M2, M5 and M6 to start working only after the converter enters heavy load.

[0072] Figure 4 The diagram shows a portion of the signal waveforms in the active clamp flyback circuit provided in an embodiment of the present invention; based on this... Figure 4 As can be seen, the active clamp flyback circuit provided in this embodiment of the invention can flexibly switch the operating state of each MOS transistor according to the load conditions, thereby reducing the total power consumption of the active clamp flyback circuit and improving the overall efficiency of the flyback converter circuit under light load.

[0073] Alternatively, in one embodiment, as in Figure 1 The graded drive circuit shown may further include: a gain amplifier circuit AMP;

[0074] This gain amplifier circuit amplifies the sampled signal so that the comparator circuit compares the amplified sampled signal with the reference signal V. ref By making comparisons, the accuracy of detection under load conditions can be improved.

[0075] Based on the same inventive concept, embodiments of the present invention also provide a hierarchical driving method for hierarchically driving an active clamp flyback converter; see [link to related document]. Figure 1As shown, the active clamp flyback converter has parallel synchronous rectifier MOSFETs M1 and M2 on the secondary side, parallel primary low-side MOSFETs M3 and M5 on the primary side, and parallel primary high-side MOSFETs M4 and M6 on the primary side.

[0076] See Figure 5 As shown, the hierarchical driving method provided in this embodiment of the invention includes:

[0077] S10: Detect the load conditions of the active clamp flyback converter;

[0078] S20: Drives the MOS transistors in the active clamp flyback converter in stages according to the load condition detection results.

[0079] Specifically, in response to a light load condition detection result, the primary-side low-end MOSFET M3, the primary-side high-end MOSFET M4, and the synchronous rectifier MOSFET M1 are driven to work, while other MOSFETs are not working; in response to a heavy load condition detection result, all MOSFETs are driven to work.

[0080] Optionally, in one implementation, step S10 involves detecting the load conditions of the active clamp flyback converter, including:

[0081] The magnitude of the output current of the active clamp flyback converter is detected and sampled to obtain a sampling signal; by comparing the sampling signal with a reference signal, an enable control signal is output to characterize whether the active clamp flyback converter is operating under light or heavy load conditions.

[0082] Optionally, in one implementation, the hierarchical driving method provided in this embodiment of the invention may further include: amplifying the sampled signal using a gain amplifier circuit to compare the amplified sampled signal with a reference signal.

[0083] Optionally, in one implementation, step S20, which involves driving the MOSFETs in the active clamp flyback converter in stages according to the load condition detection result, includes:

[0084] An RS flip-flop is used to output a first enable signal V in response to an enable control signal. EN ;

[0085] Using a digital isolator, the first enable signal V is... EN Transmitted to the primary side, forming the second enable signal V EN1 ;

[0086] Using the primary-side drive circuit, based on the first external power supply signal V CCThe first drive signal pair (QL, QH) is output to the primary-side low-side MOSFET M3 and the primary-side high-side MOSFET M4 respectively, and according to the first enable signal V EN The second drive signal pair (QL', QH') is output to the primary-side low-side MOSFET M5 and the primary-side high-side MOSFET M6 respectively; simultaneously, the secondary-side drive circuit is used to drive the secondary external power supply signal V according to the second external power supply signal V. DD Second enable signal V EN1 The third drive signal pair (SR, SR') is output to synchronous rectifier MOSFET M1 and synchronous rectifier MOSFET M2 respectively;

[0087] The MOS transistors in the active clamp flyback converter are driven in stages using the first drive signal pair, the second drive signal pair, and the third drive signal pair.

[0088] It should be noted that the method embodiments are basically similar to the product embodiments, so the description is relatively simple. For relevant details, please refer to the description of the product embodiments.

[0089] The hierarchical driving method provided in this embodiment of the invention is preferably used for hierarchical driving of silicon carbide-based active clamp flyback converters with operating frequencies above 100kHz, or for hierarchical driving of silicon-based active clamp flyback converters with operating frequencies above 500kHz.

[0090] In the hierarchical driving method provided in this embodiment of the invention, the load conditions of the active clamp flyback converter are detected to drive all MOSFETs of the active clamp flyback converter to work under heavy load conditions, thereby reducing conduction losses and improving the efficiency of the flyback converter circuit. Under light load conditions, only the primary-side low-end MOSFET M3, the primary-side high-end MOSFET M4, and the synchronous rectifier MOSFET M1 work, while other MOSFETs do not work. This avoids the problem that the increase in drive losses of multiple parallel devices under light load conditions is greater than the decrease in conduction losses, thus reducing the drive losses of the flyback converter circuit and improving its efficiency. Therefore, this embodiment of the invention reduces the total power consumption of the active clamp flyback circuit and improves the overall efficiency of the flyback converter circuit under light load conditions.

[0091] It should be noted that the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this disclosure described herein can be implemented in orders other than those illustrated or described herein. The implementations described in the following exemplary embodiments do not represent all implementations consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure.

[0092] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0093] Although this application has been described herein in conjunction with various embodiments, those skilled in the art, by reviewing the accompanying drawings and the disclosure, will understand and implement other variations of the disclosed embodiments in carrying out the claimed application. In the description of this invention, the word "comprising" does not exclude other components or steps, "a" or "an" does not exclude a plurality, and "a plurality" means two or more, unless otherwise explicitly specified. Furthermore, while different embodiments may describe certain measures, this does not mean that these measures cannot be combined to produce good results.

[0094] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A graded-drive active clamp flyback circuit, characterized in that, include: Active clamp flyback converter and graded drive circuit; among which, The active clamp flyback converter has a parallel synchronous rectifier MOSFET M1 and a synchronous rectifier MOSFET M2 on the secondary side, a parallel primary low-side MOSFET M3 and a primary low-side MOSFET M5 on the primary side, and a parallel primary high-side MOSFET M4 and a primary high-side MOSFET M6 on the primary side. The graded drive circuit is used to output a first drive signal pair to the primary side low-end MOS transistor M3 and the primary side high-end MOS transistor M4 respectively, according to the load conditions of the active clamp flyback converter; output a second drive signal pair to the primary side low-end MOS transistor M5 and the primary side high-end MOS transistor M6 respectively; and output a third drive signal pair to the synchronous rectifier MOS transistor M1 and the synchronous rectifier MOS transistor M2 respectively. The active clamp flyback converter, in response to the first drive signal pair, the second drive signal pair and the third drive signal pair, operates the primary-side low-end MOSFET M3, the primary-side high-end MOSFET M4 and the synchronous rectifier MOSFET M1 under light load conditions, while other MOSFETs do not operate at the same time; under heavy load conditions, all MOSFETs operate.

2. The graded-drive active clamp flyback circuit according to claim 1, characterized in that, The hierarchical driving circuit includes: The secondary-side sampling circuit is used to detect and sample the magnitude of the output current of the active clamp flyback converter to obtain a sampling signal; The comparator circuit is used to compare the sampled signal with the reference signal and output an enable control signal that indicates whether the active clamp flyback circuit is operating under light or heavy load conditions. An RS flip-flop outputs a first enable signal in response to the enable control signal; A digital isolator is used to transmit the first enable signal to the primary side to form a second enable signal; The primary-side driving circuit is used to output the first driving signal pair according to the first external power supply signal, and to output the second driving signal pair according to the first enable signal; The secondary drive circuit is used to output one of the drive signals in the third drive signal pair according to the second external power supply signal, and to output the other drive signal in the third drive signal pair according to the second enable signal.

3. The graded-drive active clamp flyback circuit according to claim 2, characterized in that, The graded driving circuit further includes: a gain amplifier circuit; The gain amplifier circuit is used to amplify the sampled signal so that the comparison circuit compares the amplified sampled signal with a reference signal.

4. The graded-drive active clamp flyback circuit according to claim 2, characterized in that, The primary-side driving circuit includes: a first half-bridge driving circuit and a second half-bridge driving circuit. The first half-bridge drive circuit is used to output the second drive signal pair according to the first enable signal and the external first square wave signal; The second half-bridge drive circuit is used to output the first drive signal pair according to the first square wave signal and the first external power supply signal.

5. The graded-drive active clamp flyback circuit according to claim 4, characterized in that, The secondary-side driving circuit includes: a first secondary-side driving sub-circuit and a second secondary-side driving sub-circuit; The first secondary-side driving sub-circuit is used to output the driving signal of the third driving signal pair for driving the synchronous rectifier MOS transistor M2 according to the external second square wave signal when enabled by the second enabling signal. The second secondary-side driving sub-circuit is used to output the driving signal for driving the synchronous rectifier MOS transistor M1 in the third driving signal pair according to the second square wave signal when enabled by the second external power supply signal. The first square wave signal and the second square wave signal have opposite signal levels.

6. A hierarchical driving method, characterized in that, Used for hierarchical driving of active clamp flyback converter; the active clamp flyback converter has parallel synchronous rectifier MOSFETs M1 and M2 on the secondary side, parallel primary low-side MOSFETs M3 and M5 on the primary side, and parallel primary high-side MOSFETs M4 and M6 on the primary side. The hierarchical driving method includes: The load conditions of the active clamp flyback converter are tested; The MOSFETs in the active clamp flyback converter are driven in stages according to the load condition detection results. Specifically, in response to a light load condition detection result, the primary-side low-end MOSFET M3, the primary-side high-end MOSFET M4, and the synchronous rectifier MOSFET M1 are driven to work, while other MOSFETs are not working; in response to a heavy load condition detection result, all MOSFETs are driven to work.

7. The hierarchical driving method according to claim 6, characterized in that, The load conditions of the active clamp flyback converter are tested, including: The magnitude of the output current of the active clamp flyback converter is detected and sampled to obtain the sampled signal; By comparing the sampled signal with the reference signal, an enable control signal is output that characterizes whether the active clamp flyback converter is operating under light or heavy load conditions.

8. The hierarchical driving method according to claim 7, characterized in that, Before comparing the sampled signal with the reference signal, the hierarchical driving method further includes amplifying the sampled signal using a gain amplifier circuit.

9. The hierarchical driving method according to claim 8, characterized in that, The MOSFETs in the active clamp flyback converter are driven in stages according to the load condition detection results, including: An RS flip-flop is used to output a first enable signal in response to the enable control signal; A digital isolator is used to transmit the first enable signal to the primary side to form a second enable signal; The primary-side driving circuit outputs a first driving signal pair to the primary-side low-end MOSFET M3 and the primary-side high-end MOSFET M4 based on the first external power supply signal, and outputs a second driving signal pair to the primary-side low-end MOSFET M5 and the primary-side high-end MOSFET M6 based on the first enable signal; at the same time, the secondary-side driving circuit outputs a third driving signal pair to the synchronous rectifier MOSFET M1 and the synchronous rectifier MOSFET M2 based on the second external power supply signal and the second enable signal. The MOS transistors in the active clamp flyback converter are driven in stages using the first drive signal pair, the second drive signal pair, and the third drive signal pair.

10. The hierarchical driving method according to any one of claims 6 to 9, characterized in that, It is used for graded driving of silicon carbide-based active clamp flyback converters with operating frequencies above 100kHz, or for graded driving of silicon-based active clamp flyback converters with operating frequencies above 500kHz.

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