An anti-radiation Serdes transceiver CDR circuit based on phase interpolation

Abstract

An anti-radiation Serdes transceiver CDR circuit based on phase interpolation abandons the traditional CDR circuit completely based on the PLL structure, and uses a data and edge dual high-speed sampler, an anti-radiation CDR state machine, a high-precision phase interpolator and a general PLL based on an LC oscillator to recover high-speed data and clocks of 0.5 to 12.5 Gbps, achieving strong loop stability, single-event radiation resistance, short phase capture time, high linearity and low jitter of the CDR.

Description

Technical Field

[0001] The present invention relates to a radiation-resistant Serdes transceiver CDR circuit based on phase interpolation, in particular to a clock control circuit optimized for DDR3 application requirements through a programmable logic device, and belongs to the field of integrated circuits. Background Art

[0002] As an indispensable key module in high-speed serial communication, the CDR circuit plays a crucial role in the entire serial transmission process. Whether the CDR circuit can extract a clock signal synchronized with the data from the distorted high-speed serial data restricts the performance of the entire Serdes chip. And only when the recovered clock signal samples at the data peak can the original data be recovered to ensure a low bit error rate. The traditional PLL-based CDR circuit is a single-loop structure, with a relatively simple circuit structure, convenient for production and integration. However, the working mode of first locking the frequency and then locking the phase easily causes the circuit to lose lock, which may lead to system instability. The CDR circuit of the radiation-resistant Serdes transceiver based on phase interpolation adopts a data and edge dual high-speed sampler, a radiation-resistant CDR state machine, a high-precision phase interpolator, and a general PLL circuit structure based on an LC oscillator, which can enable the circuit to quickly capture high-speed clocks and data. The phase smoothing adjustment makes the system highly stable. The use of a digital state machine in the circuit improves the system's ability to resist PVT variations, reduces the design difficulty, decreases the layout area, and enhances the jitter performance of the CDR. Summary of the Invention

[0003] The technical problem solved by the present invention is: for clock recovery in high-speed serial data communication, it provides a CDR circuit technology for a radiation-resistant Serdes transceiver based on phase interpolation, overcomes the deficiencies of the prior art, solves the CDR jitter problem caused by temperature, voltage fluctuations, etc., improves the performance of sampling, interpolation, and locking in high-speed serial communication, solves the accurate phase accuracy capture and delay problems of the CDR circuit for 0.5 Gbps - 12.5 Gbps Serdes transceivers, solves the loop stability of the CDR circuit for 0.5 Gbps - 12.5 Gbps Serdes transceivers, reduces the design difficulty, and enhances the jitter performance of the CDR.

[0004] The technical solution of the present invention is: an anti-radiation Serdes transceiver CDR circuit based on phase interpolation, including a data sampler, an edge sampler, an anti-radiation CDR state machine, a phase interpolator, and a general PLL based on an LC oscillator; the phase interpolator includes a data phase interpolator and an edge phase interpolator; after the external RXP / RXN receives data, it undergoes linear equalization by a linear equalizer and data equalization by a decision feedback equalizer, and then enters the data sampler and the edge sampler for sampling respectively; the data D0...Dn sampled in the data sampler and the edge data E0...En sampled in the edge sampler enter the anti-radiation CDR state machine; the anti-radiation CDR state machine controls the data phase interpolator by tracking the information of the data D0...Dn and the edge data E0...En, outputs the phase interpolation codes d0...d5 to the data phase interpolator, and outputs the phase interpolation codes e0...e5 to the edge phase interpolator; the anti-radiation CDR state machine controls the data phase interpolator and the edge phase interpolator to output the sampling clocks of the data sampler and the edge sampler, forming a stable negative feedback loop to achieve the recovery of the data and the clocks output by the data and clock samplers.

[0005] The data sampler includes PMOS transistors i72, i74, i80, i82, i84, i86, and NMOS transistors i73, i75, i76, i77, i78, i79, i81, i83, i85, i87; the source terminal of PMOS transistor i72 is connected to the power supply, the gate terminal is used as the bidirectional port B of the data sampler and the source terminal of NMOS transistor i73, and the drain terminal is connected to the drain terminal of NMOS transistor i73; the source terminal of PMOS transistor i74 is connected to the power supply, the gate terminal is connected to the bidirectional port A and the gate terminal of NMOS transistor i75 respectively, and the drain terminal is connected to the drain terminal of NMOS transistor i75; the source terminal of NMOS transistor i73 is grounded, and the source terminal of NMOS transistor i75 is grounded; the drain terminal of NMOS transistor i76 is connected to the bidirectional port A, the gate terminal is used as an external data or clock input, and the source terminal is connected to the drain terminal of NMOS transistor i77; the source terminal of NMOS transistor i77 is grounded, and the gate terminal is used as an external reference input; the drain terminal of NMOS transistor i78 is used as the bidirectional port B of the data sampler, the gate terminal is used as an external data or clock input, and the source terminal is connected to the drain terminal of NMOS transistor i79; the source terminal of NMOS transistor i79 is grounded, and the gate terminal is used as an external reference input;

[0006] The source terminal of PMOS transistor i80 is connected to the power supply. The gate terminal serves as the bidirectional port B of the data sampler and the source terminal of NMOS transistor i81 respectively, and the drain terminal is connected to the drain terminal of NMOS transistor i81. The source terminal of PMOS transistor i82 is connected to the power supply. The gate terminal serves as the external output port Out_P and the gate terminal of NMOS transistor i83 respectively, and the drain terminal is connected to the drain terminal of NMOS transistor i83. The source terminal of NMOS transistor i81 is grounded, and the source terminal of NMOS transistor i83 is grounded. The source terminal of PMOS transistor i84 is connected to the power supply. The gate terminal serves as the bidirectional port A of the data sampler, and the drain terminal serves as the external output port Out_P. The source terminal of PMOS transistor i86 is connected to the power supply. The gate terminal serves as the bidirectional port B of the data sampler, and the drain terminal serves as the external output port Out_N. The source terminal of NMOS transistor i85 is grounded. The gate terminal serves as the bidirectional port A of the data sampler, and the drain terminal serves as the external output port Out_P. The source terminal of NMOS transistor i87 is grounded. The gate terminal serves as the bidirectional port B of the data sampler, and the drain terminal serves as the external output port Out_P.

[0007] The edge sampler includes PMOS transistors i72, i74, i80, i82, i84, i86, and NMOS transistors i73, i75, i76, i77, i78, i79, i81, i83, i85, i87. The source terminal of PMOS transistor i72 is connected to the power supply. The gate terminal serves as the bidirectional port B of the edge sampler and the source terminal of NMOS transistor i73 respectively, and the drain terminal is connected to the drain terminal of NMOS transistor i73. The source terminal of PMOS transistor i74 is connected to the power supply. The gate terminal serves as the bidirectional port A of the edge sampler and the gate terminal of NMOS transistor i75 respectively, and the drain terminal is connected to the drain terminal of NMOS transistor i75. The source terminal of NMOS transistor i73 is grounded, and the source terminal of NMOS transistor i75 is grounded. The drain terminal of NMOS transistor i76 serves as the bidirectional port A of the edge sampler. The gate terminal serves as the external data or clock input, and the source terminal is connected to the drain terminal of NMOS transistor i77. The source terminal of NMOS transistor i77 is grounded, and the gate terminal serves as the external reference input. The drain terminal of NMOS transistor i78 serves as the bidirectional port B of the edge sampler. The gate terminal serves as the external data or clock input, and the source terminal is connected to the drain terminal of NMOS transistor i79. The source terminal of NMOS transistor i79 is grounded, and the gate terminal serves as the external reference input.

[0008] The source terminal of PMOS transistor i80 is connected to the power supply. The gate terminal serves as the bidirectional port B of the edge sampler and the source terminal of NMOS transistor i81 respectively, and the drain terminal is connected to the drain terminal of NMOS transistor i81. The source terminal of PMOS transistor i82 is connected to the power supply. The gate terminal serves as the external output port Out_P and the gate terminal of NMOS transistor i83 respectively, and the drain terminal is connected to the drain terminal of NMOS transistor i83. The source terminal of NMOS transistor i81 is grounded, and the source terminal of NMOS transistor i83 is grounded. The source terminal of PMOS transistor i84 is connected to the power supply. The gate terminal serves as the bidirectional port A of the edge sampler, and the drain terminal serves as the external output port Out_P. The source terminal of PMOS transistor i86 is connected to the power supply. The gate terminal serves as the bidirectional port B of the edge sampler, and the drain terminal serves as the external output port Out_N. The source terminal of NMOS transistor i85 is grounded. The gate terminal serves as the bidirectional port A of the edge sampler, and the drain terminal serves as the external output port Out_P. The source terminal of NMOS transistor i87 is grounded. The gate terminal serves as the bidirectional port B of the edge sampler, and the drain terminal serves as the external output port Out_P.

[0009] The radiation-hardened CDR state machine includes a triple modular redundancy voting module, a counter module, a data phase interpolation code generation module, and an edge phase interpolation code generation module. The voting circuit module receives the sampled data D0...Dn and the sampled edges E0...En, and outputs the voting results Ve[0]Ve[1]...Ve[n] to the counter module after voting. The counter module outputs d0...d5 to the data phase interpolation code generation module and e0...e5 to the edge phase interpolation code generation module after receiving the voting results, and controls the phases of the output data sampling clock and the edge sampling clock through the phase interpolator.

[0010] Both the data phase interpolator and the edge phase interpolator include a phase interpolator decoding module, a phase interpolator reference generation module, and a phase interpolation circuit. The phase interpolator decoding module decodes the interpolation code and outputs it to the phase interpolation circuit, and controls the phase of the output sampling clock through phase interpolation. The reference of both modules comes from the phase interpolator reference generation module.

[0011] The phase interpolator decoding module includes a decoding circuit i26 and flip-flop circuits i27 - i42. The decoding circuit i26 receives the data phase interpolation code d0...d5 and the edge phase interpolation code e0...e5, and after decoding, outputs them to the flip-flop circuits i27 - i42 respectively. At the same time, the 16 flip-flops output 32-bit data A0, A0N, A1, A1N, A2, A2N, A3, A3N,...A15, A15N to the phase interpolation circuit.

[0012] The phase interpolator reference generation module includes PMOS transistor i31, PMOS transistor i32, NMOS transistor i33, NMOS transistor i34, PMOS transistor i35, PMOS transistor i36, NMOS transistor i37, NMOS transistor i38, PMOS transistor i39, PMOS transistor i40, NMOS transistor i41, NMOS transistor i422, PMOS transistor i43, PMOS transistor i44, PMOS transistor i45, PMOS transistor i46, PMOS transistor i47, PMOS transistor i48, PMOS transistor i49, PMOS transistor i50, PMOS transistor i51, PMOS transistor i52, the source of PMOS transistor i53, and PMOS transistor i54;

[0013] The source of PMOS transistor i31 is connected to the power supply, the gate is used as the external reference input terminal VO1, and the drain is connected to the source of PMOS transistor i32; the gate of PMOS transistor i32 is used as the external reference input port VO2, and the drain is connected to the drain of NMOS transistor i33, the gate of NMOS transistor i33, the gate of NMOS transistor i34, and the external output port S; the source of NMOS transistor i33 is grounded; the source and drain of NMOS transistor i34 are both grounded;

[0014] The source of PMOS transistor i35 is connected to the power supply, the gate is used as the external reference input terminal VO1, and the drain is connected to the source of PMOS transistor i36; the gate of PMOS transistor i36 is used as the external reference input port VO2, and the drain is connected to the drain of NMOS transistor i37, the gate of NMOS transistor i37, the gate of NMOS transistor i38, and the external output port P, the bidirectional port OP; the source of NMOS transistor i37 is grounded; the source and drain of NMOS transistor i38 are both grounded;

[0015] The source of PMOS transistor i39 is connected to the power supply, the gate is used as the external reference input terminal VO1, and the drain is connected to the source of PMOS transistor i40; the gate of PMOS transistor i40 is used as the external reference input port VO2, and the drain is connected to the drain of NMOS transistor i41, the gate of NMOS transistor i41, the gate of NMOS transistor i42, and the external output port N, the bidirectional port ON; the source of NMOS transistor i41 is grounded; the source and drain of NMOS transistor i42 are both grounded;

[0016] The source of PMOS transistor i43 is connected to the power supply and the source of PMOS transistor i44, the gate is connected to the drain, the gate and drain of PMOS transistor i44, the source of PMOS transistor i45, and the source of PMOS transistor i46. The gate of PMOS transistor i45 is used as the external input port A1, the drain of PMOS transistor i45 is used as the external bidirectional port OP, the gate of PMOS transistor i46 is used as the external input port A1N, and the drain of PMOS transistor i46 is used as the external bidirectional port ON;

[0017] The source terminal of PMOS transistor i47 is connected to the power supply and the source terminal of PMOS transistor i48. The gate terminal is connected to the drain terminal, the gate terminal and the drain terminal of PMOS transistor i48, the source terminal of PMOS transistor i49, and the source terminal of PMOS transistor i50. The gate terminal of PMOS transistor i49 serves as the external input port A1, the drain terminal of PMOS transistor i49 serves as the bidirectional port OP, the gate terminal of PMOS transistor i50 serves as the external input port A1N, and the drain terminal of PMOS transistor i50 serves as the external bidirectional port ON;

[0018] The source terminal of PMOS transistor i51 is connected to the power supply and the source terminal of PMOS transistor i52. The gate terminal is connected to the drain terminal, the gate terminal and the drain terminal of PMOS transistor i52, the source terminal of PMOS transistor i53, and the source terminal of PMOS transistor i54. The gate terminal of PMOS transistor i53 serves as the external input port A15, the drain terminal of PMOS transistor i53 serves as the external bidirectional port OP, the gate terminal of PMOS transistor i54 serves as the external input port A15N, and the drain terminal of PMOS transistor i54 serves as the external bidirectional port ON.

[0019] The phase interpolation circuit in the phase interpolator includes inverter i55, PMOS transistor i56, PMOS transistor i57, three parallel resistors i58, NMOS transistors i60, i61, i62, i63, i64, i65, i66, i67, i68, i69, i70, and i71;

[0020] The external input reference port is input from the input terminal of inverter i55, and the output terminal of inverter i55 is connected to the gate terminals of PMOS transistor i56 and PMOS transistor i57; the source terminal of PMOS transistor i56 is connected to the power supply, and the source terminal of PMOS transistor i57 is connected to the power supply;

[0021] The drain terminal of PMOS transistor i56 is connected to one end of three parallel resistors i58; the other end of three parallel resistors i58 is connected to the drain terminals of NMOS transistors i60, i63, i66, and i69; the drain terminal of PMOS transistor i56 is connected to one end of three parallel resistors i58; the other end of three parallel resistors i58 is connected to the drain terminals of NMOS transistors i60, i63, i66, and i69; the drain terminal of PMOS transistor i57 is connected to one end of three parallel resistors i59; the other end of three parallel resistors i59 is connected to the drain terminals of NMOS transistors i62, i65, i68, and i71;

[0022] The source terminal of NMOS transistor i60 is connected to the source terminal of NMOS transistor i62 and the drain terminal of NMOS transistor i61; the source terminal of NMOS transistor i63 is connected to the source terminal of NMOS transistor i65 and the drain terminal of NMOS transistor i64; the source terminal of NMOS transistor i66 is connected to the source terminal of NMOS transistor i68 and the drain terminal of NMOS transistor i67; the source terminal of NMOS transistor i69 is connected to the source terminal of NMOS transistor i71 and the drain terminal of NMOS transistor i70;

[0023] The gate terminal of NMOS transistor i60 serves as an external input terminal clk0, the gate terminal of NMOS transistor i62 serves as an external input terminal clk180, the gate terminal of NMOS transistor i63 serves as an external input terminal clk90, the gate terminal of NMOS transistor i65 serves as an external input terminal clk270, the gate terminal of NMOS transistor i66 serves as an external input terminal clk180, the gate terminal of NMOS transistor i68 serves as an external input terminal clk360, the gate terminal of NMOS transistor i69 serves as an external input terminal clk270, and the gate terminal of NMOS transistor i71 serves as an external input terminal clk90; the gate terminal of NMOS transistor i61 serves as an external input port S, and the source terminal is grounded; the gate terminal of NMOS transistor i64 serves as an external input port P, and the source terminal is grounded; the gate terminal of NMOS transistor i67 serves as an external input port S, and the source terminal is grounded; the gate terminal of NMOS transistor i70 serves as an external input port N, and the source terminal is grounded.

[0024] The advantages of the present invention compared with the prior art are as follows:

[0025] (1) By adopting a phase interpolation structure, the present invention realizes precise delay of the clock phase, can improve the flexibility of the data and edge sampler, adopts a loop negative feedback structure to reduce the influence of the clock caused by process, temperature, and noise, and provides the anti-interference ability of the data edge sampler and the edge sampling controller.

[0026] (2) By adopting an anti-radiation CDR state machine structure, the present invention can utilize the phase interpolator circuit to realize the function of the voltage-controlled oscillator, realize the integral link in high-speed serial transmission, solve the tracking problem of the frequency difference between the input data and the reference clock of the CDR circuit, and realize the reduction of the clock jitter recovered by the CDR circuit.

[0027] (3) By adopting a high-speed data and edge sampler structure, the present invention can improve the high-speed sampling sensitivity, increase the charge and discharge speed, reduce the signal high and low level conversion time, and realize accurate sampling of the sampler. Brief Description of the Drawings

[0028] Figure 1 It is a schematic diagram of the CDR design of an anti-radiation Serdes transceiver based on phase interpolation according to the present invention;

[0029] Figure 2 It is a schematic diagram of the data and edge sampler circuit according to the present invention;

[0030] Figure 3 is the schematic diagram of the anti-radiation CDR state machine circuit of the present invention;

[0031] Figure 4 is the schematic diagram of the decoding module circuit of the present invention;

[0032] Figure 5 is the schematic diagram of the reference generation module circuit of the present invention;

[0033] Figure 6 is the schematic diagram of the phase interpolation circuit of the present invention; Detailed implementation manners

[0034] A radiation-resistant Serdes transceiver CDR circuit based on phase interpolation according to the present invention, as Figure 1 shown, includes a data sampler, an edge sampler, an anti-radiation CDR state machine, a phase interpolator, and a general PLL based on an LC oscillator. The phase interpolator includes a data phase interpolator and an edge phase interpolator.

[0035] After the external RXP / RXN receives data, it undergoes linear equalization by a linear equalizer and data equalization by a decision feedback equalizer, and then enters the data sampler and the edge sampler for sampling respectively; the sampled data D0...Dn in the data sampler and the sampled edge data E0...En in the edge sampler enter the anti-radiation CDR state machine; the anti-radiation CDR state machine controls the data phase interpolator by tracking the information of the data D0...Dn and the edge data E0...En, outputs phase interpolation codes d0...d5 to the data phase interpolator, and outputs phase interpolation codes e0...e5 to the edge phase interpolator; the anti-radiation CDR state machine controls the data phase interpolator and the edge phase interpolator to output the sampling clocks of the data sampler and the edge sampler, forming a stable negative feedback loop to realize the recovery of the data and clocks output by the data and clock samplers.

[0036] Such as Figure 2As shown, the data sampler includes PMOS transistors i72, i74, i80, i82, i84, i86, and NMOS transistors i73, i75, i76, i77, i78, i79, i81, i83, i85, i87; the source terminal of PMOS transistor i72 is connected to the power supply, the gate terminal serves as the bidirectional port B of the data sampler and the source terminal of NMOS transistor i73, and the drain terminal is connected to the drain terminal of NMOS transistor i73; the source terminal of PMOS transistor i74 is connected to the power supply, the gate terminal is respectively connected to the bidirectional port A and the gate terminal of NMOS transistor i75, and the drain terminal is connected to the drain terminal of NMOS transistor i75; the source terminal of NMOS transistor i73 is grounded, and the source terminal of NMOS transistor i75 is grounded; the drain terminal of NMOS transistor i76 is connected to the bidirectional port A, the gate terminal serves as an external data or clock input, and the source terminal is connected to the drain terminal of NMOS transistor i77; the source terminal of NMOS transistor i77 is grounded, and the gate terminal serves as an external reference input; the drain terminal of NMOS transistor i78 serves as the bidirectional port B of the data sampler, the gate terminal serves as an external data or clock input, and the source terminal is connected to the drain terminal of NMOS transistor i79; the source terminal of NMOS transistor i79 is grounded, and the gate terminal serves as an external reference input;

[0037] The source terminal of PMOS transistor i80 is connected to the power supply, the gate terminal respectively serves as the bidirectional port B of the data sampler and the source terminal of NMOS transistor i81, and the drain terminal is connected to the drain terminal of NMOS transistor i81; the source terminal of PMOS transistor i82 is connected to the power supply, the gate terminal respectively serves as the external output port Out_P and the gate terminal of NMOS transistor i83, and the drain terminal is connected to the drain terminal of NMOS transistor i83; the source terminal of NMOS transistor i81 is grounded, and the source terminal of NMOS transistor i83 is grounded; the source terminal of PMOS transistor i84 is connected to the power supply, the gate terminal serves as the bidirectional port A of the data sampler, and the drain terminal serves as the external output port Out_P; the source terminal of PMOS transistor i86 is connected to the power supply, the gate terminal serves as the bidirectional port B of the data sampler, and the drain terminal serves as the external output port Out_N; the source terminal of NMOS transistor i85 is grounded, the gate terminal serves as the bidirectional port A of the data sampler, and the drain terminal serves as the external output port Out_P; the source terminal of NMOS transistor i87 is grounded, the gate terminal serves as the bidirectional port B of the data sampler, and the drain terminal serves as the external output port Out_P.

[0038] The edge sampler includes PMOS transistors i72, i74, i80, i82, i84, i86 and NMOS transistors i73, i75, i76, i77, i78, i79, i81, i83, i85, i87. The source terminal of PMOS transistor i72 is connected to the power supply. The gate terminal serves as the bidirectional port B of the edge sampler and the source terminal of NMOS transistor i73 respectively, and the drain terminal is connected to the drain terminal of NMOS transistor i73. The source terminal of PMOS transistor i74 is connected to the power supply. The gate terminal serves as the bidirectional port A of the edge sampler and the gate terminal of NMOS transistor i75 respectively, and the drain terminal is connected to the drain terminal of NMOS transistor i75. The source terminal of NMOS transistor i73 is grounded, and the source terminal of NMOS transistor i75 is grounded. The drain terminal of NMOS transistor i76 serves as the bidirectional port A of the edge sampler, the gate terminal serves as the external data or clock input, and the source terminal is connected to the drain terminal of NMOS transistor i77. The source terminal of NMOS transistor i77 is grounded, and the gate terminal serves as the external reference input. The drain terminal of NMOS transistor i78 serves as the bidirectional port B of the edge sampler, the gate terminal serves as the external data or clock input, and the source terminal is connected to the drain terminal of NMOS transistor i79. The source terminal of NMOS transistor i79 is grounded, and the gate terminal serves as the external reference input.

[0039] The source terminal of PMOS transistor i80 is connected to the power supply. The gate terminal serves as the bidirectional port B of the edge sampler and the source terminal of NMOS transistor i81 respectively, and the drain terminal is connected to the drain terminal of NMOS transistor i81. The source terminal of PMOS transistor i82 is connected to the power supply. The gate terminal serves as the external output port Out_P and the gate terminal of NMOS transistor i83 respectively, and the drain terminal is connected to the drain terminal of NMOS transistor i83. The source terminal of NMOS transistor i81 is grounded, and the source terminal of NMOS transistor i83 is grounded. The source terminal of PMOS transistor i84 is connected to the power supply. The gate terminal serves as the bidirectional port A of the edge sampler, and the drain terminal serves as the external output port Out_P. The source terminal of PMOS transistor i86 is connected to the power supply. The gate terminal serves as the bidirectional port B of the edge sampler, and the drain terminal serves as the external output port Out_N. The source terminal of NMOS transistor i85 is grounded, the gate terminal serves as the bidirectional port A of the edge sampler, and the drain terminal serves as the external output port Out_P. The source terminal of NMOS transistor i87 is grounded, the gate terminal serves as the bidirectional port B of the edge sampler, and the drain terminal serves as the external output port Out_P.

[0040] As Figure 3 shown, the radiation-hardened CDR state machine includes a triple modular redundancy voting module, a counter module, a data phase interpolation code generation module, and an edge phase interpolation code generation module. The voting circuit module receives the sampled data D0...Dn and the sampled edges E0...En, and outputs the voting results Ve[0]Ve[1]...Ve[n] to the counter module after voting. The counter module outputs d0...d5 to the data phase interpolation code generation module and outputs e0...e5 to the edge phase interpolation code generation module after receiving the voting results, and controls the phases of the output data sampling clock and the edge sampling clock through the phase interpolator.

[0041] The phase interpolator is divided into a data phase interpolator and an edge phase interpolator, and includes a phase interpolator decoding module (as shown in Figure 4 ), a phase interpolator reference generation module (as shown in Figure 5 ), and a phase interpolation circuit (as shown in Figure 6 ). The phase interpolator decoding module decodes the interpolation code and outputs it to the phase interpolation circuit, and controls the sampling clock phase of the output through phase interpolation. The reference of both modules comes from the phase interpolator reference generation module;

[0042] The phase interpolator decoding module includes a decoding circuit i26 and flip-flop circuits i27 - i42; the decoding circuit i26 receives the d0...d5 data phase interpolation code and the e0...e5 edge phase interpolation code. After decoding, they are respectively output to the flip-flop circuits i27 - i42. At the same time, 16 flip-flops output 32-bit data A0, A0N, A1, A1N, A2, A2N, A3, A3N,...A15, A15N to the phase interpolation circuit;

[0043] The phase interpolator reference generation module includes PMOS transistor i31, PMOS transistor i32, NMOS transistor i33, NMOS transistor i34, PMOS transistor i35, PMOS transistor i36, NMOS transistor i37, NMOS transistor i38, PMOS transistor i39, PMOS transistor i40, NMOS transistor i41, NMOS transistor i422, PMOS transistor i43, PMOS transistor i44, PMOS transistor i45, PMOS transistor i46, PMOS transistor i47, PMOS transistor i48, PMOS transistor i49, PMOS transistor i50, PMOS transistor i51, PMOS transistor i52, the source of PMOS transistor i53, and PMOS transistor i54.

[0044] The source of PMOS transistor i31 is connected to the power supply, the gate is used as the external reference input terminal VO1, and the drain is connected to the source of PMOS transistor i32; the gate of PMOS transistor i32 is used as the external reference input port VO2, and the drain is connected to the drain of NMOS transistor i33, the gate of NMOS transistor i33, the gate of NMOS transistor i34, and the external output port S; the source of NMOS transistor i33 is grounded; both the source and drain of NMOS transistor i34 are grounded;

[0045] The source of PMOS transistor i35 is connected to the power supply, the gate is used as the external reference input terminal VO1, and the drain is connected to the source of PMOS transistor i36; the gate of PMOS transistor i36 is used as the external reference input port VO2, and the drain is connected to the drain of NMOS transistor i37, the gate of NMOS transistor i37, the gate of NMOS transistor i38, and the external output port P, the bidirectional port OP; the source of NMOS transistor i37 is grounded; both the source and drain of NMOS transistor i38 are grounded;

[0046] The source terminal of PMOS transistor i39 is connected to the power supply, the gate terminal serves as the external reference input terminal VO1, and the drain terminal is connected to the source terminal of PMOS transistor i40; the gate terminal of PMOS transistor i40 serves as the external reference input port VO2, and the drain terminal is connected to the drain terminal of NMOS transistor i41, the gate terminal of NMOS transistor i41, the gate terminal of NMOS transistor i42, and the external output port N, the bidirectional port ON; the source terminal of NMOS transistor i41 is grounded; both the source terminal and the drain terminal of NMOS transistor i42 are grounded;

[0047] The source terminal of PMOS transistor i43 is connected to the power supply and the source terminal of PMOS transistor i44, the gate terminal is connected to the drain terminal, the gate terminal and the drain terminal of PMOS transistor i44, the source terminal of PMOS transistor i45, the source terminal of PMOS transistor i46, the gate terminal of PMOS transistor i45 serves as the external input port A1, the drain terminal of PMOS transistor i45 serves as the external bidirectional port OP, the gate terminal of PMOS transistor i46 serves as the external input port A1N, and the drain terminal of PMOS transistor i46 serves as the external bidirectional port ON;

[0048] The source terminal of PMOS transistor i47 is connected to the power supply and the source terminal of PMOS transistor i48, the gate terminal is connected to the drain terminal, the gate terminal and the drain terminal of PMOS transistor i48, the source terminal of PMOS transistor i49, the source terminal of PMOS transistor i50, the gate terminal of PMOS transistor i49 serves as the external input port A1, the drain terminal of PMOS transistor i49 serves as the bidirectional port OP, the gate terminal of PMOS transistor i50 serves as the external input port A1N, and the drain terminal of PMOS transistor i50 serves as the external bidirectional port ON;

[0049] The source terminal of PMOS transistor i51 is connected to the power supply and the source terminal of PMOS transistor i52, the gate terminal is connected to the drain terminal, the gate terminal and the drain terminal of PMOS transistor i52, the source terminal of PMOS transistor i53, the source terminal of PMOS transistor i54, the gate terminal of PMOS transistor i53 serves as the external input port A15, the drain terminal of PMOS transistor i53 serves as the external bidirectional port OP, the gate terminal of PMOS transistor i54 serves as the external input port A15N, and the drain terminal of PMOS transistor i54 serves as the external bidirectional port ON;

[0050] The phase interpolation circuit in the phase interpolator; includes inverter i55, PMOS transistor i56, PMOS transistor i57, three parallel resistors i58, NMOS transistor i60, NMOS transistor i61, NMOS transistor i62, NMOS transistor i63, NMOS transistor i64, NMOS transistor i65, NMOS transistor i66, NMOS transistor i67, NMOS transistor i68, NMOS transistor i69, NMOS transistor i70, NMOS transistor i71.

[0051] The external input reference port is input from the input end of the inverter i55, and the output end of the inverter i55 is connected to the gate ends of the PMOS transistor i56 and the PMOS transistor i57; the source of the PMOS transistor i56 is connected to the power supply, and the source of the PMOS transistor i57 is connected to the power supply;

[0052] The drain of the PMOS transistor i56 is connected to one end of three parallel resistors i58; the other ends of the three parallel resistors i58 are connected to the drains of the NMOS transistors i60, i63, i66, and i69; the drain of the PMOS transistor i56 is connected to one end of three parallel resistors i58; the other ends of the three parallel resistors i58 are connected to the drains of the NMOS transistors i60, i63, i66, and i69; the drain of the PMOS transistor i57 is connected to one end of three parallel resistors i59; the other ends of the three parallel resistors i59 are connected to the drains of the NMOS transistors i62, i65, i68, and i71;

[0053] The source of the NMOS transistor i60 is connected to the sources of the NMOS transistors i62 and the drain of the NMOS transistor i61; the source of the NMOS transistor i63 is connected to the sources of the NMOS transistors i65 and the drain of the NMOS transistor i64; the source of the NMOS transistor i66 is connected to the sources of the NMOS transistors i68 and the drain of the NMOS transistor i67; the source of the NMOS transistor i69 is connected to the sources of the NMOS transistors i71 and the drain of the NMOS transistor i70;

[0054] The gate of the NMOS transistor i60 is used as the external input terminal clk0, the gate of the NMOS transistor i62 is used as the external input terminal clk180, the gate of the NMOS transistor i63 is used as the external input terminal clk90, the gate of the NMOS transistor i65 is used as the external input terminal clk270, the gate of the NMOS transistor i66 is used as the external input terminal clk180, the gate of the NMOS transistor i68 is used as the external input terminal clk360, the gate of the NMOS transistor i69 is used as the external input terminal clk270, and the gate of the NMOS transistor i71 is used as the external input terminal clk90; the gate of the NMOS transistor i61 is used as the external input port S, and the source is grounded; the gate of the NMOS transistor i64 is used as the external input port P, and the source is grounded; the gate of the NMOS transistor i67 is used as the external input port S, and the source is grounded; the gate of the NMOS transistor i70 is used as the external input port N, and the source is grounded.

[0055] The operation of the entire circuit can be under a frequency clock of 12.5 GHz and can be used in 0.5 Gbps - 12.5 Gbps Serdes transceivers. Under normal operating conditions, the circuit of the present invention uses 28-nanometer process devices of Semiconductor Manufacturing International Corporation, and appropriate device types can also be selected according to the user's own needs to achieve the clock and data recovery functions of the 0.5 Gbps - 12.5 Gbps Serdes high-speed serial interface.

Claims

1. An anti-radiation Serdes transceiver CDR circuit based on phase interpolation, characterized in that: it includes a data sampler, an edge sampler, an anti-radiation CDR state machine, a phase interpolator, and a general PLL based on an LC oscillator; the phase interpolator includes a data phase interpolator and an edge phase interpolator; after the external RXP / RXN receives data, it goes through linear equalizer equalization and decision feedback equalizer for data equalization, and then enters the data sampler and the edge sampler for sampling respectively; the data D0...Dn sampled in the data sampler and the edge data E0...En sampled in the edge sampler enter the anti-radiation CDR state machine; the anti-radiation CDR state machine controls the data phase interpolator by tracking the information of the data D0...Dn and the edge data E0...En, outputs the phase interpolation codes d0...d5 to the data phase interpolator, and outputs the phase interpolation codes e0...e5 to the edge phase interpolator; the anti-radiation CDR state machine controls the data phase interpolator and the edge phase interpolator to output the sampling clocks of the data sampler and the edge sampler, forming a stable negative feedback loop to realize the recovery of the data and clocks output by the data and clock samplers; the data sampler includes PMOS transistors i72, i74, i80, i82, i84, i86, and NMOS transistors i73, i75, i76, i77, i78, i79, i81, i83, i85, i87; the source terminal of PMOS transistor i72 is connected to the power supply, the gate terminal is used as the bidirectional port B of the data sampler and is connected to the gate terminal of NMOS transistor i73, and the drain terminal is connected to the drain terminal of NMOS transistor i73; the source terminal of PMOS transistor i74 is connected to the power supply, the gate terminal is connected to the bidirectional port A and the gate terminal of NMOS transistor i75 respectively, and the drain terminal is connected to the drain terminal of NMOS transistor i75; the source terminal of NMOS transistor i73 is grounded, and the source terminal of NMOS transistor i75 is grounded; the drain terminal of NMOS transistor i76 is connected to the bidirectional port A, the gate terminal is used as an external data or clock input, and the source terminal is connected to the drain terminal of NMOS transistor i77; the source terminal of NMOS transistor i77 is grounded, and the gate terminal is used as an external reference input; the drain terminal of NMOS transistor i78 is used as the bidirectional port B of the data sampler, the gate terminal is used as an external data or clock input, and the source terminal is connected to the drain terminal of NMOS transistor i79; the source terminal of NMOS transistor i79 is grounded, and the gate terminal is used as an external reference input; the source terminal of PMOS transistor i80 is connected to the power supply, the gate terminal is used as the external output terminal Out_N and is connected to the gate terminal of NMOS transistor i81 respectively, and the drain terminal is connected to the drain terminal of NMOS transistor i81; the source terminal of PMOS transistor i82 is connected to the power supply, the gate terminal is used as the external output port Out_P and the gate terminal of NMOS transistor i83 respectively, and the drain terminal is connected to the drain terminal of NMOS transistor i83; the source terminal of NMOS transistor i81 is grounded, and the source terminal of NMOS transistor i83 is grounded; the source terminal of PMOS transistor i84 is connected to the power supply, the gate terminal is used as the bidirectional port A of the data sampler, and the drain terminal is used as the external output port Out_P; The source terminal of PMOS transistor i86 is connected to the power supply, the gate terminal serves as the bidirectional port B of the data sampler, and the drain terminal serves as the external output port Out_N; the source terminal of NMOS transistor i85 is grounded, the gate terminal serves as the bidirectional port A of the data sampler, and the drain terminal serves as the external output port Out_P; the source terminal of NMOS transistor i87 is grounded, the gate terminal serves as the bidirectional port B of the data sampler, and the drain terminal serves as the external output port Out_N; The radiation-hardened CDR state machine includes a triple modular redundancy voting module, a counter module, a data phase interpolation code generation module, and an edge phase interpolation code generation module; the triple modular redundancy voting module receives the sampled data D0...Dn and the sampled edges E0...En, and outputs the voting results Ve[0]Ve[1]...Ve[n] to the counter module after voting; the counter module outputs d0...d5 to the data phase interpolation code generation module after receiving the voting results, and outputs e0...e5 to the edge phase interpolation code generation module at the same time, and controls the phases of the output data sampling clock and the edge sampling clock through the phase interpolator; The data phase interpolator and the edge phase interpolator both include a phase interpolator decoding module, a phase interpolator reference generation module, and a phase interpolation circuit. The phase interpolator decoding module decodes the interpolation code and outputs it to the phase interpolation circuit, and controls the phase of the output sampling clock through phase interpolation. The reference of both modules comes from the phase interpolator reference generation module.

2. A radiation-hardened Serdes transceiver CDR circuit based on phase interpolation according to claim 1, characterized in that: The edge sampler includes PMOS transistors i72, i74, i80, i82, i84, i86, and NMOS transistors i73, i75, i76, i77, i78, i79, i81, i83, i85, i87; the source terminal of PMOS transistor i72 is connected to the power supply, the gate terminals serve as the bidirectional port B of the edge sampler and the source terminal of NMOS transistor i73 respectively, and the drain terminal is connected to the drain terminal of NMOS transistor i73; the source terminal of PMOS transistor i74 is connected to the power supply, the gate terminals serve as the bidirectional port A of the edge sampler and the gate terminal of NMOS transistor i75 respectively, and the drain terminal is connected to the drain terminal of NMOS transistor i75; the source terminal of NMOS transistor i73 is grounded, and the source terminal of NMOS transistor i75 is grounded; the drain terminal of NMOS transistor i76 serves as the bidirectional port A of the edge sampler, the gate terminal serves as the external data or clock input, and the source terminal is connected to the drain terminal of NMOS transistor i77; the source terminal of NMOS transistor i77 is grounded, and the gate terminal serves as the external reference input; the drain terminal of NMOS transistor i78 serves as the bidirectional port B of the edge sampler, the gate terminal serves as the external data or clock input, and the source terminal is connected to the drain terminal of NMOS transistor i79; the source terminal of NMOS transistor i79 is grounded, and the gate terminal serves as the external reference input; The source terminal of PMOS transistor i80 is connected to the power supply. The gate terminal serves as the external output terminal Out_N and the source terminal of NMOS transistor i81 respectively, and the drain terminal is connected to the drain terminal of NMOS transistor i81. The source terminal of PMOS transistor i82 is connected to the power supply. The gate terminal serves as the external output port Out_P and the gate terminal of NMOS transistor i83 respectively, and the drain terminal is connected to the drain terminal of NMOS transistor i83. The source terminal of NMOS transistor i81 is grounded, and the source terminal of NMOS transistor i83 is grounded. The source terminal of PMOS transistor i84 is connected to the power supply. The gate terminal serves as the bidirectional port A of the edge sampler, and the drain terminal serves as the external output port Out_P. The source terminal of PMOS transistor i86 is connected to the power supply. The gate terminal serves as the bidirectional port B of the edge sampler, and the drain terminal serves as the external output terminal Out_N. The source terminal of NMOS transistor i85 is grounded. The gate terminal serves as the bidirectional port A of the edge sampler, and the drain terminal serves as the external output port Out_P. The source terminal of NMOS transistor i87 is grounded. The gate terminal serves as the bidirectional port B of the edge sampler, and the drain terminal serves as the external output terminal Out_N.

3. A phase interpolation based radiation-hardened Serdes transceiver CDR circuit according to claim 2, characterized in that: The phase interpolator decoding module includes a decoding circuit i26 and flip-flop circuits i27 - i42. The decoding circuit i26 receives the data phase interpolation codes d0...d5 and the edge phase interpolation codes e0...e5. After decoding, they are respectively output to the flip-flop circuits i27 - i42. At the same time, 16 flip-flops output 32-bit data A0, A0N, A1, A1N, A2, A2N, A3, A3N,...A15, A15N to the phase interpolation circuit.

4. A phase interpolation based radiation-hardened Serdes transceiver CDR circuit according to claim 2, characterized in that: The phase interpolator reference generation module includes PMOS transistors i31, PMOS transistors i32, NMOS transistors i33, NMOS transistors i34, PMOS transistors i35, PMOS transistors i36, NMOS transistors i37, NMOS transistors i38, PMOS transistors i39, PMOS transistors i40, NMOS transistors i41, NMOS transistors i422, PMOS transistors i43, PMOS transistors i44, PMOS transistors i45, PMOS transistors i46, PMOS transistors i47, PMOS transistors i48, PMOS transistors i49, PMOS transistors i50, PMOS transistors i51, PMOS transistors i52, PMOS transistors i53 source terminals, and PMOS transistors i54; The source terminal of PMOS transistor i31 is connected to the power supply. The gate terminal serves as the external reference input terminal VO1, and the drain terminal is connected to the source terminal of PMOS transistor i32. The gate terminal of PMOS transistor i32 serves as the external reference input port VO2, and the drain terminal is connected to the drain terminal of NMOS transistor i33, the gate terminal of NMOS transistor i33, the gate terminal of NMOS transistor i34, and the external output port S. The source terminal of NMOS transistor i33 is grounded. The source and drain terminals of NMOS transistor i34 are both grounded. The source terminal of PMOS transistor i35 is connected to the power supply, the gate terminal is used as the external reference input terminal VO1, and the drain terminal is connected to the source terminal of PMOS transistor i36; the gate terminal of PMOS transistor i36 is used as the external reference input port VO2, and the drain terminal is connected to the drain terminal of NMOS transistor i37, the gate terminal of NMOS transistor i37, the gate terminal of NMOS transistor i38, and the external output port P, the bidirectional port OP; the source terminal of NMOS transistor i37 is grounded; the source and drain terminals of NMOS transistor i38 are both grounded; The source terminal of PMOS transistor i39 is connected to the power supply, the gate terminal is used as the external reference input terminal VO1, and the drain terminal is connected to the source terminal of PMOS transistor i40; the gate terminal of PMOS transistor i40 is used as the external reference input port VO2, and the drain terminal is connected to the drain terminal of NMOS transistor i41, the gate terminal of NMOS transistor i41, the gate terminal of NMOS transistor i42, and the external output port N, the bidirectional port ON; the source terminal of NMOS transistor i41 is grounded; the source and drain terminals of NMOS transistor i42 are both grounded; The source terminal of PMOS transistor i43 is connected to the power supply and the source terminal of PMOS transistor i44, the gate terminal is connected to the drain terminal, the gate and drain terminals of PMOS transistor i44, the source terminal of PMOS transistor i45, the source terminal of PMOS transistor i46, the gate terminal of PMOS transistor i45 is used as the external input port A1, the drain terminal of PMOS transistor i45 is used as the external bidirectional port OP, the gate terminal of PMOS transistor i46 is used as the external input port A1 N, and the drain terminal of PMOS transistor i46 is used as the external bidirectional port ON; The source terminal of PMOS transistor i47 is connected to the power supply and the source terminal of PMOS transistor i48, the gate terminal is connected to the drain terminal, the gate and drain terminals of PMOS transistor i48, the source terminal of PMOS transistor i49, the source terminal of PMOS transistor i50, the gate terminal of PMOS transistor i49 is used as the external input port A2, the drain terminal of PMOS transistor i49 is used as the bidirectional port OP, the gate terminal of PMOS transistor i50 is used as the external input port A2N, and the drain terminal of PMOS transistor i50 is used as the external bidirectional port ON; The source terminal of PMOS transistor i51 is connected to the power supply and the source terminal of PMOS transistor i52, the gate terminal is connected to the drain terminal, the gate and drain terminals of PMOS transistor i52, the source terminal of PMOS transistor i53, the source terminal of PMOS transistor i54, the gate terminal of PMOS transistor i53 is used as the external input port A15, the drain terminal of PMOS transistor i53 is used as the external bidirectional port OP, the gate terminal of PMOS transistor i54 is used as the external input port A15N, and the drain terminal of PMOS transistor i54 is used as the external bidirectional port ON.

5. The anti-radiation Serdes transceiver CDR circuit based on phase interpolation according to claim 2, characterized in that: the phase interpolation circuit in the phase interpolator; comprises an inverter i55, PMOS transistors i56, i57, three parallel resistors i58, three parallel resistors i59, NMOS transistors i60, i61, i62, i63, i64, i65, i66, i67, i68, i69, i70, i71; The external input reference port is input from the input terminal of inverter i55, and the output terminal of inverter i55 is connected to the gate terminals of PMOS transistor i56 and PMOS transistor i57; The source terminal of PMOS transistor i56 is connected to the power supply, and the source terminal of PMOS transistor i57 is connected to the power supply; The drain terminal of PMOS transistor i56 is connected to one end of three parallel resistors i58; the other ends of the three parallel resistors i58 are connected to the drain terminals of NMOS transistors i60, i63, i66, and i69; the drain terminal of PMOS transistor i57 is connected to one end of three parallel resistors i59; the other ends of the three parallel resistors i59 are connected to the drain terminals of NMOS transistors i62, i65, i68, and i71; The source terminal of NMOS transistor i60 is connected to the source terminals of NMOS transistors i62 and the drain terminal of NMOS transistor i61; the source terminal of NMOS transistor i63 is connected to the source terminals of NMOS transistors i65 and the drain terminal of NMOS transistor i64; the source terminal of NMOS transistor i66 is connected to the source terminals of NMOS transistors i68 and the drain terminal of NMOS transistor i67; the source terminal of NMOS transistor i69 is connected to the source terminals of NMOS transistors i71 and the drain terminal of NMOS transistor i70; The gate terminal of NMOS transistor i60 serves as the external input terminal clk0, the gate terminal of NMOS transistor i62 serves as the external input terminal clk180, the gate terminal of NMOS transistor i63 serves as the external input terminal clk90, the gate terminal of NMOS transistor i65 serves as the external input terminal clk270, the gate terminal of NMOS transistor i66 serves as the external input terminal clk180, the gate terminal of NMOS transistor i68 serves as the external input terminal clk360, the gate terminal of NMOS transistor i69 serves as the external input terminal clk270, and the gate terminal of NMOS transistor i71 serves as the external input terminal clk90; the gate terminal of NMOS transistor i61 serves as the external input port S, and the source terminal is grounded; the gate terminal of NMOS transistor i64 serves as the external input port P, and the source terminal is grounded; the gate terminal of NMOS transistor i67 serves as the external input port S, and the source terminal is grounded; the gate terminal of NMOS transistor i70 serves as the external input port N, and the source terminal is grounded.

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