A digital phase-locked loop, phase-locking method and electronic device

Abstract

This application provides a digital phase-locked loop (PLL), a PLL method, and an electronic device. The PLL includes a phase detection unit, a voltage-controlled oscillator (VCO), a central processing unit (CPU), and a digital-to-analog converter (DAC). The phase detection unit includes a mixer. The phase detection unit receives an externally input reference signal and a fundamental signal output from the VCO, performs phase detection based on the reference signal and the fundamental signal, and sends the resulting digital phase detection voltage to the CPU. The CPU performs preset type signal processing based on the digital phase detection voltage to obtain a target control word and sends the target control word to the DAC. The DAC outputs a control voltage according to the target control word to adjust the fundamental signal output by the VCO and achieve closed-loop locking. This application utilizes a mixer instead of an expensive digital phase detector for phase detection, achieving PLL locking and enabling the system to operate normally with high performance.

Description

Technical Field

[0001] This application relates to the field of electronic communications, and in particular to a digital phase-locked loop, a phase-locking method, and an electronic device. Background Technology

[0002] A phase-locked loop (PLL) is a negative feedback control system that uses a voltage generated by phase synchronization to tune a voltage-controlled oscillator (VCO) to produce a target frequency. According to automatic control principles, this is a typical feedback control circuit that uses an externally input reference signal to control the frequency and phase of the oscillation signal within the loop, achieving automatic tracking of the output signal frequency to the input signal frequency. It is generally used in closed-loop tracking circuits.

[0003] Phase-locked loops (PLLs) are widely used in various fields of science and technology industry. Among them, digital PLLs are more commonly used due to their ability to maintain the reference even when interrupted and their large locking time constant. However, current digital PLLs are generally implemented using expensive digital phase detectors, which makes it difficult to achieve the required cost and ease of implementation. Furthermore, the testing stability of digital phase detectors themselves cannot meet the requirements for high detection accuracy.

[0004] Therefore, existing technologies suffer from high costs and low detection accuracy. Summary of the Invention

[0005] To address the aforementioned technical problems, this application provides a digital phase-locked loop, a phase-locking method, and an electronic device, the specific solutions of which are as follows:

[0006] In a first aspect, embodiments of this application provide a digital phase-locked loop, which includes a phase detection unit, a voltage-controlled oscillator, a central processing unit, and a digital-to-analog converter, wherein the phase detection unit includes a mixer;

[0007] The phase detection unit is used to receive an externally input reference signal and a base signal output by the voltage-controlled oscillator, perform phase detection based on the reference signal and the base signal, and send the obtained digital phase detection voltage to the central processing unit.

[0008] The central processing unit is used to perform a preset type of signal processing based on the digital phase detector voltage to obtain a target control word and send the target control word to the digital-to-analog converter, wherein the preset type of signal processing includes proportional-integral-differential operations;

[0009] The digital-to-analog converter is used to output a control voltage according to the target control word, so as to adjust the basic signal output by the voltage-controlled oscillator and achieve closed-loop locking.

[0010] According to a specific embodiment disclosed in this application, the digital phase-locked loop further includes an isolation unit, which includes a first isolator and a second isolator. The first isolator is connected between the input terminal of the reference signal and the phase detection unit, and the second isolator is connected between the voltage-controlled oscillator and the phase detection unit.

[0011] The first isolator is used to isolate the input terminal of the reference signal from the phase detector unit;

[0012] The second isolator is used to isolate the voltage-controlled oscillator and the phase detector unit.

[0013] According to a specific embodiment disclosed in this application, the phase detection unit further includes a low-pass filter and an analog-to-digital converter;

[0014] The mixer is used to receive an externally input reference signal and a base signal output by the voltage-controlled oscillator, perform mixing based on the reference signal and the base signal, and send the resulting initial mixed signal to the low-pass filter. The initial mixed signal includes a sum frequency component and a difference frequency component.

[0015] The low-pass filter is used to filter out the difference frequency component in the initial mixing signal to obtain the target mixing signal and send the target mixing signal to the digital-to-analog converter;

[0016] The analog-to-digital converter is used to convert the target mixing signal into a digital signal and send the digital signal to the central processing unit.

[0017] According to a specific embodiment disclosed in this application, the phase detection unit further includes a variable gain amplifier, which is connected to the low-pass filter, the analog-to-digital converter, and the central processing unit respectively.

[0018] The variable gain amplifier is used to receive the target mixing signal from the low-pass filter, amplify the target mixing signal according to the current gain coefficient, obtain the target amplified signal, and send the target amplified signal to the analog-to-digital converter. The gain coefficient of the variable gain amplifier is configured in real time by the central processing unit.

[0019] Secondly, embodiments of this application provide a phase-locked loop method applied to the digital phase-locked loop described in any one of the first aspects, the phase-locked loop method comprising:

[0020] The phase detection unit receives an externally input reference signal and a base signal output by a voltage-controlled oscillator, performs phase detection based on the reference signal and the base signal, and sends the obtained digital phase detection voltage to the central processing unit.

[0021] The central processing unit performs a preset type of signal processing based on the digital phase detector voltage to obtain a target control word and sends the target control word to the digital-to-analog converter. The preset type of signal processing includes proportional-integral-differential operations.

[0022] The digital-to-analog converter outputs a control voltage according to the target control word to adjust the basic signal output by the voltage-controlled oscillator and achieve closed-loop locking.

[0023] According to a specific embodiment disclosed in this application, the digital phase-locked loop further includes an isolation unit, which includes a first isolator and a second isolator. The first isolator is connected between the input terminal of the reference signal and the phase detection unit, and the second isolator is connected between the voltage-controlled oscillator and the phase detection unit. The phase-locking method further includes:

[0024] The first isolator isolates the input terminal of the reference signal from the phase detector unit;

[0025] The second isolator isolates the voltage-controlled oscillator and the phase detector unit.

[0026] According to a specific embodiment disclosed in this application, the phase detection unit further includes a low-pass filter and an analog-to-digital converter, and the phase-locked loop method further includes:

[0027] The mixer receives an externally input reference signal and a base signal output by the voltage-controlled oscillator, performs mixing based on the reference signal and the base signal, and sends the resulting initial mixed signal to the low-pass filter. The initial mixed signal includes a sum frequency component and a difference frequency component.

[0028] The low-pass filter removes the difference frequency component from the initial mixing signal to obtain the target mixing signal, and sends the target mixing signal to the digital-to-analog converter.

[0029] The analog-to-digital converter converts the target mixing signal into a digital signal and sends the digital signal to the central processing unit.

[0030] According to a specific embodiment disclosed in this application, the phase detection unit further includes a variable gain amplifier, which is connected to the low-pass filter, the analog-to-digital converter, and the central processing unit respectively. The phase-locked loop method further includes:

[0031] The variable gain amplifier receives the target mixing signal from the low-pass filter, amplifies the target mixing signal according to the current gain coefficient, obtains the target amplified signal, and sends the target amplified signal to the analog-to-digital converter. The gain coefficient of the variable gain amplifier is configured in real time by the central processing unit.

[0032] Thirdly, embodiments of this application provide an electronic device, which includes a processing device and a memory. The memory stores a computer program, which, when executed on the processor, implements the phase-locked loop method described in any embodiment of the second aspect.

[0033] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program that, when executed on a processing device, implements the phase-locked loop method described in any embodiment of the second aspect.

[0034] Compared with the prior art, this application has the following beneficial effects:

[0035] The digital phase-locked loop (PLL) provided in this application includes a phase detection unit, a voltage-controlled oscillator (VCO), a central processing unit (CPU), and a digital-to-analog converter (DAC). The phase detection unit includes a mixer. The phase detection unit receives an externally input reference signal and a base signal output from the VCO, performs phase detection based on the reference signal and the base signal, and sends the resulting digital phase detection voltage to the CPU. The CPU performs preset type signal processing based on the digital phase detection voltage to obtain a target control word and sends the target control word to the DAC. The DAC outputs a control voltage according to the target control word to adjust the base signal output by the VCO and achieve closed-loop locking. This application utilizes a mixer instead of an expensive digital phase detector for phase detection, achieving PLL locking and enabling the system to operate normally with high performance. Attached Figure Description

[0036] To more clearly illustrate the technical solution of the present invention, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope of protection of the present invention. In the various drawings, similar components are numbered similarly.

[0037] Figure 1 This is a schematic diagram of the system composition of a digital phase-locked loop in the prior art;

[0038] Figure 2 A schematic diagram of the system composition of a digital phase-locked loop provided in this application embodiment.

[0039] Figure 3 A schematic flowchart of a phase-locked loop method provided in an embodiment of this application;

[0040] Figure 4 This is an exemplary structural diagram of an electronic device provided in an embodiment of this application. Detailed Implementation

[0041] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0042] The components of the embodiments of this application described and illustrated in the accompanying drawings can be arranged and designed in a variety of different configurations. Therefore, the following detailed description of the embodiments of this application provided in the drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0043] In the following, the terms “comprising,” “having,” and their cognates, which may be used in various embodiments of this application, are intended only to indicate a particular feature, number, step, operation, element, component, or combination thereof, and should not be construed as excluding, firstly, the presence of one or more other features, numbers, steps, operations, elements, components, or combinations thereof, or adding the possibility of one or more features, numbers, steps, operations, elements, components, or combinations thereof.

[0044] Furthermore, the terms "first," "second," and "third" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0045] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the various embodiments of this application pertain. Terms (such as those defined in commonly used dictionaries) shall be interpreted as having the same meaning as in their contextual meaning in the relevant technical field and shall not be construed as having an idealized or overly formal meaning, unless clearly defined in the various embodiments of this application.

[0046] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0047] Phase-locked loop (PLL) is a technique that controls the phase of a controlled oscillator (ROL) using a standard or external signal. It is used to achieve phase synchronization with or track the frequency or phase of an external signal. PLL is short for phase-locked, meaning phase synchronization between two signals. See also... Figure 1 , Figure 1 This is a schematic diagram of the system composition of a digital phase-locked loop in the prior art. For example... Figure 1 As shown, the digital phase-locked loop 100 includes a frequency and phase detector 110, a central processing unit 120, a digital-to-analog converter module 130, and a local voltage-controlled oscillator 140.

[0048] In practice, after the reference signal is input to the digital phase-locked loop 100, it is first transmitted to the frequency and phase detector 110, and then together with the output frequency sent by the local voltage-controlled oscillator 140, it is subjected to frequency and phase discrimination. The obtained digital information is transmitted to the central processing unit 120 for data processing, and the calculated digital to analog converter (DAC) control word is used to control the output voltage of the DAC module 130, thereby achieving the purpose of controlling the output frequency of the local voltage-controlled oscillator (VCO) 140.

[0049] While existing digital phase-locked loops can achieve phase-locked loop locking, they cannot achieve higher-precision phase locking due to the resolution limitations of frequency and phase detectors.

[0050] See Figure 2 , Figure 2 This is a schematic diagram of the system composition of a digital phase-locked loop provided in an embodiment of this application. Figure 2 As shown, the digital phase-locked loop 200 includes a phase detector unit 210, a voltage-controlled oscillator 220, a central processing unit 230, and a digital-to-analog converter 240, wherein the phase detector unit 210 includes a mixer 211.

[0051] Compared to the phase-locked loop (PLL) in existing technologies, this application innovatively introduces a mixer 211 for phase detection. The mixer 211, also known as a "frequency converter," is used to convert the frequency of an input signal to another frequency. The RF mixer 211 has three ports: RF, IF, and LO, two of which are input ports and one is an output port. For example, for upconversion, IF and LO are used as input ports, and the RF port is used as the output port; for downconversion, RF and LO are used as input ports, and the IF port is used as the output port.

[0052] The phase detector unit 210 refers to a device capable of identifying the phase difference of input signals. It is a circuit that establishes a definite relationship between the output voltage and the phase difference between the two input signals. This is similar to everyone dancing to music. A dance instructor notices that everyone's movements are out of sync with the music, lagging behind by half a beat (i.e., there's a phase difference), so they change to slower music so everyone can keep up. The function of the phase detector unit is like a phase monitoring mechanism, detecting the phase difference between the input signal and the feedback signal, and then representing this difference in a reasonable way; this representation is voltage.

[0053] A voltage-controlled oscillator 220 refers to an oscillation circuit whose output frequency corresponds to the input control voltage; the frequency is a function of the input signal voltage. A voltage-controlled oscillator 220 can be constructed by controlling the operating state of the oscillator or the component parameters of the oscillation circuit with the input control voltage.

[0054] In specific implementation, the phase detection unit 210 is used to receive the externally input reference signal and the basic signal output by the voltage-controlled oscillator 220, perform phase detection based on the reference signal and the basic signal, and send the obtained digital phase detection voltage to the central processing unit 230.

[0055] The central processing unit 230 is used to perform a preset type of signal processing based on the digital phase detector voltage to obtain a target control word and send the target control word to the digital-to-analog converter 240, wherein the preset type of signal processing includes proportional-integral-differential operations;

[0056] The digital-to-analog converter 240 is used to output a control voltage according to the target control word to adjust the basic signal output by the voltage-controlled oscillator 220 and achieve closed-loop locking.

[0057] In a specific implementation, the digital phase-locked loop 200 further includes an isolation unit 250, which includes a first isolator 251 and a second isolator 252. The first isolator 251 is connected between the input terminal of the reference signal and the phase detection unit 210, and the second isolator 252 is connected between the voltage-controlled oscillator 220 and the phase detection unit 210.

[0058] The first isolator 251 is used to isolate the input terminal of the reference signal from the phase detector unit 210;

[0059] The second isolator 252 is used to isolate the voltage-controlled oscillator 220 and the phase detector unit 210.

[0060] The function of an isolator is to isolate the output from the input. That is, when the device is operating normally, stray signals may occur due to user operations. Adding a first isolator and / or a second isolator prevents these stray signals from affecting the input performance, thus protecting the input signal. It should be noted that the first and second isolators in this application can be selected with different isolation levels based on actual usage requirements and specific application scenarios; no further limitations are made here.

[0061] In a specific implementation, the phase detection unit 210 further includes a low-pass filter 212 and an analog-to-digital converter 213;

[0062] The mixer 211 is used to receive an externally input reference signal and a base signal output by the voltage-controlled oscillator 220, perform mixing based on the reference signal and the base signal, and send the resulting initial mixed signal to the low-pass filter 212. The initial mixed signal includes a sum frequency component and a difference frequency component.

[0063] The low-pass filter 212 is used to filter out the difference frequency component in the initial mixing signal to obtain the target mixing signal and send the target mixing signal to the digital-to-analog converter 240;

[0064] The analog-to-digital converter 213 is used to convert the target mixing signal into a digital signal and send the digital signal to the central processing unit 230.

[0065] Specifically, the reference signal is input to the RF terminal of the mixer 211 via the first isolator 251, and its time-frequency function is sin(ω). r t), where the initial phase is not considered, and ω r The reference frequency corresponds to the reference signal; the fundamental signal is input to the IF terminal of mixer 211 via the second isolator 252, and its time-frequency function is sin(ω). i t), where the initial phase is not considered, and ω i This is the fundamental frequency corresponding to the fundamental signal. After phase detection by mixer 211, the reference signal and the fundamental signal generate the initial mixing signal LO, whose time-frequency function is 1 / 2{cos[(ω... r -ω i )t]+cos[(ω r +ω i Here, fixed phase is not considered. At this point, the time-frequency function corresponding to the initial mixing signal contains both sum-frequency and difference-frequency components.

[0066] After filtering the initial mixing signal through low-pass filter 212, the sum frequency component is removed, leaving only the difference frequency component 1 / 2cos[(ω r -ω i [t], which is the target mixing signal mentioned above. Then, the target mixing signal is converted into a digital signal via a digital-to-analog converter 240, and the digital signal is sent to the central processing unit 230 for subsequent data processing. Furthermore, after the phase-locked loop is locked, the expected value of the observed difference frequency component will be at a very small and stable value, only when ω... r -ω i The condition is true when = 0, therefore it can be determined that the fundamental frequency corresponding to the fundamental signal is equal to the reference frequency corresponding to the reference signal.

[0067] In a specific implementation, the phase detection unit 210 further includes a variable gain amplifier 214, which is connected to the low-pass filter 212, the analog-to-digital converter 213 and the central processing unit 230 respectively.

[0068] The variable gain amplifier 214 is used to receive the target mixing signal from the low-pass filter 212, amplify the target mixing signal according to the current gain coefficient, obtain the target amplified signal, and send the target amplified signal to the analog-to-digital converter 213. The gain coefficient of the variable gain amplifier 214 is configured in real time by the central processing unit 230.

[0069] Using the technical solution described above, this application innovatively inputs the reference signal and the basic signal into the mixer 211 after passing through the first isolator 251 and the second isolator 252, respectively. However, the detection accuracy of the analog-to-digital converter 213 is not very high at this point. For example, the peak-to-peak value of the difference frequency signal output by the mixer 211 is approximately 0.7V when the phase-locked loop (PLL) is not locked, and approximately 10µV when the PLL is locked. A difference frequency signal of this amplitude is difficult to detect directly using a conventional PLL 213. However, after the difference frequency signal is amplified, regardless of whether the PLL is locked, the amplitude of the output difference frequency signal can be controlled to approximately 1V, which can greatly improve the detection accuracy of the analog-to-digital converter 213, thereby improving the stability of the detection. This enables the realization of a high-performance digital phase-locked loop 200.

[0070] Therefore, the difference frequency signal output by the mixer 211, i.e., the target mixed signal, can be appropriately amplified by the variable gain amplifier 214 to improve the resolution of digital detection. Specifically, the variable gain amplifier 214 can be added between the mixer 211 and the analog-to-digital converter 213 to improve the detection accuracy of the analog-to-digital converter 213.

[0071] After detection by the analog-to-digital converter 213, the analog signal corresponding to the target mixing signal is converted into a digital signal and input to the central processing unit 230 for digital calculation. The central processing unit 230 can dynamically adjust the gain coefficient of the variable gain amplifier 214 according to the acquired digital signal, so that the acquisition range of the analog-to-digital converter 213 is within a reasonable range. Taking a reference frequency stability of ≈1E-13 and a fundamental frequency stability of ≈1E-13 as an example, when the phase-locked loop is locked, the peak-to-peak value Vpp of the difference frequency signal output by the mixer 211 is ≈12uV. The gain coefficient of the variable gain amplifier 214 can be configured to 200000. At this time, the output amplitude of the variable gain amplifier 214 is ≈2.4V, which is suitable for detection by the analog-to-digital converter 213. At the same time, after analysis, considering the detection error of the analog-to-digital converter 213, if a 12-bit analog-to-digital converter 213 is used, its detection sensitivity can be converted to the order of ≈1E-15 stability, which is very good. When using an analog-to-digital converter 213 with a higher bit depth, the sampling dynamic range is wider.

[0072] This application inputs the target mixed signal, processed by a mixer, to a variable gain amplifier for adaptive amplification: when the phase-locked loop (PLL) is not locked, the variable gain amplifier is in low-gain mode, facilitating rapid PLL locking; when the PLL is initially locked, the variable gain amplifier is in high-gain mode, facilitating better locking performance. Based on the stability of the reference frequency corresponding to the reference signal and the fundamental frequency corresponding to the fundamental signal, multiple gain modes can be flexibly set according to actual usage requirements and specific application scenarios, such as locking, preheating and waiting of the voltage-controlled oscillator (VCO), and deep tracking configuration. The digital PLL provided in this application, through the use of a mixer for phase detection and the coordinated operation of the variable gain amplifier, enables the PLL to operate normally under extremely high performance, achieving high stability for digital phase locking.

[0073] Corresponding to the above system embodiments, see [link to relevant documentation]. Figure 3 This application also provides a phase-locked loop (PLL) method, the PLL method comprising:

[0074] Step S301: The phase detection unit receives the externally input reference signal and the basic signal output by the voltage-controlled oscillator, performs phase detection based on the reference signal and the basic signal, and sends the obtained digital phase detection voltage to the central processing unit.

[0075] Step S302: The central processing unit performs a preset type of signal processing based on the digital phase detector voltage to obtain a target control word and sends the target control word to the digital-to-analog converter. The preset type of signal processing includes proportional-integral-differential operations.

[0076] In step S303, the digital-to-analog converter outputs a control voltage according to the target control word to adjust the basic signal output by the voltage-controlled oscillator and achieve closed-loop locking.

[0077] In specific implementation, the digital phase-locked loop further includes an isolation unit, which includes a first isolator and a second isolator. The first isolator is connected between the input terminal of the reference signal and the phase detection unit, and the second isolator is connected between the voltage-controlled oscillator and the phase detection unit. The phase-locking method further includes:

[0078] The first isolator isolates the input terminal of the reference signal from the phase detector unit;

[0079] The second isolator isolates the voltage-controlled oscillator and the phase detector unit.

[0080] In specific implementation, the phase detection unit further includes a low-pass filter and an analog-to-digital converter, and the phase-locked loop method further includes:

[0081] The mixer receives an externally input reference signal and a base signal output by the voltage-controlled oscillator, performs mixing based on the reference signal and the base signal, and sends the resulting initial mixed signal to the low-pass filter. The initial mixed signal includes a sum frequency component and a difference frequency component.

[0082] The low-pass filter removes the difference frequency component from the initial mixing signal to obtain the target mixing signal, and sends the target mixing signal to the digital-to-analog converter.

[0083] The analog-to-digital converter converts the target mixing signal into a digital signal and sends the digital signal to the central processing unit.

[0084] In a specific implementation, the phase detection unit further includes a variable gain amplifier, which is connected to the low-pass filter, the analog-to-digital converter, and the central processing unit. The phase-locked loop method further includes:

[0085] The variable gain amplifier receives the target mixing signal from the low-pass filter, amplifies the target mixing signal according to the current gain coefficient, obtains the target amplified signal, and sends the target amplified signal to the analog-to-digital converter. The gain coefficient of the variable gain amplifier is configured in real time by the central processing unit.

[0086] The specific implementation process of the phase-locked loop method provided in this application can be found in the specific implementation process of the digital phase-locked loop provided in the above embodiments, and will not be repeated here.

[0087] The phase-locked loop (PLL) method provided in this application inputs the target mixed signal, processed by a mixer, to a variable gain amplifier for adaptive amplification. When the PLL is not locked, the variable gain amplifier is in low-gain mode, facilitating rapid PLL locking. When the PLL is initially locked, the variable gain amplifier is in high-gain mode, ensuring better locking performance. Based on the stability of the reference frequency corresponding to the reference signal and the fundamental frequency corresponding to the fundamental signal, multiple gain modes can be flexibly set according to actual usage requirements and specific application scenarios, such as locking, preheating and waiting of the voltage-controlled oscillator (VCO), and deep tracking configuration. By utilizing a mixer for phase detection and the coordinated operation of the variable gain amplifier, this application enables the PLL to operate normally under extremely high performance, achieving high stability for digital phase-locking.

[0088] In this application embodiment, an electronic device is provided, the electronic device including a processing device and a memory, the processing device being loaded with a digital phase-locked loop as described in any of the embodiments of this application, the memory storing a computer program, and the computer program implementing the phase-locking method as described in any of the embodiments of this application when executed on the processor.

[0089] Figure 4 The illustration shows a method for implementing embodiments of the present application or an electronic device 400 for implementing embodiments of the present application. In some embodiments, more or fewer electronic devices may be included than illustrated. In some embodiments, implementation may be carried out using a single or multiple electronic devices. In some embodiments, implementation may be carried out using cloud-based or distributed electronic devices.

[0090] like Figure 4 As shown, the electronic device 400 includes a processor 401, which can perform various appropriate operations and processes based on programs and / or data stored in read-only memory (ROM) 402 or programs and / or data loaded from storage portion 408 into random access memory (RAM) 403. The processor 401 may be a multi-core processor or may contain multiple processors. In some embodiments, the processor 401 may include a general-purpose main processor and one or more special coprocessors, such as a central processing unit (CPU), graphics processing unit (GPU), neural network processor (NPU), digital signal processor (DSP), etc. Various programs and data required for the operation of the electronic device 400 are also stored in RAM 403. The processor 401, ROM 402, and RAM 403 are interconnected via bus 404. An input / output (I / O) interface 405 is also connected to bus 404.

[0091] The processor and memory described above are used together to execute programs stored in the memory. When the program is executed by a computer, it can implement the methods, steps, or functions described in the above embodiments.

[0092] The following components are connected to I / O interface 405: an input section 406 including a keyboard, mouse, touchscreen, etc.; an output section 407 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and speakers, etc.; a storage section 408 including a hard disk, etc.; and a communication section 409 including a network interface card such as a LAN card, modem, etc. The communication section 409 performs communication processing via a network such as the Internet. A drive 410 is also connected to I / O interface 405 as needed. A removable medium 411, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed on drive 410 as needed so that computer programs read from it can be installed into storage section 408 as needed. Figure 4 The diagram only shows a portion of the components and does not imply that the computer system 400 includes only a few components. Figure 4 The components shown.

[0093] The systems, devices, modules, or units described in the above embodiments can be implemented by a computer or its associated components. The computer may be, for example, a mobile terminal, smartphone, personal computer, laptop computer, in-vehicle human-machine interface device, personal digital assistant, media player, navigation device, game console, tablet computer, wearable device, smart TV, Internet of Things system, smart home, industrial computer, server, or a combination thereof.

[0094] In this application embodiment, a computer-readable storage medium is provided, the computer-readable storage medium storing a computer program, the computer program being configured to execute any phase-locked method of this application embodiment when run.

[0095] The storage media in embodiments of this application include articles that can store information using any method or technology, whether permanent or non-permanent, removable or non-removable. Examples of storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic magnetic disk storage or other magnetic storage devices, or any other non-transfer medium that can be used to store information that can be accessed by a computing device.

[0096] The methods, programs, systems, apparatuses, etc., of the embodiments of this application can be executed or implemented in one or more networked computers, or practiced in a distributed computing environment. In the embodiments of this specification, in these distributed computing environments, tasks can be performed by remote processing devices connected via a communication network.

[0097] The specific implementation process of the provided electronic device and computer-readable storage medium can be found in the specific implementation process of the phase-locked loop method provided in the above embodiments, and will not be repeated here.

[0098] The electronic device and computer-readable storage medium provided in this application input the target mixed signal processed by the mixer to a variable gain amplifier for adaptive amplification: when the phase-locked loop (PLL) is not locked, the variable gain amplifier is in a low-gain mode, which facilitates rapid PLL locking; when the PLL is initially locked, the variable gain amplifier is in a high-gain mode, which facilitates better locking performance. Based on the stability of the reference frequency corresponding to the reference signal and the fundamental frequency corresponding to the fundamental signal, multiple gain modes can be flexibly set according to actual usage requirements and specific application scenarios, such as locking, preheating and waiting of the voltage-controlled oscillator (VCO), and deep tracking configuration. This application, by utilizing a mixer for phase detection and the coordinated operation of the variable gain amplifier, enables the PLL to operate normally under extremely high performance, achieving high stability for digital phase locking.

[0099] Those skilled in the art will understand that the embodiments described in this specification can be provided as methods, systems, or computer program products. Therefore, those skilled in the art will realize that the functional modules / units or controllers and related method steps described in the above embodiments can be implemented in software, hardware, or a combination of both.

[0100] Unless explicitly stated otherwise, the actions or steps of the methods and procedures described in the embodiments of this application do not necessarily have to be performed in a specific order and can still achieve the desired results. In some implementations, multitasking and parallel processing are also possible or may be advantageous.

[0101] This document describes several embodiments of the present application; however, for the sake of brevity, the descriptions of the embodiments are not exhaustive, and identical or similar features or parts between the embodiments may be omitted. In this document, "one embodiment," "some embodiments," "example," "specific example," or "some examples" refers to at least one embodiment or example applicable to the present application, but not all embodiments. The above terms do not necessarily refer to the same embodiment or example. Without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of the different embodiments or examples.

[0102] The exemplary systems and methods of this application have been specifically shown and described with reference to the above embodiments, which are merely examples of the best mode for implementing the systems and methods. Those skilled in the art will understand that various changes can be made to the embodiments of the systems and methods described herein without departing from the spirit and scope of this application as defined in the appended claims when implementing the systems and / or methods.

Claims

1. A digital phase-locked loop, characterized by The digital phase-locked loop comprises a phase discriminator, a low-pass filter, a variable gain amplifier, an analog-to-digital converter, a voltage-controlled oscillator, a central processing unit, a digital-to-analog converter, wherein the phase discriminator comprises a frequency mixer; The phase discriminator is configured to receive an externally input reference signal and a base signal output by the voltage-controlled oscillator, perform phase discrimination based on the reference signal and the base signal, and send a digital phase discrimination voltage obtained to the central processing unit; The central processing unit is configured to perform preset type signal processing based on the digital phase discrimination voltage, obtain a target control word, and send the target control word to the digital-to-analog converter, wherein the preset type signal processing comprises proportional integral derivative operation; The digital-to-analog converter is configured to output a control voltage according to the target control word, to adjust the base signal output by the voltage-controlled oscillator and realize closed-loop locking; The digital phase-locked loop further comprises an isolation unit, the isolation unit comprising a first isolator and a second isolator, the first isolator being connected between an input end of a reference signal and the phase discriminator, and the second isolator being connected between the voltage-controlled oscillator and the phase discriminator; The first isolator is configured to isolate the input end of the reference signal and the phase discriminator; The second isolator is configured to isolate the voltage-controlled oscillator and the phase discriminator The frequency mixer is configured to receive an externally input reference signal and a base signal output by the voltage-controlled oscillator, perform frequency mixing based on the reference signal and the base signal, and send an initial frequency mixing signal obtained to the low-pass filter, wherein the initial frequency mixing signal comprises sum frequency component and difference frequency component; The low-pass filter is configured to filter out the sum frequency component in the initial frequency mixing signal, obtain a target frequency mixing signal, and send the target frequency mixing signal to the digital-to-analog converter; The analog-to-digital converter is configured to convert the target frequency mixing signal into a digital signal, and send the digital signal to the central processing unit 2. A method of phase locking, characterized by, The variable gain amplifier is connected to the low-pass filter, the analog-to-digital converter, and the central processing unit, respectively; The variable gain amplifier is configured to receive the target frequency mixing signal of the low-pass filter, amplify the target frequency mixing signal according to a current gain coefficient, obtain a target amplified signal, and send the target amplified signal to the analog-to-digital converter, wherein the gain coefficient of the variable gain amplifier is configured in real time by the central processing unit. The phase-locked method applied to the digital phase-locked loop in claim 1 comprises: receiving an externally input reference signal, performing phase discrimination based on the reference signal and a base signal to obtain a digital phase discrimination voltage, wherein the base signal is output by a voltage-controlled oscillator; performing preset type signal processing based on the digital phase discrimination voltage to obtain a target control word, and sending the target control word to a digital-to-analog converter, wherein the preset type signal processing comprises proportional integral derivative operation; outputting a control voltage according to the target control word, to adjust the base signal output by the voltage-controlled oscillator and realize closed-loop locking; the first isolator isolates the input end of the reference signal and the phase discriminator; The second isolator isolates the voltage-controlled oscillator and the phase discriminator unit; The mixer receives an externally input reference signal and a base signal output by the voltage-controlled oscillator, mixes the reference signal and the base signal to obtain an initial mixed signal, wherein the initial mixed signal includes sum frequency components and difference frequency components; The sum frequency components in the initial mixed signal are filtered out to obtain a target mixed signal; The target mixed signal is amplified according to a current gain coefficient to obtain a target amplified signal, wherein the gain coefficient is configured by the central processing unit in real time; The target amplified signal is converted into a digital signal.

3. An electronic device, comprising: The electronic device comprises a processing device and a memory, and the memory stores a computer program which, when executed on the processor, implements the phase-locked method in claim 2.

4. A computer-readable storage medium, characterized in that, The computer readable storage medium stores a computer program which, when executed on a processing device, implements the phase-locked method in claim 2.

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