Nested Δ-Σ Analog-to-Digital Conversion System and Method

Abstract

A nested Δ-Σ analog-to-digital conversion system and method, comprising: an analog filter, an analog comparator, and a first feedback digital-to-analog converter connected in sequence; a second feedback digital-to-analog converter disposed before the first feedback digital-to-analog converter; and a digital filter and an MSB quantizer disposed at the output end of the analog comparator. The input end of the first feedback digital-to-analog converter is connected to the output end of the analog comparator. The analog filter, the analog comparator, and the first feedback digital-to-analog converter form an internal analog Δ-Σ loop. The input end of the second feedback digital-to-analog converter is connected to the output end of the MSB quantizer. The output end of the second feedback digital-to-analog converter is connected to the output end of the first feedback digital-to-analog converter and the input end of the analog filter. The second feedback digital-to-analog converter, the internal analog Δ-Σ loop, the digital filter, and the MSB quantizer form an external hybrid Δ-Σ loop. By means of the nested external digital-to-analog external hybrid Δ-Σ loop, the present invention dynamically adjusts the signal swing of the internal analog Δ-Σ loop, thereby reducing the design difficulty of the internal analog Δ-Σ loop and significantly improving the energy efficiency and accuracy.

Description

Technical Field

[0001] The present invention relates to a technology in the field of signal processing, and more particularly to a nested Δ-Σ analog-to-digital conversion system and method. Background Art

[0002] Existing scaled Δ-Σ analog-to-digital conversion technology pre-quantifies an analog input signal through a coarse quantizer, so that the analog Δ-Σ loop only needs to process a small part of the analog signal, thereby reducing the design difficulty of the Δ-Σ loop. However, the scaled Δ-Σ analog-to-digital converter has problems of spurious leakage and coarse-fine quantization level mismatch, which limit the accuracy of the Δ-Σ analog-to-digital converter, that is: the signal transfer function of the fine quantization Δ-Σ analog-to-digital converter is not equal to 1, and the final output result is affected by this function and there is a leakage problem, and the spectrum of the output signal has spurs, which limits the accuracy of the analog-to-digital converter; the outputs of the coarse quantization and fine quantization analog-to-digital converters are both fed back to the input end of the analog-to-digital converter through a digital-to-analog converter, and the mismatch in the levels of the most significant bit (MSB) generated by the coarse quantization and the least significant bit (LSB) generated by the fine quantization will cause an increase in the internal signal swing of the fine quantization Δ-Σ analog-to-digital converter, deteriorating the performance of the analog-to-digital converter. Summary of the Invention

[0003] In view of the above deficiencies in the prior art, the present invention proposes a nested Δ-Σ analog-to-digital conversion system and method, which dynamically adjusts the signal swing of the internal analog Δ-Σ loop through a nested external digital-to-analog external hybrid Δ-Σ loop, thereby reducing the design difficulty of the internal analog Δ-Σ loop and significantly improving the energy efficiency and accuracy.

[0004] The present invention is achieved by the following technical solutions:

[0005] The present invention relates to a nested Δ-Σ analog-to-digital conversion system, including: an analog filter, an analog comparator and a first feedback digital-to-analog converter (DAC) connected in sequence, a second feedback digital-to-analog converter provided in front of the first feedback digital-to-analog converter, and a digital filter and an MSB quantizer provided at the output end of the analog comparator, wherein: the input end of the first feedback digital-to-analog converter is connected to the output end of the analog comparator, the analog filter, the analog comparator and the first feedback digital-to-analog converter form an internal analog Δ-Σ loop, the input end of the second feedback digital-to-analog converter is connected to the output end of the MSB quantizer, the output end of the second feedback digital-to-analog converter is connected to the output end of the first feedback digital-to-analog converter and the input end of the analog filter, and the second feedback digital-to-analog converter, the internal analog Δ-Σ loop, the digital filter and the MSB quantizer form an external hybrid Δ-Σ loop.

[0006] Technical Effects

[0007] The present invention significantly reduces the signal swing inside the analog Δ-Σ loop through a nested architecture, improving the energy efficiency of the analog-to-digital converter; there are no spurious leakage and level mismatch problems, and it features high precision; except for the analog Δ-Σ loop, other circuits are all digital circuits, with high digital circuit affinity and design flexibility. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 It is a schematic diagram of the system of the present invention;

[0009] Figure 2 It is a schematic diagram of the implementation method of low-latency MSB quantization;

[0010] Figure 3 It is a schematic diagram of the input-output transfer characteristic of a three-state comparator without hysteresis comparison;

[0011] Figure 4 is a schematic diagram of the MSB quantization method based on hysteresis comparison;

[0012] Figure 5 It is a schematic diagram of the spectrum comparison between a scaled and a nested Δ-Σ analog-to-digital converter;

[0013] Figure 6 It is a schematic diagram of the spectrum comparison with / without hysteresis comparison. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0014] As Figure 1 shown, this embodiment relates to a nested Δ-Σ analog-to-digital conversion system, including: an analog filter, an analog comparator, and a first feedback digital-to-analog converter connected in sequence, a second feedback digital-to-analog converter DAC-MSB arranged before the first feedback digital-to-analog converter DAC-LSB, and a digital filter and an MSB quantizer arranged at the output end of the analog comparator, where: the input end of the first feedback digital-to-analog converter is connected to the output end of the analog comparator, the analog filter, the analog comparator, and the first feedback digital-to-analog converter form an internal analog Δ-Σ loop, the input end of the second feedback digital-to-analog converter is connected to the output end of the MSB quantizer, and the analog quantity Y corresponding to the output signal Y of the external hybrid Δ-Σ loop output by the second feedback digital-to-analog converter A The difference from the input signal IN is further used as the input of the analog filter together with the difference output by the first feedback digital-to-analog converter, and the second feedback digital-to-analog converter, the internal analog Δ-Σ loop, the digital filter, and the MSB quantizer form an external hybrid Δ-Σ loop.

[0015] As Figure 2 shown, the digital filter includes: a first-in-first-out memory (FIFO) and a counter.

[0016] As Figure 2 shown, the MSB quantizer includes: a three-state digital comparator and an adder-subtractor-accumulator.

[0017] As shown Figure 3 in the figure, the operating states of the described three-state digital comparator include: when the input D of the three-state digital comparator is greater than the comparison threshold D H , the three-state digital comparator outputs +1; when the input D of the three-state digital comparator is less than the comparison threshold D L , the three-state digital comparator outputs -1; when the input D of the three-state digital comparator is between D L and D H , the three-state comparator does not produce an output result.

[0018] The described internal analog Δ-Σ loop quantifies the input difference IN - Y A and outputs the signal V = STF * (IN - Y A ), where STF is the signal transfer function of the internal analog Δ-Σ loop; due to the high-gain characteristic of the digital filter, the input end of the digital filter, that is, the output end of the internal analog Δ-Σ loop, is a virtual ground end, and the output signal V of the internal analog Δ-Σ loop only has signals in two states of '0' and '1'. When the output signal V deviates from the mean value of 1 / 2, the MSB quantizer will detect this deviation. Specifically: when the mean value of the output signal V is higher than D H / lower than D L , the MSB quantizer will increase / decrease Y A to reduce / increase (IN - Y A ) so as to force the mean value of V to return to 1 / 2; only when the mean value of the output signal V changes large enough and exceeds the range of (D L , D H ), it may cause a change in the output of the MSB quantizer, where: D H and D L are respectively the high and low thresholds of the three-state comparator of the MSB quantizer.

[0019] Therefore, the MSB quantizer only quantifies the MSB. In the entire nested Δ-Σ analog-to-digital converter, the internal analog Δ-Σ loop quantifies and feeds back the LSB, and the external hybrid Δ-Σ loop is responsible for quantifying and feeding back the MSB.

[0020] The output signal of the described external hybrid Δ-Σ loop where: IN is the input of the nested Δ-Σ analog-to-digital conversion system, that is, the input analog signal of the external hybrid Δ-Σ loop, V is the output signal of the internal analog Δ-Σ loop, LPF DIG is the transfer function of the digital filter, E Y is the quantization noise in the MSB quantization process, E QFor the quantization noise of the internal analog Δ-Σ loop, NTF is the noise transfer function of the internal analog Δ-Σ loop, and STF is the signal transfer function of the internal analog Δ-Σ loop.

[0021] The quantization noise E of the internal analog Δ-Σ loop described above Q , during the MSB quantization process, as a perturbation signal, it breaks the signal correlation characteristics caused by low precision in the MSB quantization process, thereby eliminating signal-related spurs and avoiding the problem that a large amount of spur leakage exists in the error of the coarse quantization stage in the existing scaled Δ-Σ analog-to-digital conversion technology.

[0022] The input signal of the MSB quantizer described above in one MSB quantization period is limited by the MSB decision range, specifically: D = ∑(STF × (IN - Y A ) + E Q ×NTF) ∈ (D L , D H ), where: ∑ represents the summation filtering process of the digital filter, and (D L , D H ) is the decision interval of the MSB quantizer.

[0023] Since the signal part outside the interval (D L , D H ) will be suppressed by the external hybrid Δ-Σ loop and will not appear in the internal analog Δ-Σ loop, the signal swing of the internal analog Δ-Σ loop depends on (D L , D H ) and is not affected by the mismatch problem.

[0024] As Figure 2 shown, this embodiment relates to a low-latency MSB quantization method based on the above analog-to-digital conversion system, including:

[0025] Step 1: The digital filter filters the output V of the analog Δ-Σ loop to obtain the output signal D. The FIFO in the digital filter stores the data of the most recent H periods of V, and the counter in the digital filter counts the H data in the FIFO, and the counting result D is the output result of the digital filter.

[0026] Step 2: The three-state comparator in the MSB quantizer compares D with the thresholds D L , D H , and the three-state comparator outputs +1 or -1 or does not output.

[0027] Step 3: The adder-subtractor-accumulator accumulates the output of the three-state comparator. When the three-state comparator outputs +1, the output of the adder-subtractor-accumulator increases by 1; when the three-state comparator outputs -1, the output of the adder-subtractor-accumulator decreases by 1; when the three-state comparator does not produce an output, the output of the adder-subtractor-accumulator remains unchanged.

[0028] The output of the adder-subtractor accumulator, that is, the quantization output result of the MSB quantizer. During the MSB quantization process, although the MSB quantizer can generate multi-bit data, each quantization only changes the +1 or -1 data accumulated by the accumulator compared with the previous quantization for the MSB. All information of the MSB does not need to be obtained in one MSB quantization. Only the information of the least significant bit in the MSB needs to be obtained in one MSB quantization. Therefore, it has the characteristic of low latency.

[0029] As Figure 3 shown, it is the input-output transfer characteristic of the three-state comparator without hysteresis, that is, at any time, the threshold of the MSB comparison in step 2 is always fixed at D L and D H , which makes it difficult for the analog-to-digital converter to achieve a compromise between accuracy and speed. When the analog-to-digital converter inputs a sine wave, D L needs to be relatively large, D H needs to be relatively small to ensure that the MSB quantizer can follow the change of the zero crossing of the sine wave; D L needs to be relatively small, D H needs to be relatively large to ensure that the MSB quantizer does not generate error codes when quantizing the peaks and valleys of the sine wave.

[0030] As Figures 4a - 4c shown, it is the threshold optimization method of the three-state comparator in the MSB quantizer in step 2 above, including:

[0031] Step a: Before MSB quantization, set the indication variable S to the polarity of the output result of the previous three-state comparator, as Figure 4a shown.

[0032] Step b: Dynamically update the high and low thresholds D H and D L of the three-state comparator according to the indication variable S, as Figures 4b - 4c shown. Specifically: preset the upper and lower limits of the range of the high and low thresholds (D H ), H , (D H ), L and (D L ), H , (D L ). When S is +1, set the high and low thresholds D L of the three-state comparator to (D H ) L and (D H ) L respectively, otherwise set to (D L ) L , H ) HWith (D L ) H .

[0033] Step c: Based on the updated high and low thresholds of the three - state comparator, perform the comparison of the three - state comparator during the MSB quantization process.

[0034] The MSB quantization method based on hysteresis comparison. The hysteresis comparison controls the selection of the MSB comparison threshold through the indication variable S. The hysteresis comparison can dynamically adjust the threshold in real - time, enabling the analog - to - digital converter to balance accuracy and speed. For example: when S is + 1, when 1) the signal processed by the analog - to - digital converter is rising continuously, that is, the mean value of V will increase continuously. Therefore, the comparison threshold during MSB quantization is D H , and the hysteresis comparison mechanism sets D H to (D H ) L , and the MSB quantizer can follow the rapid change of the input signal; when 2) the signal processed by the analog - to - digital converter is at the peak, the mean value of V tends to decrease. Therefore, the comparison threshold during MSB quantization is D L , and the hysteresis comparison mechanism sets D L to (D L ) L , and no error code is generated in the MSB quantization.

[0035] After specific actual experiments, chip testing and verification were carried out in the 180nm CMOS process. The clock frequency was 7.68MHz, and the input signal was a sine wave of - 0.6dBFs and 820Hz. Figure 4 compares the spectra of the scaled - down Δ - Σ analog - to - digital converter and the nested Δ - Σ analog - to - digital converter. Since the nested Δ - Σ analog - to - digital converter can avoid the problems of spurious leakage and level mismatch, the nested Δ - Σ analog - to - digital converter can achieve a higher signal - to - noise - and - distortion ratio (SNDR) and spurious - free dynamic range (SFDR). Figure 5 Comparing the spectra with and without the hysteresis comparison technology, the hysteresis comparison can avoid the error - code problem, so a higher SNDR and SFDR can be achieved.

[0036] Compared with the prior art, in this system, through the closed - loop feedback control of the external hybrid Δ - Σ loop, Y A tends to IN. Therefore, the amplitude of (IN - YA) is only a small part of the amplitude of IN. The design difficulty of the internal analog Δ - Σ loop can be greatly alleviated. Even with a low - power internal analog Δ - Σ loop, high performance can be achieved, featuring high energy efficiency. Secondly, there are no problems of spurious leakage and MSB, LSB level mismatch in the nested Δ - Σ analog - to - digital converter of the present invention. At the same time, except for the analog Δ - Σ loop, all modules are digital circuits, with high flexibility and affinity for digital circuits.

[0037] The above specific embodiments can be locally adjusted in different ways by those skilled in the art without departing from the principles and purposes of the present invention. The protection scope of the present invention is subject to the claims and is not limited by the above specific embodiments. All implementation solutions within its scope are subject to the present invention.

Claims

1. A nested Δ-Σ analog-to-digital conversion system, characterized in that Comprising: An analog filter, an analog comparator, a first feedback digital-to-analog converter connected in sequence, a second feedback digital-to-analog converter disposed before the first feedback digital-to-analog converter, and a digital filter and an MSB quantizer disposed at the output end of the analog comparator, wherein: the input end of the first feedback digital-to-analog converter is connected to the output end of the analog comparator, and the analog filter, the analog comparator, and the first feedback digital-to-analog converter form an internal analog Δ-Σ loop; the input end of the second feedback digital-to-analog converter is connected to the output end of the MSB quantizer, the output end of the second feedback digital-to-analog converter is connected to the output end of the first feedback digital-to-analog converter and the input end of the analog filter, and the second feedback digital-to-analog converter, the internal analog Δ-Σ loop, the digital filter, and the MSB quantizer form an external hybrid Δ-Σ loop; The MSB quantizer described above includes: a three-state digital comparator and an adder-subtractor-accumulator. When the input D of the three-state digital comparator is greater than the comparison threshold D H the three-state digital comparator outputs +1; when the input D of the three-state digital comparator is less than the comparison threshold D L the three-state digital comparator outputs -1; when the input D of the three-state digital comparator is between D L and D H the three-state comparator does not produce an output result; The internal analog Δ-Σ loop processes the input difference IN - Y A and outputs a quantized signal V = STF * (IN - Y A ), where: IN is the input of the nested Δ-Σ analog-to-digital conversion system, i.e., the input analog signal of the external hybrid Δ-Σ loop, and Y A is the output signal of the external hybrid Δ-Σ loop corresponding to the analog quantity output by the second feedback digital-to-analog converter . Due to the high-gain characteristic of the digital filter, the input end of the digital filter, i.e., the output end of the internal analog Δ-Σ loop, is a virtual ground terminal. The output signal V of the internal analog Δ-Σ loop has only two states of signals, '0' and '1'. When the output signal V deviates from the mean value of 1 / 2, the MSB quantizer will detect this deviation. Specifically: when the mean value of the output signal V is higher than D H / lower than D L , the MSB quantizer will increase / decrease Y A to decrease / increase (IN - Y A ) so as to force the mean value of V to return to 1 / 2. Only when the change in the mean value of the output signal V exceeds the range of (D L , D H ), it will cause a change in the output of the MSB quantizer, where: D H and D L are the high and low thresholds of the three-state comparator of the MSB quantizer respectively.

2. The nested Δ-Σ analog-to-digital conversion system according to claim 1, characterized in that The output signal of the external hybrid Δ-Σ loop , where: V is the output signal of the internal analog Δ-Σ loop, LPF DIG is the transfer function of the digital filter, E Y is the quantization noise in the MSB quantization process, E Q is the quantization noise of the internal analog Δ-Σ loop, NTF is the noise transfer function of the internal analog Δ-Σ loop, and STF is the signal transfer function of the internal analog Δ-Σ loop.

3. The nested Δ-Σ analog-to-digital conversion system according to claim 2, characterized in that, The quantization noise E of the internal analog Δ-Σ loop Q , during the MSB quantization process, acts as a perturbation signal to break the signal correlation characteristics caused by low precision in the MSB quantization process, thereby eliminating signal-related spurs and avoiding the problem that the errors in the coarse quantization stage of the existing scaled Δ-Σ analog-to-digital conversion technology contain a large amount of spur leakage.

4. A low-latency MSB quantization method based on any one of the analog-to-digital conversion systems described in claims 1-3, characterized in that, Comprising: Step 1: The digital filter filters the output V of the analog Δ-Σ loop to obtain an output signal D. The FIFO in the digital filter stores the data of V in the most recent H cycles, and the counter in the digital filter counts the H data in the FIFO. The counting result D is the output result of the digital filter; Step 2: The three-state comparator in the MSB quantizer compares D with the threshold values D L , D H , and outputs +1 or -1 or does not output; Step 3: The adder-subtractor accumulator accumulates the output of the three-state comparator. When the output of the three-state comparator is +1, the output of the adder-subtractor accumulator is incremented by 1; when the output of the three-state comparator is -1, the output of the adder-subtractor accumulator is decremented by 1; when the three-state comparator does not produce an output, the output of the adder-subtractor accumulator remains unchanged; In each quantization, compared with the previous quantization, only the data of +1 or -1 accumulated by the accumulator changes in the MSB. All the information of the MSB does not need to be obtained in one MSB quantization, and only the information of the least significant bit in the MSB needs to be obtained in one MSB quantization.

5. The low-latency MSB quantization method according to claim 4, characterized in that, For the described three-state comparator, its threshold is further optimized in the following manner, specifically: Step a: Before MSB quantization, set the indication variable S to the polarity of the output result of the previous three-state comparator; Step b: Dynamically update the high and low thresholds D of the three-state comparator according to the indication variable S H and D L , specifically: preset the upper and lower limits of the range of the high and low thresholds (D H ), H (D H ), L and (D L ), H (D L ), L . When S is +1, set the high and low thresholds D H and D L to (D H ) L and (D L ), L respectively; otherwise, set them to (D H ) H and (D L ). H ; Step c: Based on the updated high and low thresholds of the three-state comparator, perform the comparison of the three-state comparator during the MSB quantization process.

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