A flexible and scalable cellular digital beamforming network system

Abstract

This invention discloses a flexible and expandable cellular digital beamforming network system. This network system is composed of multiple identical node units arbitrarily spliced ​​together to form a cellular beamforming network, allowing for the addition and deletion of units at will. Through arbitrary combinations of units, this digital beamforming network possesses the characteristic of flexible expansion in the number of channels and beams. Furthermore, because it uses multiple units for combination, it can be built using a common hardware platform in different application scenarios. Simultaneously, the digital beamforming network employing this scheme also features high reliability and high redundancy efficiency, making it suitable for rapid deployment and application of digital phased arrays.

Description

Technical Field

[0001] This invention relates to a flexible and expandable cellular digital beamforming network system. The method is mainly used for the design and development of digital beamforming equipment and can be applied to electronic information fields such as communication, radar, or measurement and control. Background Technology

[0002] Digital beamforming (DBF) offers advantages such as a large number of beams, flexible beam pointing and gain, and fine-grained beam tracking, making it an inevitable trend for future high-capacity communication systems. As DBF technology matures in-orbit applications, a series of related derivative technologies and problems urgently need to be addressed. With increasing communication capacity demands, the processing bandwidth and number of beams in digital beamforming systems are constantly increasing. Besides the increased processing resources brought about by changes in broadband digital beamforming architecture, the more significant issue is the geometrical increase in hardware size due to the increased processing bandwidth and number of beams, leading to a substantial increase in the weight, power consumption, and cost of the hardware processing platform. While using more advanced components can alleviate some of these problems, traditional DBF implementation architectures have fundamental flaws. Therefore, it is necessary to research a more optimized DBF implementation architecture.

[0003] Traditional digital beamforming networks employ a single-stage, multi-node crossover network structure, with the following topology: Figure 1 As shown.

[0004] To implement an M×N scale digital beamforming network, the number of network connections would be M×N. This connection structure increases geometrically with the number of beams or channels. Furthermore, the network composition is fixed by the hardware design, making flexible hardware expansion difficult. Once the application scenario is determined, the structure of the digital beamforming network is fixed, making it impossible to quickly assemble devices for different application scenarios using a general-purpose hardware platform.

[0005] Currently, research in the field of digital beamforming mainly focuses on implementing certain algorithms using beamforming networks, with virtually no research on beamforming network architectures. A search of relevant domestic and international literature using keywords such as "beamforming network," "architecture," and "flexible expansion" in relevant databases yielded the following results: Reference 1 (Sikri Divaydeep, "Scalable Multi Beamforming Topology Supporting An Electronically SteeredArray Antenna," 2021) proposes a chain-topology DBF structure. This structure supports the cascading of multiple branch DBFs, connecting the beams to external ports via the chain structure. The DBF branches are directly connected to the RF terminals, and the chain cascading is accomplished using Satixfy's proprietary Prime chip. This chip supports 32 beam processing capabilities, a beam bandwidth of 1 GHz, and meets broadband beamforming requirements. Reference 2 (Zan Zhiming, Du Yuming, Yu Zhiqiang, et al., “Design of 28-Channel Transceiver Processing Module”, Journal of Chengdu University of Information Technology, 2022, No. 3) introduces a hardware structure for array signal transceiver processing based on FPGA and multi-channel AD / DA converters. This design uses the integrated AD9371 chip and performs direct RF sampling through a built-in mixer and DDS technology. Its advantages include reduced RF channel size and improved system integration.

[0006] The advantage of Reference 1 mentioned above is that the deployment of the digital beamforming network only requires the integration of DBF branches, chain-connected chips, and external structures. It offers flexible channel expansion capabilities, making it suitable for rapid product deployment and delivery. The disadvantages are that the chain structure is not suitable for satellite applications, has lower reliability, and if any node in the chain structure fails, it can lead to uncontrollable performance loss or damage to the entire beamforming network.

[0007] The design used in Reference 2 can meet the needs of low-speed multi-channel processing and can serve as a digital-to-analog converter and beam processing module for a flexibly expandable cellular digital beamforming node unit. However, it cannot meet the processing requirements of high-speed services, necessitating the use of other AD and DA devices with higher sampling rates. Summary of the Invention

[0008] The purpose of this invention is to overcome the shortcomings of the prior art and propose a flexible and expandable cellular digital beamforming network system that can effectively eliminate the inherent defects of traditional beamforming networks.

[0009] The technical solution adopted in this invention is as follows:

[0010] A flexible and expandable cellular digital beamforming network system, the network system adopting a cellular structure, including: beamlines, beam ports, center node units, and edge node units;

[0011] Each central node unit is connected to 3 beamlines, and each edge node unit is connected to at least 1 beamline and 1 beamport; wherein the beamport can be converted into a beam connection by connecting to the edge node unit externally, and the edge node unit can be converted into a central node unit by connecting to the beamline externally.

[0012] Each central node unit and edge node unit corresponds to a fixed number of phased array channels. The number of channels can be expanded by increasing the number of node units; the number of beams can be expanded by connecting different beam ports.

[0013] Furthermore, the edge node units and the center node units have the same structure and are both node units. They are distinguished by their position in the beamforming network. If a node unit is connected to three beams, then it is a center node unit; otherwise, it is an edge node unit.

[0014] Furthermore, each node unit includes a clock synchronization module, a digital-to-analog converter module, a beam processing module, and a digital interface module;

[0015] The clock synchronization module synchronizes the input clock and synchronization signal, and provides the working clock and synchronization signal to other modules;

[0016] One RF reference clock signal is input from an external clock synchronization module. The clock synchronization module has one pair of LVPECL level clock signals and one pair of LVDS level synchronization signals with each of the digital-to-analog converter module, beam processing module, and digital interface module. It also has three pairs of LVPECL level clock signals and three pairs of LVDS level synchronization signals as inputs and three pairs of LVPECL level clock signals and three pairs of LVDS level synchronization signals as outputs with the clock synchronization modules of other node units. There is one set of configuration signals between the clock synchronization module and the digital interface module.

[0017] The digital-to-analog conversion module uses RF direct-sampling digital devices for digital-to-analog conversion;

[0018] There are several pairs of GTH interfaces between the digital-to-analog converter module and the beam processing module for transmitting the signals after digital-to-analog conversion. The specific number depends on the number of lanes in the digital-to-analog converter and the number of GTH pins in the FPGA of the beam processing module. There are multiple RF channel interfaces between the digital-to-analog converter module and the phased array channel.

[0019] The beam processing module is used for digital beamforming; there are several pairs of GTH interfaces between the beam processing module and the digital interface module for transmitting beam signals.

[0020] The digital interface module is used to enable data exchange of beam signals between node units and to enable data exchange of beam signals with external processing units.

[0021] The number of configuration signals between the digital interface module and the clock synchronization module depends on the selection and number of clock chips in the clock synchronization module. Furthermore, the clock synchronization module includes two sets of input selections corresponding to clock input selection and synchronization signal input selection, respectively, as well as a three-level clock chip.

[0022] In the master node unit, the first-level clock chip is configured in zero-latency mode for external feedback, the second-level clock chip is configured in zero-latency mode for internal feedback, and the third level is a clock chip buff.

[0023] In the slave node unit, the first-level clock chip is configured in zero-latency mode for external feedback, the second-level clock chip is configured in PLL frequency multiplication mode, and the third level is a clock chip buff.

[0024] The clock input selection selects the clock from other node units or the RF reference input, based on the configuration signal sent by the digital interface module. After selection, the clock is sent to the first-stage clock chip. The synchronization input selection selects the synchronization signal from other node units, based on the configuration signal sent by the digital interface module. After selection, the synchronization signal is sent to the second-stage clock chip.

[0025] Each clock synchronization module is connected to up to three clock synchronization modules, and the clock input path is selected by configuring the connection method of ID mapping.

[0026] 5. A flexible and expandable cellular digital beamforming network system according to claim 3, characterized in that: the digital-to-analog conversion module includes an ADC and a DAC;

[0027] The sysref frequency of ADC and DAC is related to the synchronization signal by a power of 2.

[0028] The sampling rate of ADC and DAC is related to the synchronization signal by a power of 2.

[0029] The digital-to-analog conversion module and the beam processing module communicate via a high-speed GTH / GTY / GTZ interface, using the JESD204B / C interface and the JESD204B / C subclass 1 synchronous interface protocol.

[0030] Furthermore, the beam processing module is implemented using an FPGA and includes: a digital up / down conversion module, a first-level digital beamforming module, a second-level digital beamforming module, a beam data buffer and read module, and a digital-to-analog conversion interface module;

[0031] The digital-to-analog conversion interface module completes data transmission between the digital up / down conversion module and the ADC and DAC, and configures the parameters of the ADC and DAC;

[0032] The digital up-conversion module completes the digital down-conversion of the received link signal and the digital up-conversion of the transmitted link signal, and interacts with the first-level digital beamforming and digital-to-analog conversion module for channel signal data exchange.

[0033] The first-level beam digital beamforming module contains an m×N digital beamforming network, which completes the processing of m channels and N beam digital beams. The receiving link combines the m channels after digital downconversion into N beams and sends them to the beam data buffer and read module. The transmitting link combines the N beams from the beam data buffer and read module into m channels and sends them to the digital upconversion and downconversion module.

[0034] The beam buffer and read module includes a storage control module and a data buffer; the storage control module writes the beam signal data into the data buffer, and aligns the beam signals of each node unit in time according to the ID of the node unit and sends them to the next level;

[0035] The secondary beamforming module includes an accumulation module and a copying module, which are used for accumulation processing in the receive processing link and copying processing in the transmit processing link, respectively. The accumulation processing sums the received beam signal of the current node unit with the received beam signal of the previous node unit and sends it to the next node unit. The copying processing divides the transmit beam signal of the previous node unit into two paths. The first path is sent to the beam buffer and readout module, and the second path is sent to the next node unit.

[0036] Furthermore, beamforming for each beam is divided into multiple parts, with first-level digital beamforming followed by cascaded second-level beamforming.

[0037] For transmitting digital beamforming network beam signals, a copy is made at each node and transmitted to the next cascaded node, where it is stored and processed. For receiving digital beamforming network beams, the beam signal is summed with the beam signal of the current node as it passes through each node and then sent to the next cascaded node.

[0038] Furthermore, each node unit needs to store the beam signal, and the storage depth is related to the position of the node unit in the beamforming network;

[0039] The amount of data stored in each node unit is:

[0040] Data=m×N×Nob×FrameNum×(K-k+1)

[0041] in,

[0042] m represents the number of channels in a single node unit;

[0043] N represents the number of beams;

[0044] K represents the number of node units;

[0045] k represents the current node cell number;

[0046] Nob indicates the signal bit width;

[0047] FrameNum represents the number of data frames transmitted between node units, and this number is determined by the interface protocol between node units.

[0048] The calculation method for FrameNum is as follows:

[0049]

[0050] C represents the period multiple between the interface data transmission frame and the synchronization signal;

[0051] fsync represents the frequency of the synchronization signal;

[0052] fsys represents the internal clock frequency.

[0053] Furthermore, the signals transmitted by the digital interface module include: clock signals, synchronization signals, beam signals, and control signals;

[0054] The clock and synchronization signals of the digital interface module are transmitted using differential digital signals; the beam and control signals are transmitted using either electrical or optical signals. When using electrical signals, the FPGA's built-in GTH / GTY / GTZ interface is used for transmission; when using optical signals, a photoelectric conversion module and optical fiber are used for data transmission between node units.

[0055] The transmission delay from the transmitter to the receiver is fixed and does not exceed the time of one synchronization signal cycle.

[0056] Furthermore, the node units are controlled in a cascaded manner, with all node units connected to the control bus and controlled uniformly by an external interface. After the beamforming network is initially assembled, each node unit is configured with an ID and stored in the configuration memory for subsequent direct use. When configuring the ID, each cascaded node unit is configured with its ID in order of proximity to the external interface from closest to furthest.

[0057] The advantages of this invention compared to the prior art are:

[0058] (1) This invention proposes a flexibly scalable cellular digital beamforming network design method, which can effectively eliminate the inherent defects of traditional beamforming networks. The network consists of multiple identical digital beamforming units, and because multiple units are combined, it can be built using a common hardware platform in different application scenarios. Furthermore, the digital beamforming network using this scheme also features high reliability and high redundancy efficiency, making it suitable for rapid deployment and application of digital phased arrays.

[0059] (2) In the network system of this invention, the node unit is the basic unit that makes up the digital beamforming network. Each node unit has three sets of external connections, and the node units form the beamforming network through their connections with each other. Based on the position of the node unit in the beamforming network, edge node units and center node units are defined. The two can be converted into each other by adding or deleting node units externally.

[0060] (3) The network system of this invention is formed by arbitrarily splicing multiple identical node units to create a cellular beamforming network, and units can be added or deleted arbitrarily. Through arbitrary combinations of units, the digital beamforming network has the characteristic of flexible expansion of the number of channels and beams. The digital beamforming network using this scheme also has the characteristics of high reliability and high redundancy efficiency, and is suitable for rapid deployment and application of digital phased arrays.

[0061] (4) Current research on digital beamforming technology is mostly focused on narrowband applications, primarily in radar applications, where real-time signal processing requirements are not high. Research in communication applications is still in its early stages, with clearly defined broadband and narrowband application scenarios and needs. The solution proposed in this invention can provide theoretical reference and practical guidance for research in related fields in China. Attached Figure Description

[0062] Figure 1 Schematic diagram of the topology of a traditional beamforming network;

[0063] Figure 2 Schematic diagram of the topology of a cellular beamforming network;

[0064] Figure 3 Schematic diagram of node unit connection and transformation;

[0065] Figure 4 Block diagram of node unit composition;

[0066] Figure 5 Clock synchronization module processing block diagram;

[0067] Figure 6 Clock signal processing timing diagram;

[0068] Figure 7 Synchronization signal processing timing diagram;

[0069] Figure 8 Beam processing module block diagram;

[0070] Figure 9 Beam signal processing data flow diagram;

[0071] Figure 10 Beamforming network configuration flowchart. Detailed Implementation

[0072] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0073] Currently, satellite internet constellations use digital beamforming to implement onboard payloads. Because the satellites use traditional digital beamforming networks, the number and layout of phased arrays are designed entirely according to the low-Earth orbit (LEO) coverage requirements. For high-Earth orbit (HEO), inclined orbit (TEO), or other digital beamforming phased array applications, the phased arrays need to be redesigned. Similarly, the supporting data processing equipment also needs to be redeveloped, which significantly increases the manpower, material resources, and financial resources consumed by the mission and makes it difficult to meet the requirements of rapid future development for rapid design, rapid commissioning, and rapid delivery of satellite payloads.

[0074] like Figure 2 As shown, the present invention proposes a flexible and expandable cellular digital beamforming network system. This network structure differs from the mesh structure of traditional beamforming networks and adopts a cellular structure, including: beamlines, beam ports, central node units, and edge node units.

[0075] Each central node unit is connected to three beamlines, and each edge node unit is connected to at least one beamline and one beamport; wherein the beamport can be converted into a beam connection by connecting to an edge node unit externally, and the edge node unit can be converted into a central node unit by connecting to an external beamline, such as... Figure 3 As shown;

[0076] Each central node unit and edge node unit corresponds to a fixed number of phased array channels. The number of channels can be expanded by increasing the number of node units; the number of beams can be expanded by connecting different beam ports.

[0077] Edge node units and center node units are essentially both node units. The only difference is their location in the beamforming network. If a node unit is connected to three beams, it is a center node unit; otherwise, it is an edge node unit.

[0078] The technical innovations of this invention are as follows:

[0079] 1) A flexible and scalable cellular digital beamforming network architecture is proposed, along with the basic units that make up the beamforming network;

[0080] 2) It proposes key design elements and design methods for each module in the basic unit;

[0081] 3) A process and method for constructing cellular beamforming networks are proposed, including flexible scaling up and down.

[0082] Once the solution of this invention is adopted as a fixed-type product and a production line is established, it can significantly increase the production capacity and profits of all digital beamforming products. Furthermore, this technology can also be utilized on ground-based equipment.

[0083] The following is a detailed description of the cellular digital beamforming network system.

[0084] (1) Node unit composition

[0085] Each node unit consists of a clock synchronization module, a digital-to-analog converter (DAC) module, a beamforming module, and a digital interface module. The clock synchronization module synchronizes the input clock and synchronization signals within the node unit; the DAC module uses RF direct-sampling digital devices for DAC conversion; the beamforming module is the core processing module responsible for digital beamforming; and the digital interface module is responsible for data exchange between node units and between beamforming signals and external processing units. The node unit's composition is as follows: Figure 4 As shown.

[0086] One RF reference clock signal is input from an external clock synchronization module. The clock synchronization module has one pair of LVPECL level clock signals and one pair of LVDS level synchronization signals between itself and the digital-to-analog converter module, beam processing module, and digital interface module. It also has three pairs of LVPECL level clock signals and three pairs of LVDS level synchronization signals as inputs and three pairs of LVPECL level clock signals and three pairs of LVDS level synchronization signals as outputs between itself and the clock synchronization modules of other node units. There is one set of configuration signals between the clock synchronization module and the digital interface module.

[0087] There are several pairs of GTH interfaces between the digital-to-analog converter module and the beam processing module for transmitting the signals after digital-to-analog conversion. The specific number depends on the number of lanes in the digital-to-analog converter and the number of GTH pins in the FPGA of the beam processing module. There are multiple RF channel interfaces between the digital-to-analog converter module and the phased array channel.

[0088] There are several pairs of GTH interfaces between the beam processing module and the digital interface module for transmitting beam signals;

[0089] The number of configuration signals between the digital interface module and the clock synchronization module depends on the selection and number of clock chips in the clock synchronization module.

[0090] (2) Clock synchronization module

[0091] The deployment of the clock synchronization module also conforms to the topology of the flexibly expandable cellular digital beamforming network structure, on the one hand to match the connection relationship between each module, and on the other hand to improve the reliability of the entire digital beamforming network.

[0092] The clock synchronization module receives clock signals from external / other node units to generate the clock and synchronization source for the entire digital beamforming network. Its specific components are as follows: Figure 5 As shown. The clock synchronization module includes two sets of input selections corresponding to clock input selection and synchronization signal input selection, as well as a three-level clock chip.

[0093] To maximize the processing power of the digital beamforming network, the clock chip should be a model that supports the JESD204 subclass 1 synchronization protocol, such as TI's LMK04828 or LMK04832.

[0094] The clock input selection and synchronization input selection use a multi-port input clock buffer. The input can be expanded to 4 channels by cascading 2 CSCLK954s, and the maximum number of output channels is 10, which is sufficient for subsequent devices.

[0095] Taking the LMK04832 clock chip as an example, due to the limited number of ports on this type of device, an additional level of clock synchronization expansion is needed to synchronize more devices. Each clock chip can support 10 clock channels or 5 clock synchronization signals. The first-level clock chip of the master node unit is configured in zero-delay mode (ZDM) for external feedback. The external feedback uses one of the clock channels, so the clock chip can only use 9 clock channels. After looping 3 of these channels out of the node unit, the remaining 6 channels can be expanded to support 30 clock synchronization signals.

[0096] The clock frequency of the loop-out node unit is consistent with the input frequency. Furthermore, the hardware design requires that the feedback path length be greater than the clock path length from the first-stage clock chip to the loop-out node unit. This ensures that, after adjustment, the clock phase of the loop-out node unit slightly leads the input clock phase, ultimately resulting in complete consistency of the input clock phases for all node units after passing through the interconnecting lines. Specific timing relationships are as follows: Figure 6 As shown.

[0097] The second-stage clock chips of the master node unit and the slave node unit have different configurations. Since the second-stage clock chip of the master node unit has no synchronization signal input, it is configured as the internal feedback ZDM. One of its outputs is selected as the synchronization signal for the entire system, while the remaining outputs can be used as clock and synchronization signals for other internal modules.

[0098] The second-level clock chip of the slave node unit is configured in PLL frequency multiplication mode, and a synchronization signal is used as the sysref for clock chip synchronization. The phase timing relationship of the input and output synchronization signals of the slave node unit is similar to that of the loop-out clock input and output phase relationship. It is necessary to ensure that the phase of the input synchronization signals of each node unit is completely consistent after hardware debugging. The implementation process is as follows: after the synchronization signal input is selected, the clock chip generates the clock and synchronization signals and sends them to the internal processing logic. The internal processing logic delays the synchronization signal and sends it to the clock chip buffer, and finally sends it to the slave node unit. The specific timing relationship is as follows: Figure 7 As shown.

[0099] The synchronization signal frequency can be calculated comprehensively based on the actual signal processing bandwidth, number of channels, number of beams, and carrier intermediate frequency. The formula for calculating the synchronization period signal frequency is as follows:

[0100]

[0101] fsync indicates the synchronization signal frequency.

[0102] fsys represents the internal clock frequency (the main processing logic's operating clock frequency).

[0103] bw indicates beamwidth

[0104] M represents the number of channels.

[0105] N represents the number of beams.

[0106] [·,·] indicates taking the least common multiple.

[0107] ceil(·) represents rounding up.

[0108] (3) Digital-to-analog conversion module

[0109] The digital-to-analog converter module includes an ADC, a DAC, and related circuitry. The ADC and DAC models can be selected based on specific requirements, and the total data processing capacity of the entire module is essentially fixed. Multi-channel ADCs and DACs can be used in narrowband applications, while single-channel ADCs and DACs can be used in broadband applications.

[0110] At the same time, the following factors need to be considered when selecting components:

[0111] 1) The ADC and DAC need to support the JESD204B / C subclass 1 synchronous interface protocol.

[0112] 2) The sysref frequency of the ADC and DAC is a power of 2 with respect to the synchronization signal.

[0113] 3) The sampling rate needs to be a power of 2 with respect to the synchronization signal.

[0114] 4) The digital-to-analog conversion module and the beam processing module communicate with each other using a high-speed GTH / GTY / GTZ interface, and adopt the JESD204B / C interface and subclass 1 synchronous interface protocol.

[0115] (4) Beam processing module

[0116] The beam processing module is the core processing module of the entire digital beamforming network, and its characteristics are:

[0117] 1) It has synchronization requirements;

[0118] 2) Matrix multiplication is required;

[0119] 3) High data port throughput.

[0120] Furthermore, real-time communication requires rapid processing, therefore only a design scheme using an FPGA as the primary processing unit is feasible. The beam processing module mainly consists of an FPGA and external memory (data buffer, configuration memory), with the following structure: Figure 8 As shown.

[0121] The main functions processed internally by the FPGA include: digital up / down conversion, first-stage digital beamforming, second-stage digital beamforming, beam data buffering and retrieval, and digital-to-analog conversion interface. In a flexible and expandable cellular digital beamforming network, beamforming for each beam is divided into multiple parts, with first-stage digital beamforming followed by cascaded second-stage beamforming. The cascaded beamforming network structure is as follows: Figure 9 As shown.

[0122] The first-level beam digital beamforming module contains an m×N digital beamforming network, which completes the processing of m channels and N beam digital beams. The receiving link combines the m channels after digital downconversion into N beams and sends them to the beam data buffer and read module. The transmitting link combines the N beams from the beam data buffer and read module into m channels and sends them to the digital upconversion and downconversion module.

[0123] The beam buffer and read module includes a storage control module and a data buffer; the storage control module writes the beam signal data into the data buffer, and aligns the beam signals of each node unit in time according to the ID of the node unit and sends them to the next level.

[0124] The secondary beamforming module includes an accumulation module and a copying module, which are used for accumulation processing in the receive processing link and copying processing in the transmit processing link, respectively. The accumulation processing sums the received beam signal of the current node unit with the received beam signal of the previous node unit and sends it to the next node unit. The copying processing divides the transmit beam signal of the previous node unit into two paths. The first path is sent to the beam buffer and readout module, and the second path is sent to the next node unit.

[0125] For transmitting digital beamforming network (DBN) signals, a copy is made at each node and transmitted to the next cascaded node for storage and processing. For receiving digital beamforming network (DBN) signals, the beam signal is summed with the current node's beam signal at each node and sent to the next cascaded node. This cascaded structure is characterized by different time delays between each node and the beam signal, while the channel ends require synchronization between the various channels of each beam. Therefore, each node needs to store the beam signal, and the storage depth depends on its position within the beamforming network.

[0126] The amount of data stored in each node unit is:

[0127] Data=m×N×Nob×FrameNum×(K-k+1)

[0128] m represents the number of channels in a single node unit.

[0129] N represents the number of beams.

[0130] K represents the number of node units.

[0131] k represents the current node cell number.

[0132] Nob indicates the signal bit width.

[0133] FrameNum represents the number of data frames transmitted between node units, which is determined by the interface protocol between node units. Generally, since data transmission between node units uses GTH / GTY / GTZ interfaces and needs to meet the deterministic delay of interface data transmission, the duration of each data frame is related to the period of the synchronization signal.

[0134] The calculation method for FrameNum is as follows:

[0135]

[0136] C represents the period multiple between the interface data transmission frame and the synchronization signal. The value varies depending on the protocol, but C = 2 is generally acceptable.

[0137] fsync represents the frequency of the synchronization signal;

[0138] fsys represents the internal clock frequency.

[0139] As can be seen from the data storage formula of the node unit above, the closer the node unit is to the beam signal port, the more data it can store. The data buffer can use high-capacity, high-speed memory, such as DDR3 or DDR4.

[0140] The slave node unit also needs to process the synchronization signal and output a synchronization reference. This processing involves delaying the input synchronization signal; the delay time is related to the synchronization signal period.

[0141] (5) Digital interface module

[0142] The signals transmitted by the digital interface module include: 1) clock signal; 2) synchronization signal; 3) beam signal; and 4) control signal.

[0143] The clock and synchronization signals of the digital interface module should be transmitted using high-performance differential digital signals. Beam and control signals can be transmitted using either electrical or optical signals. When using electrical signals, the FPGA's built-in GTH / GTY / GTZ interface can be used. If optical signals are used, a photoelectric conversion module and optical fiber are required for data transmission between node units. It is crucial that, regardless of whether electrical or optical signals are used, the transmission delay from the transmitter to the receiver must be fixed and cannot exceed one synchronization signal cycle. This needs to be determined based on specific application requirements.

[0144] (6) Beamforming network configuration method

[0145] The basic unit of a flexibly expandable cellular digital beamforming network is the node unit. Multiple node units are spliced ​​together via interfaces to form the beamforming network. Among all the node units constituting the network, a master node unit needs to be designated. The master node unit can be either an edge node unit or a center node unit. The designation method is determined by connecting external connectors to the corresponding interfaces. All other node units not connected to external connectors are slave node units. When assembling into the beamforming network, each node unit needs to be configured with an identification ID. This identification ID corresponds one-to-one with the node unit number k, thus distinguishing and controlling all units.

[0146] The control of the node units also adopts a cascaded approach. All node units are connected to the control bus and controlled uniformly by an external interface. After the beamforming network is initially assembled, each node unit can be configured with an ID, which is then stored in the configuration memory for subsequent use. During ID configuration, each cascaded node unit is configured with its ID sequentially according to its distance from the external interface, from closest to furthest. The configuration process is as follows: Figure 10 As shown.

[0147] In summary, this invention provides a flexible and expandable cellular digital beamforming network system. This network is composed of multiple identical digital processing units arbitrarily spliced ​​together to form a cellular beamforming network, allowing for the addition and deletion of units at will. Through arbitrary combinations of units, this digital beamforming network possesses the characteristic of flexible expansion in the number of channels and beams. Furthermore, because it uses multiple units for combination, it can be built using a common hardware platform in different application scenarios. Simultaneously, the digital beamforming network employing this scheme also features high reliability and high redundancy efficiency, making it suitable for rapid deployment and application of digital phased arrays.

[0148] The parts of this invention that are not described in detail are common knowledge to those skilled in the art.

Claims

1. A flexible and expandable cellular digital beamforming network system, characterized in that, The network system adopts a cellular structure, including: beamlines, beam ports, central node units, and edge node units; Each central node unit is connected to 3 beamlines, and each edge node unit is connected to at least 1 beamline and 1 beamport; wherein the beamport can be converted into a beam connection by connecting to the edge node unit externally, and the edge node unit can be converted into a central node unit by connecting to the beamline externally. Each central node unit and edge node unit corresponds to a fixed number of phased array channels. The number of channels can be expanded by increasing the number of node units; the number of beams can be expanded by connecting different beam ports. Each node unit includes a clock synchronization module, a digital-to-analog converter module, a beam processing module, and a digital interface module; The beam processing module is implemented using FPGA and includes: a first-level digital beamforming module, a second-level digital beamforming module, and a beam data buffering and reading module; The first-level beam digital beamforming module contains an m×N digital beamforming network, which completes the processing of m channels and N beam digital beams. The receiving link combines the m channels after digital downconversion into N beams and sends them to the beam data buffer and read module. The transmitting link combines the N beams from the beam data buffer and read module into m channels and sends them to the digital upconversion and downconversion module. The beam buffer and read module includes a storage control module and a data buffer; the storage control module writes the beam signal data into the data buffer, and aligns the beam signals of each node unit in time according to the ID of the node unit and sends them to the next level; The secondary beamforming module includes an accumulation module and a copying module, which are used for accumulation processing in the receiving processing link and copying processing in the transmitting processing link, respectively. The accumulation processing sums the received beam signal of the current node unit with the received beam signal of the previous node unit and sends it to the next node unit. The copying processing divides the transmitted beam signal of the previous node unit into two paths. The first path is sent to the beam buffer and readout module, and the second path is sent to the next node unit. Each node needs to store the beam signal, and the storage depth is related to the position of the node in the beamforming network. The amount of data stored in each node unit is: Data=m×N×Nob×FrameNum×(K-k+1) in, m represents the number of channels in a single node unit; N represents the number of beams; K represents the number of node units; k represents the current node cell number; Nob indicates the signal bit width; FrameNum represents the number of data frames transmitted between node units, and this number is determined by the interface protocol between node units. The calculation method for FrameNum is as follows: C represents the period multiple between the interface data transmission frame and the synchronization signal; fsync represents the frequency of the synchronization signal; fsys represents the internal clock frequency.

2. The flexibly expandable cellular digital beamforming network system according to claim 1, characterized in that: Edge node units and center node units have the same structure and are both node units. They are distinguished by their position in the beamforming network. If a node unit is connected to three beams, it is a center node unit; otherwise, it is an edge node unit.

3. The flexibly expandable cellular digital beamforming network system according to claim 2, characterized in that: The clock synchronization module synchronizes the input clock and synchronization signal, and provides the working clock and synchronization signal to other modules; One RF reference clock signal is input from an external clock synchronization module. The clock synchronization module has one pair of LVPECL level clock signals and one pair of LVDS level synchronization signals with each of the digital-to-analog converter module, beam processing module, and digital interface module. It also has three pairs of LVPECL level clock signals and three pairs of LVDS level synchronization signals as inputs and three pairs of LVPECL level clock signals and three pairs of LVDS level synchronization signals as outputs with the clock synchronization modules of other node units. There is one set of configuration signals between the clock synchronization module and the digital interface module. The digital-to-analog conversion module uses RF direct-sampling digital devices for digital-to-analog conversion; There are several pairs of GTH interfaces between the digital-to-analog converter module and the beam processing module for transmitting the signals after digital-to-analog conversion. The specific number depends on the number of lanes in the digital-to-analog converter and the number of GTH pins in the FPGA of the beam processing module. There are multiple RF channel interfaces between the digital-to-analog converter module and the phased array channel. The beam processing module is used for digital beamforming; there are several pairs of GTH interfaces between the beam processing module and the digital interface module for transmitting beam signals. The digital interface module is used to enable data exchange of beam signals between node units and to enable data exchange of beam signals with external processing units. The number of configuration signals between the digital interface module and the clock synchronization module depends on the selection and number of clock chips in the clock synchronization module.

4. The flexibly expandable cellular digital beamforming network system according to claim 3, characterized in that: The clock synchronization module includes two sets of input selections corresponding to clock input selection and synchronization signal input selection, respectively, as well as a three-level clock chip; In the master node unit, the first-level clock chip is configured in zero-latency mode for external feedback, the second-level clock chip is configured in zero-latency mode for internal feedback, and the third level is a clock chip buff. In the slave node unit, the first-level clock chip is configured in zero-latency mode for external feedback, the second-level clock chip is configured in PLL frequency multiplication mode, and the third level is a clock chip buff. The clock input selection selects the clock from other node units or the RF reference input, based on the configuration signal sent by the digital interface module. After selection, the clock is sent to the first-stage clock chip. The synchronization input selection selects the synchronization signal from other node units, based on the configuration signal sent by the digital interface module. After selection, the synchronization signal is sent to the second-stage clock chip. Each clock synchronization module is connected to up to three clock synchronization modules, and the clock input path is selected by configuring the connection method of ID mapping.

5. The flexibly expandable cellular digital beamforming network system according to claim 3, characterized in that: The digital-to-analog conversion module includes an ADC and a DAC; The sysref frequency of ADC and DAC is related to the synchronization signal by a power of 2. The sampling rate of ADC and DAC is related to the synchronization signal by a power of 2. The digital-to-analog conversion module and the beam processing module communicate via a high-speed GTH / GTY / GTZ interface, using the JESD204B / C interface and the JESD204B / C subclass 1 synchronous interface protocol.

6. The flexibly expandable cellular digital beamforming network system according to claim 5, characterized in that: The beam processing module also includes: a digital up / down conversion module and a digital-to-analog conversion interface module; The digital-to-analog conversion interface module completes data transmission between the digital up / down conversion module and the ADC and DAC, and configures the parameters of the ADC and DAC; The digital upconversion and downconversion module completes the digital downconversion of the received link signal and the digital upconversion of the transmitted link signal, and interacts with the first-level digital beamforming and digital-to-analog conversion module for channel signal data exchange.

7. A flexible and expandable cellular digital beamforming network system according to claim 6, characterized in that: The beamforming of each beam is divided into multiple parts, with first-level digital beamforming followed by cascaded second-level beamforming. For transmitting digital beamforming network beam signals, a copy is made at each node and transmitted to the next cascaded node, where it is stored and processed. For receiving digital beamforming network beams, the beam signal is summed with the beam signal of the current node as it passes through each node and then sent to the next cascaded node.

8. The flexibly expandable cellular digital beamforming network system according to claim 3, characterized in that: The digital interface module transmits signals including: clock signals, synchronization signals, beam signals, and control signals. The clock and synchronization signals of the digital interface module are transmitted using differential digital signals; the beam and control signals are transmitted using either electrical or optical signals. When using electrical signals, the FPGA's built-in GTH / GTY / GTZ interface is used for transmission; when using optical signals, a photoelectric conversion module and optical fiber are used for data transmission between node units. The transmission delay from the transmitter to the receiver is fixed and does not exceed the time of one synchronization signal cycle.

9. A flexible and expandable cellular digital beamforming network system according to claim 2, characterized in that: The node units are controlled in a cascaded manner, with all node units connected to the control bus and controlled uniformly by an external interface. After the beamforming network is initially assembled, each node unit is configured with an ID and stored in the configuration memory for later direct use. When configuring the ID, each cascaded node unit is configured with an ID in order of proximity to the external interface from closest to furthest.

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