A binary-based data stream converter

Abstract

The application relates to the technical field of data conversion, in particular to a BINARY-based data stream converter which comprises a data input module, a data format module, an FID module, a data processing module and a data output module; the data format module comprises a format head generation module and a format tail generation module; the FID module comprises an FID generation module and an FID conversion module; the data processing module comprises a data stream conversion module and a BARM memory. The converter can be applied to the upstream STEP / FAST hardware decoding system and the downstream MDS software system as an independent module between two different protocols, so that the two different protocol systems can normally communicate without any modification, and the compatibility and standardization of the whole data link are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of data conversion, and particularly relates to a BINARY-based data stream converter. BACKGROUND

[0002] The BINARY data format is one of the data interface specifications of the Shanghai Stock Exchange market gateway, that is, the Shanghai Stock Exchange market gateway BINARY data interface specification; the mechanism and related data exchange format for transmitting market data by accessing the Shanghai Stock Exchange market gateway MDGW through the BINARY protocol.

[0003] All numerical fields of the BINARY adopt high byte sequence (BIG_ENDIAN) coding, each BINARY message is composed of a message header, a message body and a message tail, and the maximum length of the message is 8K bytes. However, the data types of the message header, the message body and the message tail in the BINARY message are inconsistent, and the length of each field corresponding to the data sent by the upstream hardware decoding is a fixed length of 16B (128bit). If the fixed-length data stream is directly sent, there are two problems:

[0004] First, the receiving data of the downstream terminal needs to be modified in format, which is not conducive to the compatibility of the system;

[0005] Second, it will cause data length redundancy, thereby reducing the efficiency of data transmission and increasing the data receiving delay.

[0006] Therefore, there is an urgent need for a technology to solve the problem. SUMMARY

[0007] The present application aims to overcome the problems of the prior art and provides a BINARY-based data stream converter for converting the data stream output by the upstream terminal with each field being a raw fixed number of bits into a BINARY data format output data stream, so that the data stream after hardware decoding can conform to the BINARY data format output, and the downstream terminal can directly receive and decode the data without modification, thereby having higher compatibility.

[0008] The above object is achieved by the following technical scheme:

[0009] A BINARY-based data stream converter, comprising a data input module, a data format module, an FID module, a data processing module and a data output module;

[0010] The data input module is configured to receive the raw data stream sent by the STEP / FAST hardware decoding terminal and send the raw data stream to the data format module and the data processing module, respectively;

[0011] The data format module generates a head field and a tail field of a BINARY data format according to the original data stream and sends to the data processing module for data processing;

[0012] The FID module generates an FID for each field of the BINARY data format according to each field and a bit width of a BRAM memory and generates corresponding parameters;

[0013] The data processing module converts the head field, the BINARY data stream and the tail field of the BINARY data format according to the parameters generated by the FID module and stores in the BRAM memory;

[0014] The data output module is used for outputting the data stored in the BRAM memory to a MDS receiving end.

[0015] Further, the data format module comprises a format head generating module and a format tail generating module, the format head generating module generates a head field of a BINARY data format from the original data stream according to a BINARY data format specification, and the format tail generating module calculates a checksum of the BINARY data format, i.e. a tail field, from the original data stream according to the BINARY data format specification.

[0016] Further, the FID module comprises an FID generating module and an FID conversion module, the FID generating module is used for generating an FID, and each field of the BINARY data format is assigned a unique FID, and the FID conversion module is used for generating corresponding parameters for each field of the BINARY data format according to the FID.

[0017] Further, the parameters comprise an address, a position and a byte number of a field stored in the BRAM memory.

[0018] Further, the data processing module comprises a data stream conversion module and the BRAM memory, the data stream conversion module converts the original data stream into a BINARY data stream according to the generated FID, address, position and byte number of the field, and the BRAM memory stores the head field, the tail field and the BINARY data stream in sequence according to the BINARY data format.

[0019] Further, the data input module receives the original data stream according to an AXIS4 protocol and realizes communication with an upstream.

[0020] Furthermore, the data output module outputs the data stored in the BRAM memory sequentially according to the AXIS4 protocol, thereby enabling communication with downstream devices.

[0021] Furthermore, the data input module, the data format module, the FID module, the data processing module, and the data output module are disposed in an FPGA or AISC.

[0022] Beneficial effects

[0023] The present invention provides a BINARY-based data stream converter, which can be used as an independent module between the upstream STEP / FAST hardware decoding system and the downstream MDS software system, which have different protocols. This allows the two systems with different protocols to communicate normally without any modifications, thereby improving the compatibility and standardization of the entire data link. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the structure of a data stream converter based on BINARY as described in this invention;

[0025] Figure 2 This is a schematic diagram of the upstream and downstream connections of a BINARY-based data stream converter according to the present invention. Detailed Implementation

[0026] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. The described embodiments are merely some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0027] like Figure 1 As shown, a BINARY-based data stream converter includes a data input module, a data format module, an FID module, a data processing module, and a data output module. The data input module, the data format module, the FID module, the data processing module, and the data output module are disposed in an FPGA or ASIC.

[0028] like Figure 2 As shown, this converter has two communication ports: one for receiving decoded data to complete communication with the decoding system, using the AXIS4 handshake protocol; the other for outputting the converted BINARY data format stream, also using the AXIS4 handshake protocol. Wherein:

[0029] The data input module receives the original data stream from the upstream STEP / FAST hardware decoding system, and the handshake protocol is AXIS4, which is based on the high level of valid and ready signals to handshake, to achieve the operation of receiving data, and to judge whether a single FAST data packet is ended by judging the value of the last signal; after the handshake, the data is sent to the data format module and the data processing module for subsequent processing.

[0030] The data format module generates the head field and tail field of the BINARY data format according to the original data stream, and sends them to the data processing module for data processing; specifically, the data format module includes a format head generation module and a format tail generation module, the format head generation module generates the head field of the BINARY data format from the original data stream according to the BINARY data format specification; the format tail generation module calculates the checksum, i.e. the tail field of the BINARY data format, from the original data stream according to the BINARY data format specification;

[0031] The FID module generates an FID for each field according to the BINARY data format and the bit width of the BRAM memory, and generates the corresponding parameters; specifically, the FID module includes an FID generation module and an FID conversion module, the FID generation module is used to complete the generation of FID, and each field in the BINARY data format is assigned a unique FID; the FID conversion module is used to generate the corresponding parameters for each field in the BINARY data format according to the FID, the parameters include the address, position and byte number of the field stored in the BRAM memory;

[0032] The data processing module converts the head field of the BINARY data format, the BINARY data stream and the tail field of the BINARY data format according to the parameters generated by the FID module, and stores them in the BRAM memory; specifically, the data processing module includes a data stream conversion module and the BARM memory, the data stream conversion module converts the original data stream into a BINARY data format data stream according to the generated FID, address, position and byte number of the field; the BRAM memory stores the head field, tail field and BINARY data stream converted by the data stream conversion module according to the BINARY data format sequence;

[0033] The data output module is used to output the data stored in the BRAM memory to the MDS receiving end.

[0034] The above merely illustrates the embodiments of the present application, and is not intended to limit the present application. Any modification, equivalent replacement, improvement, etc. made by those skilled in the art within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A BINARY based data stream converter, characterized in that, The data input module, the data format module, the FID module, the data processing module and the data output module are included. The data input module is used for receiving the original data stream sent by the STEP / FAST hardware decoding end and sending to the data format module and the data processing module respectively; the original data stream refers to the original market data information without conversion, which is the input source of the converter. The data format module generates the head field and the tail field of the BINARY data format according to the original data stream and sends to the data processing module for data processing. The FID module generates an FID for each field of the BINARY data format according to the bit width of the BRAM memory and generates corresponding parameters; the FID module includes an FID generation module and an FID conversion module; the FID generation module is used for completing the generation of the FID and giving a unique FID to each field in the BINARY data format; the FID conversion module is used for generating corresponding parameters for each field in the BINARY data format according to the FID, the parameters including the address, the position and the byte number of the field stored in the BRAM memory. The data processing module includes a data stream conversion module and the BRAM memory; the data stream conversion module converts the original data stream into a BINARY data stream according to the generated FID, address, position and byte number of the field; the data stream conversion module receives the head field and the tail field of the BINARY data format generated by the data format module, and then integrates to form a BINARY data stream and stores in the BRAM memory. The data output module is used for outputting the data stored in the BRAM memory to the MDS receiving end.

2. The BINARY based data stream converter of claim 1, wherein, The data format module includes a format head generation module and a format tail generation module; the format head generation module generates the head field of the BINARY data format from the original data stream according to the BINARY data format; the format tail generation module calculates the checksum, i.e. the tail field of the BINARY data format from the original data stream according to the BINARY data format.

3. The BINARY based data stream converter of claim 1, wherein, The data input module receives the original data stream according to the AXIS4 protocol to realize the upstream communication.

4. The BINARY based data stream converter of claim 1, wherein, The data output module outputs the data stored in the BRAM memory according to the AXIS4 protocol to realize the downstream communication.

5. The BINARY based data stream converter of claim 1, wherein, The data input module, the data format module, the FID module, the data processing module and the data output module are arranged in the FPGA or the AISC.

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