electronic devices

Abstract

The present disclosure provides an electronic device. The electronic device includes a detection circuit. The detection circuit includes a programming detection circuit, a light-emitting detection circuit, and a judgment circuit. The programming detection circuit receives a scan signal, a reset signal, and a light-emitting enable signal from a driver circuit for a pixel unit, and provides a first detection signal in a first phase based on the scan signal, the reset signal, and the light-emitting enable signal. The light-emitting detection circuit receives the scan signal, the reset signal, and the light-emitting enable signal, and provides a second detection signal in a second phase based on the scan signal, the reset signal, and the light-emitting enable signal. The judgment circuit determines whether to output the light-emitting enable signal to the driver circuit based on the first detection signal and the second detection signal.

Description

Technical Field

[0001] The present disclosure relates to an electronic device, and more particularly to an electronic device capable of detecting signals. Background Art

[0002] Generally speaking, existing devices (such as display devices) operate in response to at least one signal, thereby providing the intended functionality corresponding to the at least one signal. However, if the waveform or timing of the at least one signal is abnormal, the device may malfunction and fail to provide the intended functionality. Therefore, to reduce device malfunctions, the at least one signal must be detected in real time. Summary of the Invention

[0003] The present disclosure is directed to an electronic device capable of detecting signals.

[0004] According to an embodiment of the present disclosure, an electronic device includes a detection circuit, wherein the detection circuit includes a programming detection circuit, a light detection circuit, and a judgment circuit. The programming detection circuit receives a scan signal, a reset signal, and a light-enabling signal for a driving circuit, and provides a first detection signal in a first phase based on the scan signal, the reset signal, and the light-enabling signal. The light detection circuit receives the scan signal, the reset signal, and the light-enabling signal, and provides a second detection signal in a second phase based on the scan signal, the reset signal, and the light-enabling signal. The judgment circuit is coupled to the programming detection circuit and the light detection circuit. The judgment circuit determines whether to output the light-enabling signal to the driving circuit based on the first detection signal and the second detection signal.

[0005] According to an embodiment of the present disclosure, an electronic device includes a detection circuit, wherein the detection circuit includes a drive detection circuit, a judgment circuit, and a correction circuit. The drive detection circuit receives a scan signal and a light-emitting enable signal for the drive circuit and provides a drive detection signal based on the scan signal and the light-emitting enable signal. The judgment circuit is coupled to the drive detection circuit. Based on the drive detection signal, the judgment circuit determines whether to output the scan signal and the light-emitting enable signal to the next-stage drive circuit. The correction circuit is coupled to the judgment circuit. The correction circuit corrects the level of the output of the judgment circuit based on the scan signal and the light-emitting enable signal.

[0006] Based on the above, the detection circuit detects multiple signals to provide at least one detection signal, and determines whether to output the signal to the driver circuit based on the at least one detection signal. In this way, the detection circuit of the present disclosure can determine whether the multiple signals are abnormal based on the at least one detection signal, and accordingly stop outputting the multiple signals to the driver circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1is a schematic diagram of an electronic device according to a first embodiment of the present invention;

[0008] Figure 2A is a normal signal timing diagram according to an embodiment of the present invention;

[0009] Figures 2B to 2D They are respectively abnormal signal timing diagrams shown according to an embodiment of the present invention;

[0010] Figure 3 is a first circuit schematic diagram of a detection circuit according to the first embodiment;

[0011] Figure 4 is a second circuit diagram of the detection circuit shown in the first embodiment;

[0012] Figure 5 is a third circuit diagram of the detection circuit shown in the first embodiment;

[0013] Figure 6 is a schematic diagram of an electronic device according to a second embodiment of the present invention;

[0014] Figure 7 is a first circuit schematic diagram of a detection circuit according to the second embodiment;

[0015] Figure 8 is a second circuit schematic diagram of a detection circuit according to the second embodiment;

[0016] Figure 9 is a third circuit diagram of the detection circuit according to the second embodiment;

[0017] Figure 10 is a schematic diagram of an electronic device according to a third embodiment of the present invention.

[0018] Description of Reference Numerals

[0019] 10, 30, 40: Electronic devices

[0020] 100, 200, 200', 200", 300, 400, 400', 400": Detection circuit

[0021] 110, 210: Programming detection circuit

[0022] 120, 220: Luminescence detection circuit

[0023] 130, 230, 230', 230", 320, 420, 420', 420": Judgment circuit

[0024] 231, 421: Voltage stabilization circuit

[0025] 232: Pull-up circuit

[0026] 233: Transmission Circuit

[0027] 234, 234', 234", 424, 424', 424": Pull-down circuit

[0028] 310, 410: drive detection circuit

[0029] 330, 430: Correction circuit

[0030] 440: Reset circuit

[0031] C1, C2, CC: capacitors

[0032] DC: driving circuit

[0033] DCN: Next level drive circuit

[0034] EM[n]: luminous enable signal

[0035] EM[n+1]: Next level light-enabling signal

[0036] LE: Light Emitting Component

[0037] NDC: Control Node

[0038] NDB, NDB': voltage stabilization nodes

[0039] P1: Phase 1

[0040] P2: Phase 2

[0041] PU: Pixel Unit

[0042] R1, R2: resistors

[0043] RST[n]: reset signal

[0044] SD1: First detection signal

[0045] SD2: Second detection signal

[0046] SD3: drive detection signal

[0047] SN[n]: Scan signal

[0048] SN[n+1]: Next level scanning signal

[0049] T1, T1': first detection transistor

[0050] T2, T2': second detection transistor

[0051] T3: The third detection transistor

[0052] T3'~T13', T6~T11: transistors

[0053] T4: fourth detection transistor

[0054] T5: Fifth detection transistor

[0055] TD: driver transistor

[0056] TEM: Enable Transistor

[0057] TR: Reset Transistor

[0058] TS: Scan transistor

[0059] VGH: High voltage

[0060] VGL: Low Voltage

[0061] VRST: Reset Bias DETAILED DESCRIPTION

[0062] The present disclosure may be understood by referring to the following detailed description in conjunction with the accompanying drawings, as described below. It should be noted that for the purposes of clarity and ease of understanding, the various figures of the present disclosure illustrate portions of electronic devices, and that certain components in the various figures may not be drawn to scale. Furthermore, the number and size of each device shown in the figures are for illustrative purposes only and are not intended to limit the scope of the present disclosure.

[0063] Certain terms are used throughout the description and in the claims that follow to refer to specific components. As will be understood by those skilled in the art, electronic device manufacturers may refer to components by different names. This document does not intend to distinguish between components that differ in name but not in function. In the following description and in the claims, the terms "comprising," "including," and "having" are used in an open-ended manner and, therefore, should be interpreted to mean "including, but not limited to..." Therefore, when the terms "comprising," "including," and / or "having" are used in the description of the present disclosure, it will indicate the presence of corresponding features, regions, steps, operations, and / or components, but is not limited to the presence of one or more corresponding features, regions, steps, operations, and / or components.

[0064] It should be understood that when a component is referred to as being “coupled,” “connected,” or “in conduction” to another component, the component may be directly connected to the other component and an electrical connection may be directly established, or an intermediate component may be present between the components for relaying the electrical connection (indirect electrical connection). In contrast, when a component is referred to as being “directly coupled,” “directly in conduction,” or “directly connected” to another component, there are no intermediate components.

[0065] Although terms such as first, second, and third may be used to describe different components, such components are not limited by these terms. Terms are used only to distinguish components in the specification from other components. Claims may not use the same terms, but may use terms such as first, second, and third relative to the order in which the components are required. Therefore, in the following description, the first component may be the second component in the claim.

[0066] The electronic devices disclosed herein may include antennas, displays, light emitting, sensing, touch, splicing, packaging, other suitable functions, or combinations of the above functions, but are not limited thereto. The electronic devices include rollable or flexible electronic devices, but are not limited thereto. The electronic devices may, for example, include liquid crystal, light emitting diodes (LEDs), quantum dots (QDs), fluorescence, phosphors, packaging components, other suitable materials, or combinations thereof. The electronic devices may, for example, include electronic components, wherein the electronic components may include passive components and active components, such as capacitors, resistors, inductors, diodes, transistors, circuit boards, chips, dies, integrated circuits (ICs), packaging components, or combinations of the above components or other suitable electronic components, but are not limited thereto. The diodes may include light emitting diodes, photodiodes, or antenna diodes, but are not limited thereto. The light-emitting diode may include, for example, an organic light-emitting diode (OLED), a sub-millimeter light-emitting diode (mini LED), a micro LED, or a quantum dot light-emitting diode (including QLED, QDLED), or other suitable materials, or a combination thereof, but is not limited thereto. The packaging component may include, for example, a circuit redistribution layer (REDI), a wafer-level packaging (WLP), a panel-level packaging (PLP), or other packaging components, but is not limited thereto. The sensing device may include a camera, an infrared sensor, or a fingerprint sensor, but the present disclosure is not limited thereto. In some embodiments, the sensing device may also include a flash, an infrared (IR) light source, other sensors, electronic components, or a combination thereof, but is not limited thereto. The appearance of the electronic device may be rectangular, circular, polygonal, a shape with curved edges, or other suitable shape. The electronic device may have peripheral systems such as a drive system, a control system, a light source system, etc. to support the display device, antenna device, or splicing device, but the present disclosure is not limited thereto. In the present disclosure, embodiments use the term "pixel" or "pixel unit" to describe a specific area containing at least one functional circuit for at least one specific function. The area of ​​a "pixel" depends on the unit used to provide the specific function. Adjacent pixels may share the same parts or wires, but may also contain their own specific parts.For example, adjacent pixels may share the same scan line or the same data line, but a pixel may also have its own transistor or capacitor.

[0067] It should be noted that the technical features in the different embodiments described below may be replaced, recombined, or mixed with each other to constitute another embodiment without departing from the spirit of the present disclosure.

[0068] Please refer to Figure 1 , Figure 1 is a schematic diagram of an electronic device according to a first embodiment of the present invention. In this embodiment, the electronic device 10 includes a pixel circuit PU and a detection circuit 100. The pixel circuit PU includes a driving circuit DC and a light-emitting element LE. The detection circuit 100 includes a programming detection circuit 110, a light-emitting detection circuit 120, and a determination circuit 130. The programming detection circuit 110 receives a scan signal SN[n], a reset signal RST[n], and a light-emitting enable signal EM[n] for the driving circuit DC. The programming detection circuit 110 provides a first detection signal SD1 in the first phase based on the scan signal SN[n], the reset signal RST[n], and the light-emitting enable signal EM[n]. The light-emitting detection circuit 120 receives the scan signal SN[n], the reset signal RST[n], and the light-emitting enable signal EM[n]. The light-emitting detection circuit 120 provides a second detection signal SD2 in the second phase based on the scan signal SN[n], the reset signal RST[n], and the light-emitting enable signal EM[n].

[0069] In this embodiment, the determination circuit 130 is coupled to the programming detection circuit 110 and the light detection circuit 120. The determination circuit 130 determines whether to output the light enabling signal EM[n] to the driving circuit DC according to the first detection signal SD1 and the second detection signal SD2.

[0070] The determination circuit 130 determines whether an abnormality has occurred in the first or second phase based on the first detection signal SD1 and the second detection signal SD2. If an abnormality is determined in at least one of the first or second phases, the determination circuit 130 stops outputting the light-enabling signal to the driver circuit. On the other hand, if an abnormality is determined in neither the first or second phases, the determination circuit 130 continues outputting the light-enabling signal to the driver circuit. For example, if the first detection signal SD1 indicates an abnormality, the determination circuit 130 determines that an abnormality has occurred in one of the scan signal SN[n], the reset signal RST[n], and the light-enabling signal EM[n] during the first phase. Therefore, the determination circuit 130 stops outputting the light-enabling signal EM[n] to the driver circuit DC. If the second detection signal SD2 indicates an abnormality, the determination circuit 130 determines that an abnormality has occurred in one of the scan signal SN[n], the reset signal RST[n], and the light-enabling signal EM[n] during the second phase. Therefore, the determination circuit 130 stops outputting the light-emitting enable signal EM[n] to the driver circuit DC. When neither the first detection signal SD1 nor the second detection signal SD2 indicates an abnormality, the determination circuit 130 determines that the scan signal SN[n], the reset signal RST[n], and the light-emitting enable signal EM[n] are all normal. Therefore, the determination circuit 130 outputs the light-emitting enable signal EM[n] to the driver circuit DC.

[0071] It is worth noting that the detection circuit 100 detects the scan signal SN[n], the reset signal RST[n], and the light-emitting enable signal EM[n] to provide a first detection signal SD1 and a second detection signal SD2. The detection circuit 100 determines whether to output the light-emitting enable signal EM[n] to the driver circuit DC based on the first detection signal SD1 and the second detection signal SD2. In this way, the detection circuit 100 can determine whether the scan signal SN[n], the reset signal RST[n], and the light-emitting enable signal EM[n] are abnormal based on the first detection signal SD1 and the second detection signal SD2, and accordingly stop outputting the light-emitting enable signal EM[n] to the driver circuit DC.

[0072] In this embodiment, the detection circuit 100 can be applied to a display device, for example. The driving circuit DC is, for example, a pixel driving circuit disposed in the pixel unit PU (the present disclosure is not limited thereto). In this embodiment, the driving circuit DC can utilize a scan signal SN[n], a reset signal RST[n], and a light-emitting enable signal EM[n] to drive the light-emitting element LE disposed in the pixel unit PU. The light-emitting element LE can be at least one light-emitting diode or other suitable electronic component. Taking this embodiment as an example, the driving circuit DC includes a scan transistor TS, a reset transistor TR, a drive transistor TD, an enable transistor TEM, and a capacitor CC. A first terminal of the scan transistor TS receives a data signal VD. A second terminal of the scan transistor TS is coupled to a control node NDC. A control terminal of the scan transistor TS receives the scan signal SN[n]. A first terminal of the reset transistor TR is coupled to the control node NDC. A second terminal of the reset transistor TR is coupled to a reset bias voltage VRST. A control terminal of the reset transistor TR receives the reset signal RST[n]. The reset signal RST[n] can be a previous scan signal (e.g., scan signal SN[n-1], but the present disclosure is not limited thereto). A first terminal of the driving transistor TD receives a high reference voltage ARVDD. A control terminal of the driving transistor TD is coupled to a control node NDC. A first terminal of the enabling transistor TEM is coupled to a second terminal of the driving transistor TD. The control terminal of the enabling transistor TEM receives a light-emission enable signal EM[n] via a determination circuit 130. A first terminal of the light-emitting element LE is coupled to a second terminal of the enabling transistor TEM. A second terminal of the light-emitting element LE is coupled to a second terminal of the enabling transistor TEM and receives a low reference voltage ARVSS. A capacitor CC is coupled between the first terminal of the driving transistor TD and the control terminal of the driving transistor TD. In this embodiment, the scan transistor TS, the reset transistor TR, the driving transistor TD, and the enabling transistor TEM are each, for example, P-type transistors, but the present disclosure is not limited thereto. Therefore, in this embodiment, the driving circuit DC operates based on the negative pulses of the scan signal SN[n], the reset signal RST[n], and the light-emission enable signal EM[n]. The driving circuit DC in this embodiment is implemented, for example, with a 4-transistor and 1-capacitor (4T1C) architecture, but the present disclosure is not limited thereto. Circuits capable of driving components based on the scan signal SN[n], the reset signal RST[n], and the light-emitting enable signal EM[n] all fall within the scope of the driving circuit DC of the present disclosure.

[0073] In this embodiment, where the detection circuit 100 can be applied to a display device, for example, the first phase is a data input phase for the driver circuit DC. Therefore, the determination circuit 130 can use the first detection signal SD1 to determine whether an abnormality has occurred in the scan signal SN[n], reset signal RST[n], and light-emitting enable signal EM[n] during the data input phase. Furthermore, the second phase is a light-emitting phase for the driver circuit DC. Therefore, the determination circuit 130 can use the second detection signal SD2 to determine whether an abnormality has occurred in the scan signal SN[n], reset signal RST[n], and light-emitting enable signal EM[n] during the light-emitting phase.

[0074] Please also refer to Figure 1 as well as Figure 2A , Figure 2A is a normal signal timing diagram according to an embodiment of the present invention. Figure 2A A normal timing diagram of the scan signal SN[n], the reset signal RST[n], and the light-emitting enable signal EM[n] is shown. In the first phase P1, the light-emitting enable signal EM[n] is at a high level. The reset signal RST[n] has a negative pulse. The scan signal SN[n] also has a negative pulse. The timing of the negative pulse of the reset signal RST[n] precedes the timing of the negative pulse of the scan signal SN[n]. The negative pulse of the reset signal RST[n] and the negative pulse of the scan signal SN[n] do not overlap in timing. Therefore, the programming detection circuit 110 provides a first detection signal SD1 having a first level (e.g., a high level) based on the above timing in the first phase P1.

[0075] In the second phase P2, the light-emitting enable signal EM[n] is at a low level. The reset signal RST[n] and the scan signal SN[n] are both at a high level. Therefore, the light-emitting detection circuit 120 provides a second detection signal SD2 having a first level according to the timing sequence in the second phase P2.

[0076] The determination circuit 130 outputs the light-emitting enable signal EM[n] to the driving circuit DC according to the first detection signal SD1 and the second detection signal SD2 having the first level.

[0077] Figures 2B to 2D They are respectively abnormal signal timing diagrams shown according to an embodiment of the present invention. Please also refer to Figure 1 as well as Figure 2B , Figure 2BThe following diagram illustrates an abnormal timing sequence of scan signal SN[n] during the first phase P1. During the first phase P1, scan signal SN[n] does not have a negative pulse. Therefore, the programming detection circuit 110 provides a first detection signal SD1 having a second level (e.g., a low level) according to the timing sequence during the first phase P1. The determination circuit 130 stops outputting the emission enable signal EM[n] to the driver circuit DC based on the first detection signal SD1 having the second level.

[0078] Please also refer to Figure 1 as well as Figure 2C , Figure 2C FIG. 1 shows an abnormal timing diagram of the light-emitting enable signal EM[n] in the first phase P1. In the first phase P1, when the light-emitting enable signal EM[n] is at a low level, the program detection circuit 110 also provides the first detection signal SD1 of the second level.

[0079] Please also refer to Figure 1 as well as Figure 2D , Figure 2D FIG2 shows an abnormal timing diagram of the scan signal SN[n] in the second phase P2. In the second phase P2, the scan signal SN[n] and the reset signal RST[n] have at least one negative pulse. Therefore, the light detection circuit 120 provides a second detection signal SD2 having a second level according to the timing sequence in the second phase P2. The determination circuit 130 stops outputting the light-enabling signal EM[n] to the driver circuit DC based on the second detection signal SD2 having the second level. In some embodiments, in the second phase P2, when the light-enabling signal EM[n] is at a high level, the programming detection circuit 110 also provides a second detection signal SD2 having a second level.

[0080] Please refer to Figure 3 , Figure 3 2 is a first circuit diagram of a detection circuit according to the first embodiment. In this embodiment, the detection circuit 200 includes a programming detection circuit 210, a light-emitting detection circuit 220, and a determination circuit 230. The programming detection circuit 210 includes a first detection transistor T1 and a second detection transistor T2. A first terminal of the first detection transistor T1 and a control terminal of the first detection transistor T1 receive a reset signal RST[n]. A second terminal of the first detection transistor T1 is coupled to a voltage regulation node NDB. A first terminal of the second detection transistor T2 is coupled to the voltage regulation node NDB. A second terminal of the second detection transistor T2 receives a light-emitting enable signal EM[n]. A control terminal of the second detection transistor T2 receives a scan signal SN[n].

[0081] The light detection circuit 220 includes a third detection transistor T3, a fourth detection transistor T4, and a fifth detection transistor T5. A first terminal of the third detection transistor T3 is coupled to a voltage regulation node NDB. A control terminal of the third detection transistor T3 receives a scan signal SN[n]. A first terminal of the fourth detection transistor T4 is coupled to the voltage regulation node NDB. A control terminal of the fourth detection transistor T4 receives a reset signal RST[n]. A first terminal of the fifth detection transistor T5 is coupled to a second terminal of the third detection transistor T3 and a second terminal of the fourth detection transistor T4. A second terminal of the fifth detection transistor T5 is coupled to a low voltage VGL. A control terminal of the fifth detection transistor T5 receives a light enable signal EM[n].

[0082] The determination circuit 230 includes a voltage regulator circuit 231, a pull-up circuit 232, a transmission circuit 233, and a pull-down circuit 234. The voltage regulator circuit 231 is coupled to a voltage regulator node NDB. The voltage regulator circuit 231 provides a regulated voltage to the voltage regulator node NDB. The pull-up circuit 232 is coupled to the voltage regulator node NDB. The transmission circuit 233 is coupled to the pull-up circuit 232. The pull-down circuit 234 is coupled to the transmission circuit 233. In this embodiment, the pull-up circuit 232 is disabled in response to a first level (e.g., a high level) at the voltage regulator node NDB, causing the pull-down circuit 234 to turn on the transmission circuit 233 and output the light-emitting enable signal EM[n] to the driver circuit DC. The pull-up circuit 232 is enabled in response to a second level (e.g., a low level) at the voltage regulator node NDB, causing the transmission circuit 233 to be disconnected and stop outputting the light-emitting enable signal EM[n] to the driver circuit DC.

[0083] In this embodiment, the voltage regulator circuit 231 includes a capacitor C1. Capacitor C1 is coupled between a high voltage VGH and a voltage regulator node NDB. The voltage regulator circuit 231 can use the high voltage VGH to provide a bias voltage to the voltage regulator node NDB. The pull-up circuit 232 includes a transistor T6. The first terminal of transistor T6 is coupled to the high voltage VGH. The second terminal of transistor T6 is coupled to the transmission circuit 233. The control terminal of transistor T6 is coupled to the voltage regulator node NDB and the voltage regulator circuit 231. The transmission circuit 233 includes transistors T7 and T8. The first terminal of transistor T7 is coupled to the second terminal of transistor T6. The control terminal of transistor T7 receives the light-emitting enable signal EM[n]. The first terminal of transistor T8 is coupled to the control terminal of transistor T7 to receive the light-emitting enable signal EM[n]. The second terminal of transistor T8 is coupled to the first terminal of transistor T7. The second terminal of transistor T8 serves as the output terminal of the determination circuit 230. The control terminal of transistor T8 is coupled to the second terminal of transistor T7. The pull-down circuit 234 includes a resistor R1. The resistor R1 is coupled between the control terminal of the transistor T8 and the low voltage VGL.

[0084] In this embodiment, the first detection transistor T1, the second detection transistor T2, the third detection transistor T3, the fourth detection transistor T4, the fifth detection transistor T5, and the transistors T6 to T8 are each exemplified as a P-type transistor. In some embodiments, the first detection transistor T1, the second detection transistor T2, the third detection transistor T3, the fourth detection transistor T4, the fifth detection transistor T5, and the transistors T6 to T8 may also be an N-type transistor.

[0085] Please also refer to Figure 1 、 Figure 2A as well as Figure 3 In this embodiment, during the first phase P1, based on the normal timing of the scan signal SN[n], the reset signal RST[n], and the light-emitting enable signal EM[n], the first detection transistor T1 and the second detection transistor T2 can jointly provide a first detection signal SD1 having a first level (high level) to the voltage-stabilizing node NDB. Furthermore, during the second phase P2, based on the normal timing of the scan signal SN[n], the reset signal RST[n], and the light-emitting enable signal EM[n], the third detection transistor T3, the fourth detection transistor T4, and the fifth detection transistor T5 can jointly provide a second detection signal SD2 having a first level to the voltage-stabilizing node NDB. Both the first detection signal SD1 and the second detection signal SD2 have a high level. Therefore, the voltage level at the voltage-stabilizing node NDB is maintained at a high level. Transistor T6 is turned off. The voltage value of the control terminal of transistor T8 is pulled down to a low level by the pull-down circuit 234. Therefore, transistor T8 is turned on to output the received light-emitting enable signal EM[n] to the driving circuit DC.

[0086] Please also refer to Figure 1 、 Figure 2B as well as Figure 3 In this embodiment, in the first phase P1, based on the abnormal timing of the scan signal SN[n], the first detection transistor T1 and the second detection transistor T2 can jointly provide a first detection signal SD1 having a second level (low level) to pull down the level at the voltage regulation node NDB. Transistor T6 is turned on. Transistor T6 uses the high voltage VGH to set the level of the second end of transistor T8 to a high level. Therefore, the enable transistor TEM of the drive circuit DC stops driving the light-emitting element LE based on the high level at the second end of transistor T8. In addition, in the second phase P2, the light-emitting enable signal EM[n] has a low level. Transistor T7 is turned on in response to the light-emitting enable signal EM[n] having a low level. Transistor T6 uses the high voltage VGH to turn off transistor T8. Therefore, the light-emitting enable signal EM[n] having a low level is turned on and is not output to the drive circuit DC.

[0087] Please also refer to Figure 1 、 Figure 2C as well as Figure 3 In this embodiment, in the first phase P1, based on the light-emitting enable signal EM[n] having a low level, the first detection transistor T1 and the second detection transistor T2 can jointly provide a first detection signal SD1 having a second level (low level) to pull down the level at the voltage regulation node NDB. Transistor T6 is turned on. Transistor T7 is turned on in response to the light-emitting enable signal EM[n] having a low level. Transistor T6 uses the high voltage VGH to set the level of the second terminal of transistor T8 and the control terminal of transistor T8 to a high level. Therefore, transistor T8 is turned off. In addition, the enable transistor TEM of the driving circuit DC stops driving the light-emitting element LE based on the high level at the second terminal of transistor T8. In the second phase P2, the light-emitting enable signal EM[n] still has a low level. Therefore, transistor T8 is still turned off. The light-emitting enable signal EM[n] having a low level is turned on and is not output to the driving circuit DC.

[0088] Please also refer to Figure 1 、 Figure 2D as well as Figure 3 In this embodiment, in the second phase P2, based on the abnormal timing of the scan signal SN[n] and the reset signal RST[n] having negative pulses, the third detection transistor T3, the fourth detection transistor T4, and the fifth detection transistor T5 can jointly provide a second detection signal SD2 having a second level (low level) to pull down the level at the voltage regulation node NDB. Transistor T6 is turned on. Transistor T7 is turned on in response to the low level of the light-emitting enable signal EM[n]. Transistor T6 uses the high voltage VGH to set the level of the second terminal of transistor T8 and the control terminal of transistor T8 to a high level. Therefore, transistor T8 is turned off. In addition, the enable transistor TEM of the driving circuit DC stops driving the light-emitting element LE based on the high level at the second terminal of transistor T8. In the second phase P2, the light-emitting enable signal EM[n] still has a low level. Therefore, transistor T8 is still turned off. The low level light-emitting enable signal EM[n] is turned on and is not output to the driving circuit DC.

[0089] Please refer to Figure 4 , Figure 42 is a second circuit diagram of the detection circuit according to the first embodiment. In this embodiment, the detection circuit 200′ includes a programming detection circuit 210, a light-emission detection circuit 220, and a determination circuit 230′. The implementation of the programming detection circuit 210 and the light-emission detection circuit 220 can be referred to in the previous embodiment and will not be repeated here. The determination circuit 230′ includes a voltage regulator circuit 231, a pull-up circuit 232, a transmission circuit 233, and a pull-down circuit 234′. The implementation of the voltage regulator circuit 231, the pull-up circuit 232, and the transmission circuit 233 can be referred to in the previous embodiment and will not be repeated here. In this embodiment, the pull-down circuit 234′ includes a transistor T9. A first terminal of the transistor T9 is coupled to the control terminal of the transistor T8. A second terminal of the transistor T9 and the control terminal of the transistor T9 are coupled to a low voltage VGL. The transistor T9 is configured to provide an equivalent resistor between the control terminal of the transistor T8 and the low voltage VGL. In this embodiment, the transistor T9 is exemplified as a P-type transistor, but the present disclosure is not limited thereto.

[0090] Please refer to Figure 5 , Figure 5 2 is a third circuit diagram of the detection circuit shown in the first embodiment. In this embodiment, the detection circuit 200" includes a programming detection circuit 210, a light-emitting detection circuit 220, and a judgment circuit 230". The implementation of the programming detection circuit 210 and the light-emitting detection circuit 220 can refer to the aforementioned embodiments and are not repeated here. The judgment circuit 230" includes a voltage-stabilizing circuit 231, a pull-up circuit 232, a transmission circuit 233, and a pull-down circuit 234". The implementation of the voltage-stabilizing circuit 231, the pull-up circuit 232, and the transmission circuit 233 can refer to the aforementioned embodiments and are not repeated here. In this embodiment, the pull-down circuit 234″ includes transistors T9, T10, and T11. The first terminal of the transistor T9 is coupled to the control terminal of the transistor T8. The second terminal of the transistor T9 is coupled to the low voltage VGL. The first terminal of the transistor T10 is coupled to the high voltage VGH. The second terminal of the transistor T10 is coupled to the control terminal of the transistor T9. The control terminal of the transistor T10 is coupled to the voltage regulation node NDB. The first terminal of the transistor T11 is coupled to the second terminal of the transistor T10. The second terminal of the transistor T11 and the control terminal of the transistor T11 are coupled to the low voltage VGL. The transistor T11 is used to provide an equivalent resistor between the control terminal of the transistor T9 and the low voltage VGL.

[0091] In this embodiment, when at least one of the first detection signal SD1 and the second detection signal SD2 is at a low level, the voltage at the voltage regulation node NDB is at a low level. Transistors T6 and T10 are turned on. Therefore, transistor T6 uses the high voltage VGH to turn off transistor T8. At this time, transistor T10 uses the high voltage VGH to turn off transistor T9. Therefore, no leakage current occurs between the control terminal of transistor T8 and the low voltage VGL.

[0092] When both the first detection signal SD1 and the second detection signal SD2 are at a high level, transistors T6 and T10 are turned off. Transistor T11 pulls down the control terminal of transistor T9 to a low level, turning on transistor T9. Consequently, transistor T8 is turned on to transmit the light-emitting enable signal EM[n]. In this embodiment, transistors T9-T11 are each exemplified as a P-type transistor, but the present disclosure is not limited thereto.

[0093] Please refer to Figure 6 , Figure 6 3 is a schematic diagram of an electronic device according to a second embodiment of the present invention. In this embodiment, the electronic device 30 includes a next-stage driving circuit DCN and a detection circuit 300. The detection circuit 300 includes a driving detection circuit 310, a judgment circuit 320, and a correction circuit 330. The driving detection circuit 310 receives a signal for driving the circuit (e.g., Figure 1 1 . The drive detection circuit 310 provides a drive detection signal SD3 based on the scan signal SN[n] and the light-emitting enable signal EM[n]. The determination circuit 320 is coupled to the drive detection circuit 310. The determination circuit 320 determines whether to output the scan signal SN[n] and the light-emitting enable signal EM[n] to the next-stage drive circuit DCN based on the drive detection signal SD3. The correction circuit 330 is coupled to the determination circuit 320. The correction circuit 330 corrects the level of the output of the determination circuit 320 based on the scan signal SN[n] and the light-emitting enable signal EM[n].

[0094] In this embodiment, the detection circuit 300 can determine whether the scan signal SN[n] and the light-emitting enable signal EM[n] are abnormal according to the driving detection signal SD3 , and accordingly stop outputting the light-emitting enable signal EM[n] to the driving circuit DCN.

[0095] The detection circuit 300 can be applied to a display device, for example. The driving circuit is, for example, a pixel driving circuit disposed in a pixel unit (the present disclosure is not limited thereto). The next-stage driving circuit DCN is a gate driving circuit. In this embodiment, the next-stage driving circuit DCN transmits a scan signal SN[n] and a light-emitting enable signal EM[n] through the detection circuit 300. The next-stage driving circuit DCN generates a next-stage scanning signal SN[n+1] based on the scan signal SN[n], and generates a next-stage light-emitting enable signal EM[n+1] based on the light-emitting enable signal EM[n].

[0096] In this embodiment, the determination circuit 320 determines whether an abnormality has occurred in the scan signal SN[n] and the light-emitting enable signal EM[n] based on the drive detection signal SD3. If at least one of the scan signal SN[n] and the light-emitting enable signal EM[n] is determined to be abnormal, the determination circuit 320 stops outputting the scan signal SN[n] and the light-emitting enable signal EM[n] to the next-stage drive circuit DCN. Furthermore, the correction circuit 330 corrects the level of the output of the determination circuit 320. Consequently, the next-stage drive circuit DCN does not generate the next-stage scan signal SN[n+1] and the next-stage light-emitting enable signal EM[n+1].

[0097] On the other hand, when it is determined that neither the scan signal SN[n] nor the light-emitting enable signal EM[n] is abnormal, the determination circuit 320 outputs the scan signal SN[n] and the light-emitting enable signal EM[n] to the next-stage driver circuit DCN. Therefore, the next-stage driver circuit DCN generates the next-stage scan signal SN[n+1] and the next-stage light-emitting enable signal EM[n+1].

[0098] Please refer to the Figure 2A as well as Figure 6 In this embodiment, based on the normal timing of the scan signal SN[n] and the light-emitting enable signal EM[n], the driver detection circuit 310 does not provide the drive detection signal SD3 having the second level (low level). Therefore, the determination circuit 320 outputs the scan signal SN[n] and the light-emitting enable signal EM[n] to the next-stage driver circuit DCN.

[0099] Please refer to the Figure 2C 、 Figure 2D as well as Figure 6In this embodiment, based on the abnormal timing of the scan signal SN[n] and / or the emission enable signal EM[n], the drive detection circuit 310 provides a drive detection signal SD3 having a second level. Therefore, the determination circuit 320 can stop outputting the scan signal SN[n] and the emission enable signal EM[n] to the next-stage drive circuit DCN based on the drive detection signal SD3 having the second level. Furthermore, the correction circuit 330 corrects the level of the output of the determination circuit 320 based on the abnormal timing of the scan signal SN[n] and / or the emission enable signal EM[n].

[0100] Please refer to Figure 7 , Figure 7 1 is a first circuit diagram of an electronic device according to a second embodiment. In this embodiment, the electronic device 400 includes a drive detection circuit 410, a determination circuit 420, and a correction circuit 430. The drive detection circuit 410 includes a first detection transistor T1' and a second detection transistor T2'. The first end of the first detection transistor T1' is coupled to the low voltage VGL. The control end of the first detection transistor T1' receives the light-emitting enable signal EM[n]. The first end of the second detection transistor T2' is coupled to the second end of the first detection transistor T1'. The second end of the second detection transistor T2' is coupled to the voltage regulation node NDB'. The control end of the second detection transistor T2' receives the scan signal SN[n].

[0101] The determination circuit 420 includes a voltage regulator circuit 421, a pull-up circuit 422, a transmission circuit 423, and a pull-down circuit 424. The voltage regulator circuit 421 is coupled to the voltage regulator node NDB'. The voltage regulator circuit 421 provides a regulated voltage to the voltage regulator node NDB'. The pull-up circuit 422 is coupled to the voltage regulator node NDB'. The transmission circuit 423 is coupled to the pull-up circuit 422. The pull-down circuit 424 is coupled to the transmission circuit 423. In this embodiment, the pull-up circuit 422 is disabled in response to a first level (e.g., a high level) at the voltage regulator node NDB', causing the pull-down circuit 424 to conduct the transmission circuit 423 and output the scan signal SN[n] and the light-emitting enable signal EM[n] to the next-stage driver circuit DCN. The pull-up circuit 422 is enabled in response to a second level (e.g., a low level) at the voltage regulator node NDB', causing the transmission circuit 423 to be disconnected and stop outputting the light-emitting enable signal EM[n] to the next-stage driver circuit DCN.

[0102] In this embodiment, the voltage regulator circuit 421 includes a capacitor C2. Capacitor C2 is coupled between a high voltage VGH and a voltage regulator node NDB'. The voltage regulator circuit 421 can use the high voltage VGH to provide a bias voltage to the voltage regulator node NDB'. The pull-up circuit 422 includes a transistor T4'. A first terminal of the transistor T4' is coupled to the high voltage VGH. A second terminal of the transistor T4' is coupled to the transmission circuit 423. A control terminal of the transistor T4' is coupled to the voltage regulator node NDB'. The transmission circuit 423 includes transistors T5' and T6'. A first terminal of the transistor T5' receives a scan signal SN[n]. A second terminal of the transistor T5' is coupled to the next-stage driver circuit DCN. A second terminal of the transistor T5' serves as a first output terminal of the determination circuit 420. The control terminal of the transistor T5' is coupled to the second terminal of the transistor T4'. A first terminal of the transistor T6' receives a light-emission enable signal EM[n]. A second terminal of the transistor T6' is coupled to the next-stage driver circuit DCN. The second terminal of transistor T6' serves as the second output terminal of the determination circuit 420. The control terminal of transistor T6' is coupled to the second terminal of transistor T4'. The pull-down circuit 424 includes a resistor R2. Resistor R2 is coupled between the control terminals of transistors T5' and T6' and the low voltage VGL.

[0103] In this embodiment, the correction circuit 430 includes transistors T7', T8', T9', and T10'. The first terminal of transistor T7' is coupled to the high voltage VGH. The control terminal of transistor T7' receives the light-emitting enable signal EM[n]. The first terminal of transistor T8' is coupled to the second terminal of the first detection transistor T7'. The second terminal of transistor T8' is coupled to the second terminal of transistor T5'. The control terminal of transistor T8' receives the scan signal SN[n]. The first terminal of transistor T9' is coupled to the high voltage VGH. The control terminal of transistor T9' receives the light-emitting enable signal EM[n]. The first terminal of transistor T10' is coupled to the second terminal of the first detection transistor T9'. The second terminal of transistor T10' is coupled to the second terminal of transistor T6'. The control terminal of transistor T10' receives the scan signal SN[n].

[0104] Please also refer to Figure 2A 、 Figure 6 as well as Figure 7In this embodiment, based on the normal timing of the scan signal SN[n] and the light-emitting enable signal EM[n], the scan signal SN[n] and the light-emitting enable signal EM[n] will not have a low level at the same time. The first detection transistor T1' and the second detection transistor T2' will not be turned on at the same time. The drive detection signal SD3 with the second level (low level) will not be provided to the voltage regulating node NDB'. Therefore, the level at the voltage regulating node NDB' will be maintained at a high level. Transistor T4' will be turned off. The voltage value of the control end of transistors T5' and T6' will be pulled down to a low level by the pull-down circuit 424. Therefore, transistor T5' is turned on to output the received scan signal SN[n] to the drive circuit DCN. Transistor T6' is turned on to output the received light-emitting enable signal EM[n] to the drive circuit DCN.

[0105] Furthermore, based on the normal timing of the scan signal SN[n] and the light-emitting enable signal EM[n], the scan signal SN[n] and the light-emitting enable signal EM[n] will not be simultaneously low. Transistors T7' and T8' will not be simultaneously turned on. Transistors T9' and T10' will not be simultaneously turned on. Therefore, the correction circuit 430 will not use the high voltage VGH to correct the voltage levels at the second terminal of transistor T5' and the second terminal of transistor T6' to a high level.

[0106] Please also refer to Figure 2C 、 Figure 2D 、 Figure 6 as well as Figure 7 In this embodiment, based on the abnormal timing of the scan signal SN[n] and the light-emitting enable signal EM[n], the scan signal SN[n] and the light-emitting enable signal EM[n] will both have a low level. Therefore, the first detection transistor T1' and the second detection transistor T2' provide a drive detection signal SD3 with a second level to pull down the level at the voltage regulation node NDB'. The transistor T4' will be turned on and use the high voltage VGH to set the levels of the control terminals of the transistors T5' and T6' to a high level. Therefore, the transistors T5' and T6' are turned off. The transistor T5' is turned off to stop outputting the received scan signal SN[n] to the drive circuit DCN. The transistor T6' is turned off to stop outputting the received light-emitting enable signal EM[n] to the drive circuit DCN.

[0107] Furthermore, due to the abnormal timing of the scanning signal SN[n] and the light-emitting enable signal EM[n], transistors T7', T8', T9', and T10' are simultaneously turned on. Therefore, the correction circuit 430 uses the high voltage VGH to correct the voltage levels at the second end of the transistor T5' and the second end of the transistor T6' to a high level.

[0108] In addition, the electronic device 400 also includes a reset circuit 440. The reset circuit 440 is coupled to the voltage regulating node NDB'. The reset circuit 440 resets the level at the voltage regulating node NDB' based on a specific timing. In the present embodiment, the reset circuit 440 resets the level at the voltage regulating node NDB' based on the timing of the light-emitting enable signal EM[n]. The reset circuit 440 includes a transistor T3'. The first end of the transistor T3' receives the light-emitting enable signal EM[n]. The second end of the transistor T3' and the control end of the transistor T3' are coupled to the voltage regulating node NDB'. When the light-emitting enable signal EM[n] is at a high level, the reset circuit 440 resets the level at the voltage regulating node NDB' to a high level to allow the pull-up circuit 422 to return to a normal operating state. In the present embodiment, the first detection transistor T1', the second detection transistor T2', and the transistors T3' to T10' are each exemplified by a P-type transistor, but the present disclosure is not limited to this.

[0109] Please refer to Figure 8 , Figure 8 2 is a second circuit diagram of an electronic device according to a second embodiment. In this embodiment, the electronic device 400′ includes a drive detection circuit 410, a determination circuit 420′, a correction circuit 430, and a reset circuit 440. The implementation of the drive detection circuit 410, the correction circuit 430, and the reset circuit 440 is similar to that of the previous embodiment and will not be repeated here. The determination circuit 420′ includes a voltage regulator circuit 421, a pull-up circuit 422, a transmission circuit 423, and a pull-down circuit 424′. The implementation of the voltage regulator circuit 421, the pull-up circuit 422, and the transmission circuit 423 is similar to that of the previous embodiment and will not be repeated here. In this embodiment, the pull-down circuit 424′ includes a transistor T11′. The first terminal of the transistor T11′ is coupled to the control terminals of the transistors T5′ and T6′. The second terminal of the transistor T11′ and the control terminal of the transistor T11′ are coupled to a low voltage VGL. The transistor T11′ is used to provide an equivalent resistor between the control terminals of the transistors T5′ and T6′ and the low voltage VGL. In this embodiment, the transistor T11′ is, for example, a P-type transistor, but the present disclosure is not limited thereto.

[0110] Please refer to Figure 9 , Figure 93 is a schematic diagram of a third circuit of the electronic device shown in the second embodiment. In this embodiment, the electronic device 400" includes a drive detection circuit 410, a judgment circuit 420", a correction circuit 430 and a reset circuit 440. The implementation methods of the drive detection circuit 410, the correction circuit 430 and the reset circuit 440 are the same as those in the aforementioned embodiment, and therefore are not repeated here. The judgment circuit 420" includes a voltage stabilizing circuit 421, a pull-up circuit 422, a transmission circuit 423 and a pull-down circuit 424". The implementation methods of the voltage stabilizing circuit 421, the pull-up circuit 422 and the transmission circuit 423 are the same as those in the aforementioned embodiment, and therefore are not repeated here.

[0111] In this embodiment, the pull-down circuit 424' includes transistors T11', T12', and T13'. The first terminal of the transistor T11' is coupled to the control terminals of the transistors T5' and T6'. The second terminal of the transistor T11' is coupled to the low voltage VGL. The first terminal of the transistor T12' is coupled to the high voltage VGH. The second terminal of the transistor T12' is coupled to the control terminal of the transistor T11'. The control terminal of the transistor T12' is coupled to the voltage regulation node NDB'. The first terminal of the transistor T13' is coupled to the second terminal of the transistor T12'. The second terminal of the transistor T13' and the control terminal of the transistor T13' are coupled to the low voltage VGL. The transistor T13' is used to provide an equivalent resistor between the control terminal of the transistor T11' and the low voltage VGL.

[0112] In this embodiment, when the voltage level at the voltage regulation node NDB' is low, transistors T4' and T12' are turned on. Therefore, transistor T4' uses the high voltage VGH to turn off transistors T5' and T6'. At this time, transistor T12' uses the high voltage VGH to turn off transistor T11'. Therefore, no leakage current flows between the control terminals of transistors T5' and T6' and the low voltage VGL.

[0113] When the voltage level at the voltage regulation node NDB' is high, transistors T4' and T12' are turned off. Transistor T13' pulls down the voltage level at the control terminal of transistor T11' to a low level. Transistor T11' is turned on. Therefore, transistor T5' is turned on to transmit the scan signal SN[n]. Transistor T6' is turned on to transmit the light-emission enable signal EM[n]. In this embodiment, transistors T11'-T13' are each exemplified as a P-type transistor, but the present disclosure is not limited thereto.

[0114] Please refer to Figure 10 , Figure 10FIG3 is a schematic diagram of an electronic device according to a third embodiment of the present invention. In this embodiment, the electronic device 40 includes a pixel unit PU, a next-stage driving circuit DCN, and detection circuits 100 and 300. In this embodiment, the detection circuit 100 receives a scan signal SN[n], a reset signal RST[n], and a light-emitting enable signal EM[n] for the driving circuit DC. The detection circuit 100 provides a first detection signal SD1 in a first phase and a second detection signal SD2 in a second phase based on the scan signal SN[n], the reset signal RST[n], and the light-emitting enable signal EM[n]. The detection circuit 100 determines whether to output the light-emitting enable signal EM[n] to the driving circuit DC in the pixel unit PU based on the first detection signal SD1 and the second detection signal SD2. The detection circuit 300 receives the scan signal SN[n] and the light-emitting enable signal EM[n] for the driving circuit DC. The detection circuit 300 provides a drive detection signal SD3 based on the scan signal SN[n] and the light-emitting enable signal EM[n]. The detection circuit 300 outputs the scan signal SN[n] and the light-emitting enable signal EM[n] to the next stage driving circuit DCN according to the driving detection signal SD3. The implementation details of the detection circuit 100 can be found in Figure 1 、 Figure 3 、 Figure 4 、 Figure 5 The implementation details of the detection circuit 300 can be found in Figure 6 、 Figure 7 、 Figure 8 、 Figure 9 Sufficient teaching is obtained from the embodiments of the present invention, so it will not be repeated here.

[0115] In some embodiments, the detection circuit 300 or a portion of the detection circuit 300 may be integrated into the detection circuit 100. In some embodiments, the detection circuit 100 or a portion of the detection circuit 100 may be integrated into the detection circuit 300.

[0116] Based on the above, the present disclosure proposes multiple aspects of an electronic device. The electronic device detects multiple signals to provide at least one detection signal, and determines whether to output a signal to a driver circuit based on the at least one detection signal. Thus, the electronic device of the present disclosure can determine whether the multiple signals are abnormal based on the at least one detection signal, and accordingly stop outputting the multiple signals to the relevant driver circuit.

[0117] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. An electronic device, characterized in that: The electronic device comprises: Detection circuit, including: a programming detection circuit configured to receive a scan signal, a reset signal, and a light-emitting enable signal for a driving circuit, and provide a first detection signal in a first phase according to the scan signal, the reset signal, and the light-emitting enable signal; a light detection circuit configured to receive the scan signal, the reset signal, and the light-enabling signal, and provide a second detection signal in a second phase according to the scan signal, the reset signal, and the light-enabling signal; and The judgment circuit is coupled to the programming detection circuit and the light detection circuit, and is configured to judge whether to output the light-emitting enable signal to the driving circuit according to the first detection signal and the second detection signal.

2. The electronic device according to claim 1, wherein: The driving circuit is a pixel driving circuit arranged in the pixel unit, The first phase is a data input phase for the driver circuit, and The second phase is a light emitting phase for the driving circuit.

3. The electronic device according to claim 1, wherein: The judgment circuit judges whether an abnormality occurs in the first stage and the second stage according to the first detection signal and the second detection signal, and When it is determined that an abnormality occurs in at least one of the first stage and the second stage, the determination circuit stops outputting the light-emitting enable signal to the driving circuit.

4. The electronic device according to claim 3, wherein: When the determination circuit determines that no abnormality occurs in the first stage and the second stage according to the first detection signal and the second detection signal, the determination circuit outputs the light-emitting enable signal to the driving circuit.

5. The electronic device according to claim 1, wherein: The programming detection circuit includes: a first detection transistor, wherein a first terminal of the first detection transistor and a control terminal of the first detection transistor receive the reset signal, wherein a second terminal of the first detection transistor is coupled to a regulated voltage node; and a second detection transistor, wherein a first terminal of the second detection transistor is coupled to the regulated voltage node, a second terminal of the second detection transistor receives the light-emitting enable signal, and a control terminal of the second detection transistor receives the scan signal.

6. The electronic device according to claim 5, wherein: The luminescence detection circuit includes: a third detection transistor, wherein a first terminal of the third detection transistor is coupled to the regulated voltage node, and a control terminal of the third detection transistor receives the scan signal; a fourth detection transistor, wherein a first terminal of the fourth detection transistor is coupled to the regulated voltage node, wherein a control terminal of the fourth detection transistor receives the reset signal; and a fifth detection transistor, wherein a first terminal of the fifth detection transistor is coupled to the second terminal of the third detection transistor and the second terminal of the fourth detection transistor, wherein a second terminal of the fifth detection transistor is coupled to a low gate voltage, and wherein a control terminal of the fifth detection transistor receives the light-emitting enable signal.

7. The electronic device according to claim 5, wherein: The judgment circuit includes: a voltage stabilization circuit coupled to the stabilization node and configured to provide a bias voltage to the stabilization node; a pull-up circuit coupled to the voltage stabilization node; a transmission circuit coupled to the pull-up circuit; and A pull-down circuit coupled to the transmission circuit, wherein the pull-up circuit is disabled in response to the first level of the voltage stabilization node, so that the transmission circuit is turned on by the pull-down circuit and outputs the light-emitting enable signal to the driving circuit, and The pull-up circuit is enabled in response to the second level of the regulated voltage node, so that the transmission circuit is disconnected and stops outputting the light-emitting enable signal to the driving circuit.

8. An electronic device, characterized in that: The electronic device comprises: a next-stage driving circuit; and Detection circuit, including: a driving detection circuit configured to receive a scanning signal and a light-emitting enable signal for the driving circuit, and provide a driving detection signal according to the scanning signal and the light-emitting enable signal; a judgment circuit coupled to the driving detection circuit and configured to judge whether to output the scanning signal and the light-emitting enable signal to the next-stage driving circuit according to the driving detection signal; and The calibration circuit is coupled to the judgment circuit and is configured to calibrate the level of the output of the judgment circuit according to the scanning signal and the light-emitting enable signal.

9. The electronic device according to claim 8, wherein: The driving circuit is a pixel driving circuit provided in the pixel unit, and The next-stage driving circuit is a gate driving circuit.

10. The electronic device according to claim 8, wherein: The judgment circuit judges whether the scanning signal and the light-emitting enable signal are abnormal according to the driving detection signal, and When it is determined that at least one of the scan signal and the light-emitting enable signal is abnormal, the judgment circuit stops outputting the scan signal and the light-emitting enable signal to the next-stage driving circuit, and the correction circuit corrects the output level of the judgment circuit.

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