Memory

Abstract

An embodiment of the present disclosure provides a memory, comprising: bit lines extending along a first direction and word lines extending along a second direction; a read / write control circuit arranged along the first direction and a plurality of storage modules, the storage module comprising: a memory array arranged along the first direction and an amplifier array, the memory array comprising at least one storage cell, the amplifier array comprising at least one amplification unit, each bit line being electrically connected to a first end of a corresponding amplification unit, each word line being electrically connected to a corresponding storage cell; a column selection circuit, the column selection circuit and the read / write control circuit being located on adjacent sides of the plurality of storage modules respectively; m column selection lines extending along the first direction, each column selection line being electrically connected to a control end of an amplification unit arranged along the first direction, m being a positive integer greater than 1; n electrical connection lines extending along a third direction, each electrical connection line being used for electrically connecting the column selection circuit and a corresponding column selection line, n being a positive integer greater than 1, and n ≤ m.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductor technology, and in particular, to a memory. Background Art

[0002] A semiconductor memory is composed of many repeated basic memory cells. Each basic memory cell generally includes a capacitor and a transistor. The gate of the transistor is connected to a word line, the drain is connected to a bit line, and the source is connected to the capacitor. The voltage signal on the word line can control the opening or closing of the transistor, and then read the data information stored in the capacitor through the bit line, or write the data information into the capacitor through the bit line for storage.

[0003] Semiconductor memories can be divided into non-volatile memories and volatile memories. As a volatile memory, Dynamic Random Access Memory (DRAM) has advantages such as high storage density and fast read / write speed, and is widely used in various electronic systems. DRAM can be divided into Double Data Rate (DDR) dynamic random access memory, Graphics Double Data Rate (GDDR) dynamic random access memory, and Low Power Double Data Rate (LPDDR) dynamic random access memory. Summary of the Invention

[0004] Embodiments of the present disclosure provide a memory, which is at least beneficial to providing a more flexible structure to facilitate the optimization of speed, power consumption, chip area, etc.

[0005] According to some embodiments of the present disclosure, a memory is provided, including: a bit line extending along a first direction and a word line extending along a second direction; a read / write control circuit arranged along the first direction and a plurality of storage modules, the storage module including: a memory array arranged along the first direction and an amplifier array, the memory array including at least one memory cell, the amplifier array including at least one amplification unit, each bit line being electrically connected to a first end of a corresponding amplification unit, each word line being electrically connected to a corresponding memory cell; a column selection circuit, the column selection circuit and the read / write control circuit being respectively located on adjacent sides of a plurality of the storage modules; m column selection lines extending along the first direction, each column selection line being electrically connected to a control end of the amplification units arranged along the first direction, m being a positive integer greater than 1; n electrical connection lines extending along a third direction, each electrical connection line being used to electrically connect the column selection circuit and a corresponding column selection line, n being a positive integer greater than 1, and n ≤ m.

[0006] In some embodiments, each of the column selection lines is electrically connected to the control ends of multiple columns of the amplification units arranged along the first direction.

[0007] In some embodiments, the column selection circuit includes multiple column selection units arranged along the first direction, and each of the column selection units is electrically connected to at least two of the column selection lines via the electrical connection lines.

[0008] In some embodiments, each of the column selection units is electrically connected to at least two adjacent column selection lines via the electrical connection lines.

[0009] In some embodiments, each of the column selection units is electrically connected to at least two spaced-apart column selection lines via the electrical connection lines.

[0010] In some embodiments, each of the column selection units is electrically connected to at least two of the column selection lines via the same electrical connection line; or, each of the column selection units is electrically connected to at least two of the column selection lines via different electrical connection lines.

[0011] In some embodiments, the multiple storage modules are divided into at least two module regions arranged along the first direction, and each of the module regions includes several of the storage modules; the column selection circuit includes: at least two column selection modules arranged along the first direction, each of the column selection modules is located on one side of the corresponding module region, the column selection module is electrically connected to the corresponding column selection line via the electrical connection line, and each of the column selection lines is electrically connected to the control end of the amplification unit in the corresponding module region.

[0012] In some embodiments, the column selection circuit is configured such that when the word line corresponding to the module region is enabled, the column selection module corresponding to the module region provides a column selection signal to the corresponding column selection line via the electrical connection line.

[0013] In some embodiments, for the same module region, the number of the electrical connection lines is the same as the number of the column selection lines, and each of the electrical connection lines is electrically connected to one of the column selection lines.

[0014] In some embodiments, for the same module region, the same electrical connection line is electrically connected to at least two of the column selection lines.

[0015] In some embodiments, the column selection module includes at least two column selection units arranged along the first direction, and each of the column selection units is electrically connected to at least two of the column selection lines via the electrical connection line.

[0016] In some embodiments, for the same module region, each column selection unit is electrically connected to at least two of the column selection lines that are adjacent and distributed via the electrical connection.

[0017] In some embodiments, for the same module region, each column selection unit is electrically connected to at least two of the column selection lines that are spaced apart and distributed via the electrical connection line.

[0018] In some embodiments, each column selection unit is electrically connected to at least two of the column selection lines via the same electrical connection line; or, each column selection unit is electrically connected to at least two of the column selection lines via different electrical connection lines.

[0019] In some embodiments, the number of memory modules included in each module region is the same.

[0020] In some embodiments, the number of module regions is 3.

[0021] In some embodiments, the first direction is perpendicular to the third direction; the second direction is the same as the third direction.

[0022] In some embodiments, it further includes: a row decoding circuit, and the row decoding circuit and the column selection circuit are located on the same side of a plurality of the memory modules.

[0023] The technical solutions provided by the embodiments of the present disclosure have the following advantages:

[0024] In the technical solution of the memory provided by the embodiments of the present disclosure, the read / write control circuit and the column selection circuit are respectively located on the adjacent sides of a plurality of memory modules, and the column selection lines extend along the first direction. Each column selection line is electrically connected to the control ends of the amplification units arranged along the first direction, and the column selection circuit and the column selection lines are electrically connected via the electrical connection lines extending along the third direction. Since the column selection circuit and the read / write control circuit are respectively located on the adjacent sides of a plurality of memory modules, the chip design of the memory is more flexible, which is beneficial to optimizing the read / write speed, power consumption, and chip area of the memory. In addition, the column selection circuit, the electrical connection lines, and the column selection lines form a T-shaped (T shape) morphology, which is beneficial to improving the RC delay problem caused by the column selection circuit and the read / write control circuit being located on the same side, and the signal transmission path between the column selection circuit and the memory cells far from the read / write control circuit becomes shorter. Therefore, it is beneficial to improve the read / write speed of the memory cells far from the read / write control circuit, thereby improving the overall performance of the memory. Furthermore, by using the memory provided by the embodiments of the present disclosure, multiple column selection lines in different areas can share the same column selection unit, thereby reducing the circuit complexity of the column selection circuit and saving area.

[0025] In addition, multiple storage modules can be divided into different module regions, and each module region has independent column selection lines. In this way, a column selection signal can be provided only to the column selection lines of the selected module region, which helps to save more power consumption and improve the signal transmission speed. Description of the Drawings

[0026] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplary illustrations do not limit the embodiments. Elements with the same reference numerals in the drawings represent similar elements. Unless otherwise stated, the drawings in the figures do not constitute a scale limitation.

[0027] Figure 1 It is a schematic structural diagram of a memory;

[0028] Figure 2 It is a schematic structural diagram of a memory provided by some embodiments of the present disclosure;

[0029] Figure 3 It is a schematic structural diagram of a memory array in a memory provided by some embodiments of the present disclosure;

[0030] Figure 4 It is a schematic circuit structure diagram of an amplification unit and a storage unit in a memory provided by some embodiments of the present disclosure;

[0031] Figure 5 It is a schematic layout diagram of each data trace in a memory provided by some embodiments of the present disclosure;

[0032] Figures 6 to 12 It is a schematic diagram of several structures of a memory provided by some embodiments of the present disclosure. Detailed Embodiments

[0033] Figure 1 It is a schematic structural diagram of a memory. Refer to Figure 1, the memory includes: a plurality of memory banks (also known as memory bodies) 10, each memory bank 10 includes a number of memory modules, each memory module includes a memory array 11 and a sense amplifier array 12, the memory array 11 includes a plurality of memory cells arranged along the x direction, the sense amplifier array 12 includes a plurality of amplification units arranged along the x direction, the memory cells and the amplification units in the same column form a section. It can be understood that the column is defined as the column along the y direction, and the row is defined as the row along the x direction; a read / write control circuit 14, a column selection circuit (ydec) 13, and a row decoding circuit 15; a plurality of word lines wl extending along the x direction, each word line wl is connected to the memory array 11 of the corresponding row; a plurality of bit lines BL extending along the Y direction, each bit line bl is connected to the memory array 11 of the corresponding column; a local read / write conversion circuit, each local read / write conversion circuit is located on one side of the corresponding sense amplifier array 12; a column selection line csl extending along the y direction, each column selection line csl is connected to the amplification unit in the corresponding column of the sense amplifier array 12; a global data line gdata extending along the y direction, the global data line is electrically connected to the amplification unit and is also electrically connected to the read / write control circuit 14; the row decoding circuit 15 is used to provide a voltage to the word line wl so that the corresponding word line wl is enabled.

[0034] In the above memory, the row decoding circuit 15 is located on one side of each memory bank 10, and the column selection circuit 13 and the read / write control circuit 14 are located on the other side of each memory bank 10. This has certain limitations on the size and shape of the chip, affecting the optimization of chip packaging or manufacturing efficiency. Moreover, the column selection circuit 13 includes a plurality of circuit units, each circuit unit is connected to the corresponding section in the same column through the column selection line csl. Therefore, the position of each circuit unit corresponds to the position of the corresponding section, and the number of circuit units is the same as the number of sections. This is not conducive to saving the chip area and reducing the manufacturing difficulty of the chip.

[0035] In addition, the above memory also has a problem that the RC delay of the column selection circuit 13 driving different memory modules varies greatly. Specifically, the column selection line csl provides a column selection signal. Define the memory module closest to the read / write control circuit 14 as the first memory module, and define the memory module farthest from the read / write control circuit 14 as the second memory module. The difference in the transmission paths of the column selection signal to the first memory module and the second memory module is relatively large, which results in a relatively large time difference for the column selection signal to reach these two memory modules, bringing signal delay problems and affecting the normal operation of the memory.

[0036] To solve the above problems, an embodiment of the present disclosure provides a memory, which layouts the read / write control circuit and the column selection circuit on the adjacent sides of a plurality of memory modules respectively to solve the RC delay problem and make the chip design more flexible.

[0037] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. However, those of ordinary skill in the art can understand that in the embodiments of the present disclosure, many technical details are provided to help readers better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can still be implemented.

[0038] Figure 2 Schematic diagram of the structure of a memory provided by some embodiments of the present disclosure Figure 3 Schematic diagram of the structure of a memory array in a memory provided by some embodiments of the present disclosure Figure 4 Schematic diagram of the circuit structure of an amplification unit and a storage unit in a memory provided by some embodiments of the present disclosure Figure 5 Schematic diagram of the layout of each data trace in a memory provided by some embodiments of the present disclosure Figures 6 to 12 Schematic diagrams of several structures of a memory provided by some embodiments of the present disclosure. It can be understood that the storage unit described here refers to an array unit arranged by a basic storage unit composed of multiple capacitors and transistors.

[0039] Refer to Figure 2 and Figure 3 A memory provided by an embodiment of the present disclosure includes: bit lines BL extending along a first direction Y and word lines WL extending along a second direction X1; read / write control circuits 101 arranged along the first direction Y and multiple storage modules 102. The storage module 102 includes: a memory array 112 arranged along the first direction Y and an amplifier array 122. The memory array 112 includes at least one storage unit 21, and the amplifier array 122 includes at least one amplification unit 22. Each bit line BL is electrically connected to the first end of a corresponding amplification unit 22, and each word line WL is electrically connected to a corresponding storage unit 21; a column selection circuit 103, where the column selection circuit 103 and the read / write control circuit 101 are respectively located on adjacent sides of multiple storage modules 102; m column selection lines CSL extending along the first direction Y, and each column selection line CSL is electrically connected to the control end of an amplification unit 22 arranged along the first direction Y, where m is a positive integer greater than 1; n electrical connection lines CL along a third direction X2, and each electrical connection line CL is used to electrically connect the column selection circuit 103 and a corresponding column selection line CSL, where n is a positive integer greater than 1, and n ≤ m.

[0040] In some embodiments, the column selection circuit and the row decoding circuit of the storage module can be located on the same side, and the read / write control circuit is located on the other side of the storage module. As Figure 2As shown, the column selection circuit 103 and the row decoding circuit 104 of the storage module 102 may be located on the left side of the storage module 102, and the read / write control circuit 101 is located on the lower side of the storage module 102. In some other embodiments, the column selection circuit, the row decoding circuit, and the read / write control circuit may also be located on different sides of the storage module respectively. For example, the column selection circuit may be located on the left side of the storage module, the row decoding circuit may be located on the right side of the storage module, and the read / write control circuit is located on the lower side of the storage module.

[0041] It should be noted that Figure 2 only one bit line BL and one word line WL are schematically shown. In fact, the memory includes multiple bit lines BL and multiple word lines WL. Figure 3 In one memory cell, only one bit line BL and one column selection line CSL are schematically shown. In fact, multiple bit lines BL and multiple column selection lines CSL are connected in one memory cell.

[0042] In the above embodiments, the column selection circuit 103 and the read / write control circuit 101 are located on adjacent sides of multiple storage modules 102 respectively, so that the shape and size of the memory can be adjusted more flexibly, optimizing the production and manufacturing efficiency; moreover, the time difference of the column selection signals transmitted by the same column selection line CSL reaching different amplification units 22 can be shortened, thereby improving the RC delay characteristic, which is beneficial to improving the read / write speed. In addition, with the above memory, different column selection lines CSL have the opportunity to transmit the same column selection signal via the electrical connection line CL, that is, the column selection circuit 103 does not need to design a separate circuit structure for each column selection line CSL, so that the structural complexity of the column selection circuit 103 can be reduced, the size of the column selection circuit 103 can be reduced, and the chip area of the memory can be saved.

[0043] In some embodiments, the memory may be a DRAM memory, such as a DDR (double data rate) 4 DRAM memory or a DDR5 DRAM memory. In some other embodiments, the memory may also be an SRAM (Static Random-Access Memory) memory, a NAND memory, a NOR memory, a FeRAM memory, or a PcRAM memory.

[0044] Reference Figure 3 , Figure 3 For Figure 2Schematic structural diagram of part of the memory array 112. The memory array 112 may include a plurality of memory cells 21 arranged along the second direction X1. The amplifier array 122 may include a plurality of amplification units 22 arranged along the second direction X1. In some embodiments, each amplification unit 22 may be electrically connected to a memory cell 21 in the same memory module 102 to amplify the data read out from the memory cell 21 during a read operation. In other embodiments, the amplification unit 22 may also be electrically connected to a memory cell 21 in an adjacent memory module 102 to amplify the data read out from the memory cell 21 during a read operation. It can be understood that the embodiments of the present disclosure do not make special limitations on the electrical connection correspondence between the memory cells and the amplification units in the memory module, as long as the amplification unit can amplify the data read out from the memory cell.

[0045] In some embodiments, the memory cell 21 may be a DRAM memory cell.

[0046] Reference Figure 4 , Figure 4 is a functional module schematic diagram of the amplification unit 22 and the memory cell 21. The amplification unit 22 is also called the first-stage sense amplifier (FSA, First sense amplifier). The amplification unit 22 has a control terminal, a first terminal, and a second terminal. The control terminal is used to be electrically connected to the column selection line CSL to receive the column selection signal. The first terminal is electrically connected to the bit line BL, and the second terminal is electrically connected to the local data line (Local Data Line) Ldata. The memory cell 21 is electrically connected to the word line WL and the bit line BL. If the word line WL is enabled, the memory cell 21 electrically connected to the word line WL can perform a read operation, and data transmission occurs between the corresponding memory cell 21 and the bit line BL. Specifically, when the control terminal receives the column selection signal, the first terminal and the second terminal are turned on to enable data to be transmitted between the bit line BL and the local data line Ldata.

[0047] The bit line BL is electrically connected to the memory cells 21 arranged along the first direction Y in a plurality of memory arrays 112. The same bit line BL is electrically connected to a column of memory cells 21 arranged along the first direction Y. It can be understood that the bit line BL can be presented in the form of a bus, and the same bit line BL refers to the same bit line bus.

[0048] The word line WL is electrically connected to the memory cells 21 arranged along the second direction X1 in a plurality of memory arrays 112, that is, the same word line WL is electrically connected to a row of memory cells 21 arranged along the second direction X1 in the same memory array 112. It can be understood that the word line WL can be presented in the form of a bus, and the same word line WL refers to the same word line bus.

[0049] The column selection circuit 103 is commonly referred to as the YDEC circuit and is used to provide a column selection signal to the amplification unit 22 to select the amplification unit 22, so that data is transmitted between the bit line BL and the local data line Ldata. The column selection line CSL is electrically connected to the column selection circuit 103 via the electrical connection line CL.

[0050] All the amplification units 22 and the storage units 21 arranged along the first direction Y can be defined as a slice. The number of slices in the memory is the same as the number of storage units 21 in the storage module 102. Each slice includes a storage unit 21 in any memory array. It can be understood that the memory includes multiple slices, and the multiple slices are arranged along the second direction X1, and each slice extends along the first direction Y. Each bit line BL is electrically connected to the storage unit 21 and the amplification unit 22 in the corresponding slice, and each column selection line CSL is electrically connected to the amplification unit 22 in the corresponding slice. The column selection line CSL is used to conduct multiple bit lines BL and the corresponding local data lines Ldata in the same slice. Each slice includes multiple column selection lines CSL, and may also include a conventional column selection line CSL and a redundant column selection line CSL. When the memory operates, one column selection line CSL in each slice will be selected and enabled.

[0051] The electrical connection line CL is used to electrically connect the column selection circuit 103 and the column selection line CSL, so that the column selection signal provided by the column selection circuit 103 is transmitted to the column selection line CSL via the electrical connection line CL. In some embodiments, the third direction X2 may be the same as the second direction X1, that is, the extending direction of the electrical connection line CL may be the same as the extending direction of the word line WL, and the first direction Y may be perpendicular to the third direction X2. In this way, the length of the electrical connection line CL can be made as short as possible, so that the transmission path of the column selection signal is as short as possible, which is beneficial to further improving the read and write performance of the memory.

[0052] The connection node of the electrical connection line CL and the column selection line CSL is defined as point A. For any column selection line CSL, the column selection signal is transmitted into multiple amplification units 22 in the same slice on one side of point A, and the column selection signal is also transmitted into multiple amplification units 22 in the same slice on the other side of point A. In this way, the time difference required for the column selection signal to be transmitted into different amplification units 22 in the same slice is small. In particular, the difference in length between the column selection line CSL from node A to the amplification unit 22 at the head end in the same slice and the column selection line CSL from node A to the amplification unit 22 at the tail end in the same slice is small, so that the time difference required for the column selection signal to be transmitted into the two amplification units 22 at the head end and the tail end in the same slice is small, which is beneficial to improving the RC delay problem of different amplification units 22 in the same slice being enabled.

[0053] In some embodiments, the column selection circuit 103 may be arranged at an intermediate position on one side of the plurality of memory modules 102, which is beneficial to further shorten the time difference required for the column selection signal in all slices to be transmitted to the amplification units 22 at the head end and the tail end, so as to further improve the overall performance of the memory.

[0054] In some embodiments, the memory may further include: local data lines (Local Data Line) (not shown), each local data line extends along the second direction X1, and the same local data line is electrically connected to the second ends of the amplification units 22 in the same amplifier array 122. It can be understood that one amplifier array 122 can be connected to multiple local data lines.

[0055] In some embodiments, the memory may further include complementary bit lines, and the signal phase of each complementary bit line is opposite to that of the bit line BL. Correspondingly, the memory may further include: local complementary data lines, and the signal phase of each local complementary data line is opposite to that of the local data line.

[0056] In some embodiments, the memory may further include: global data lines (Global Data Line) Gdata extending along the first direction Y. The same global data line Gdata can be electrically connected to multiple local data lines. Specifically, the same global data line Gdata can be electrically connected to all local data lines. The global data line Gdata may have a smaller resistance and parasitic capacitance than the local data line. The memory may further include: global complementary data lines Gdata# extending along the first direction Y, and the signal phase of the global complementary data line Gdata# is opposite to that of the global data line Gdata.

[0057] In some embodiments, refer to Figure 3 and Figure 4 and, the memory module 102 may further include: a local read / write conversion circuit (Lrwap) 132, and the local read / write conversion circuit 132 is electrically connected to the second end of the amplification unit 22. Specifically, the local read / write conversion circuit 132 is electrically connected to the second end of the amplification unit 22 through the local data line. The local read / write conversion circuit 132 is used to implement data transmission between the local data line and the global data line. More specifically, the same global data line can be electrically connected to multiple local read / write conversion circuits 132.

[0058] Refer to Figure 3, the local read / write conversion circuit 132 can be arranged on one side of the amplifier array 122, and the local read / write conversion circuit 132 of each storage module 102 is arranged on the same side of the corresponding amplifier array 132. In this way, the length of the global data line Gdata can be saved, which is beneficial to improving the read / write speed. In some other embodiments, the local read / write conversion circuit 132 can be arranged within the amplifier array 122, that is, the local read / write conversion circuit 132 is arranged between any adjacent amplification units 22, and the local read / write conversion circuits 132 of different storage modules 102 are arranged at the same positions in the corresponding amplifier array 122. For example, the local read / write conversion circuit 132 of each storage module 102 is arranged between the fifth amplification unit 22 and the sixth amplification unit 22, or the local read / write conversion circuit 132 of each storage module 102 is arranged between the tenth amplification unit 22 and the eleventh amplification unit 22.

[0059] Referring to Figure 5 , Figure 5 is a layout schematic diagram of each data trace in the memory provided by the embodiments of the present disclosure. It should be noted that Figure 5 only one of each data trace is schematically shown.

[0060] In some embodiments, referring to Figure 2 , the memory may further include: a row decoding circuit 104. The row decoding circuit 104 is electrically connected to the word line WL through a row selection line, and is used to provide a row decoding signal to the word line WL to select the corresponding word line WL, so that the storage unit 21 electrically connected to the word line WL performs read / write operations, or in other words, selects the storage unit 21 electrically connected to the word line WL. Specifically, the row decoding circuit 104 and the column selection circuit 103 may be located on the same side of multiple storage modules 102.

[0061] In some embodiments, the row decoding circuit 104 and the column selection circuit 103 may be on the same layer of the memory. In some other embodiments, the row decoding circuit 104 and the column selection circuit 103 may also be on different layers of the memory. For example, in the semiconductor structure of the memory, the row decoding circuit 104 and the column selection circuit 103 may be formed through the same semiconductor material layer and / or metal layer, or may be formed through different semiconductor material layers and / or metal layers.

[0062] In some embodiments, referring to Figure 2 , each column selection line CSL may be electrically connected to the control ends of multiple columns of amplification units 22 arranged along the first direction Y. That is to say, each column selection line CSL is electrically connected to the control ends of multiple amplification units 22 arranged along the first direction Y in the same area.

[0063] In some embodiments, referring to Figure 6 and Figure 7 ,Figure 6 and Figure 7 are schematic diagrams of different structures of the memory provided by the embodiments of the present disclosure. The column selection circuit 103 may include a plurality of column selection units 113 arranged along the first direction Y, and each column selection unit 113 is electrically connected to at least two column selection lines CSL via an electrical connection line CL. In this way, multiple column selection lines CSL can share the column selection unit 113, and the amplification units 22 connected to the multiple column selection lines CSL can be driven by the same column selection unit 113. Therefore, the circuit complexity of the column decoding circuit 103 can be reduced, and the chip area can be saved.

[0064] Referring to Figure 6 , in some embodiments, each column selection unit 113 may be electrically connected to at least two adjacent column selection lines CSL via an electrical connection line CL. In this way, the same column selection unit 113 can be used to conduct the bit lines BL in adjacent areas, and the amplification units 22 in different areas can share the column selection unit 113, which is beneficial to reducing the number of column selection units 113 and saving the chip area. Among them, each column selection unit 113 may be electrically connected to at least two column selection lines CSL via the same electrical connection line CL, or each column selection unit 113 may also be electrically connected to at least two column selection lines CSL via different electrical connection lines CL.

[0065] Referring to Figure 7 , each column selection unit 113 may also be electrically connected to at least two spaced column selection lines CSL via an electrical connection line CL. In this way, the same column selection unit 113 can be used to enable the amplification units 22 in the spaced areas, which is not only beneficial to reducing the number of decoding units 113 and saving the chip area, but also the spaced column selection lines CSL are electrically connected to the same column selection unit 113, which is beneficial to avoiding the signal interference problem generated between different column selection lines CSL and further improving the read / write performance of the memory. Among them, each column selection unit 113 may be electrically connected to at least two column selection lines CSL via the same electrical connection line CL, or each column selection unit 113 may also be electrically connected to at least two column selection lines CSL via different electrical connection lines CL.

[0066] In some embodiments, referring to the combination of Figure 3 and Figures 8 to 12 , Figures 8 to 12Schematic diagrams of different structures of a memory provided in some embodiments of the present disclosure. A plurality of memory modules 102 can be divided into at least two module regions I arranged along a first direction Y. Each module region I includes a plurality of memory modules 102. The column selection circuit 103 includes: at least two column selection modules 130 arranged along the first direction Y. Each column selection module 130 is electrically connected to a corresponding column selection line CSL via an electrical connection line CL, and each column selection line CSL is electrically connected to the control end of an amplification unit (not shown) within the corresponding module region I. It should be noted that Figures 8 to 12 the amplifier array, memory cells, amplification units, word lines, and bit lines are not shown, and only the memory array is schematically shown as a box. The amplifier array between adjacent memory arrays is not shown. For the arrangement of the amplifier array, memory cells, amplification units, word lines, and bit lines, reference can be made to the corresponding descriptions in the foregoing Figures 2 to 7 description.

[0067] Specifically, the number of memory modules 102 included in each module region I can be the same. In addition, the memory can also be divided into a high-address storage block U and a low-address storage block V. The layouts of the high-address storage block U and the low-address storage block V both include a plurality of memory modules 102.

[0068] Memory cells 21 within different module regions I are connected to different word lines WL. That is to say, there is a situation where the word lines WL within one module region I are enabled while the word lines WL within the remaining module regions I are not enabled. In this situation, since different module regions I have independent column selection lines CSL, it is possible to only select the column selection lines CSL corresponding to the module region I where the enabled word lines WL are located to transmit the column selection signal, while the column selection lines CSL corresponding to the remaining module regions I do not need to transmit the column selection signal. In this way, more power consumption can be saved. And, compared with the scheme where each column selection line is electrically connected to the amplification units of all module regions, each module region I has independent column selection lines CSL. In this way, the length of each column selection line CSL is reduced, which is beneficial to reducing the resistance of the column selection line CSL; and the load on each column selection line CSL is reduced, which is beneficial to reducing heat loss and power consumption. It can be understood that the load includes the amplification units electrically connected to the column selection line CSL.

[0069] As Figure 8 shown, in some embodiments, the number of module regions I can be 2. As Figure 10 shown, in some other embodiments, the number of module regions I can also be 3. It can be understood that the number of module regions I can be reasonably set according to actual situations, and the embodiments of the present disclosure do not limit the number of module regions I.

[0070] In some embodiments, the column selection circuit 103 may be configured such that when the word line WL corresponding to the module region I is enabled, the column selection module 130 corresponding to the module region I provides a column selection signal to the corresponding column selection line CSL via the electrical connection line CL.

[0071] Referring to Figure 8 , Figure 9 and Figure 11 , in some embodiments, for the same module region I, the number of electrical connection lines CL may be the same as the number of column selection lines CSL, and each electrical connection line CL is electrically connected to a column selection line CSL.

[0072] Referring to Figure 10 and Figure 12 , in some embodiments, for the same module region I, the same electrical connection line CL is electrically connected to at least two column selection lines CSL, that is, the number of electrical connection lines CL is less than the number of column selection lines CSL. In this way, different column selection lines CSL can be electrically connected to the same electrical connection line CL, that is, the bit lines BL corresponding to different slices can select the column selection signal via the same type of selection line CSL, so it is beneficial to reduce the circuit complexity of the corresponding column selection circuit 103 and save chip area.

[0073] Referring to Figures 9 to 12 , the column selection module 130 may include at least two column selection units 113 arranged along the first direction Y, and each column selection unit 113 is electrically connected to at least two column selection lines CSL via the electrical connection line CL, that is, the number of electrical connection lines CL is less than the number of column selection lines CSL. In this way, the amplification units in different slices can share the same column selection signal.

[0074] It should be noted that in some other embodiments, each column selection unit may also be connected to a column selection line via independent electrical connection lines.

[0075] In some embodiments, referring to Figure 9 and Figure 10 , for the same module region I, each column selection unit 113 may be electrically connected to at least two adjacent column selection lines CSL via the electrical connection line CL, that is to say, each column selection unit 113 can enable the amplification units in adjacent slices of the same module region I. In this way, the adjacent slices can share the same column selection unit 113, which is beneficial to reducing the number of column selection units 113 and thus saving chip area.

[0076] Among them, referring to Figure 9 , each column selection unit 113 may be electrically connected to at least two adjacent column selection lines CSL via different electrical connection lines CL, where the at least two column selection lines CSL are adjacent to each other. Referring to Figure 10, each column selection unit 113 can also be electrically connected to at least two column selection lines CSL via the same electrical connection line CL, where the at least two column selection lines CSL are distributed adjacently.

[0077] In some embodiments, referring to Figure 11 and Figure 12 , the number of module regions I can be 3. For the same module region I, each column selection unit 113 can be electrically connected to at least two column selection lines CSL that are distributed at intervals via the electrical connection line CL. That is to say, each column selection unit 113 can enable the amplification units in the spaced-apart areas of the same module region I, so as to avoid the problem that the spacing between the column selection lines CSL transmitting the same column selection signal is too close, thereby avoiding the problem of signal crosstalk.

[0078] Among them, referring to Figure 11 , each column selection unit 113 can be electrically connected to at least two column selection lines CSL via different electrical connection lines CL, where the at least two column selection lines CSL are distributed at intervals. Referring to Figure 12 , each column selection unit 113 can also be electrically connected to at least two column selection lines CSL via the same electrical connection line CL, where the at least two column selection lines CSL are distributed at intervals.

[0079] It can be understood that the specific connection method of the column selection unit 113 being electrically connected to the column selection line CSL via the electrical connection line CL can be any combination of the above-mentioned methods, and the embodiments of the present disclosure do not limit the electrical connection combination method of the electrical connection line CL and the column selection line CSL.

[0080] The embodiments of the present disclosure provide a memory with excellent structural performance. The column selection circuit 103 and the row decoding circuit 104 are arranged on the same side of a plurality of memory modules 102, making the chip design of the memory more flexible, conducive to saving chip area, and shortening the time required for the column selection signal to be transmitted to the amplification unit 22 far from the read / write control circuit 101, which is conducive to improving the RC delay problem and enhancing the read / write performance of the memory.

[0081] Those of ordinary skill in the art can understand that the above-mentioned embodiments are specific embodiments for implementing the present disclosure, and in practical applications, various changes can be made to them in form and details without departing from the spirit and scope of the present disclosure. Any person skilled in the art can make their own changes and modifications within the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the scope defined by the claims.

Claims

1. A memory, characterized in that, Comprising: Bit lines extending in a first direction and word lines extending in a second direction; A read / write control circuit arranged in the first direction and a plurality of memory modules, the memory modules including: a memory array and an amplifier array arranged in the first direction, the memory array including at least one memory cell, the amplifier array including a plurality of amplification units, each of the bit lines being electrically connected to a first end of a corresponding one of the amplification units, and each of the word lines being electrically connected to a corresponding one of the memory cells; A column selection circuit, the column selection circuit and the read / write control circuit being located on adjacent sides of a plurality of the memory modules respectively; m column selection lines extending in the first direction, each of the column selection lines being electrically connected to control ends of a plurality of columns of the amplification units arranged in the first direction, where m is a positive integer greater than 1; n electrical connection lines extending in a third direction, each of the electrical connection lines being used to electrically connect the column selection circuit and a corresponding one of the column selection lines, where n is a positive integer greater than 1 and n ≤ m; Wherein, the column selection circuit includes a plurality of column selection units arranged in the first direction, and each of the column selection units is electrically connected to at least two of the column selection lines via the electrical connection lines.

2. The memory according to claim 1, characterized in that, Each of the column selection units is electrically connected to at least two adjacent-distributed column selection lines via the electrical connection lines.

3. The memory according to claim 1, characterized in that, Each of the column selection units is electrically connected to at least two spaced-apart column selection lines via the electrical connection lines.

4. The memory according to claim 1, characterized in that, Each of the column selection units is electrically connected to at least two of the column selection lines via the same electrical connection line; or, each of the column selection units is electrically connected to at least two of the column selection lines via different electrical connection lines.

5. The memory according to claim 1, characterized in that, The plurality of memory modules are divided into at least two module regions arranged in the first direction, and each of the module regions includes a plurality of the memory modules; The column selection circuit includes: At least two column selection modules arranged in the first direction, each of the column selection modules being located on one side of a corresponding one of the module regions, the column selection modules being electrically connected to the corresponding column selection lines via the electrical connection lines, and each of the column selection lines being electrically connected to control ends of the amplification units within the corresponding module region.

6. The memory according to claim 5, characterized in that, The column selection circuit is configured such that when the word line corresponding to the module region is enabled, the column selection module corresponding to the module region provides a column selection signal to the corresponding column selection lines via the electrical connection lines.

7. The memory according to claim 5, characterized in that, For the same module region, the number of the electrical connection lines is the same as the number of the column selection lines, and each of the electrical connection lines is electrically connected to one of the column selection lines.

8. The memory according to claim 5, characterized in that, For the same module region, the same electrical connection line is electrically connected to at least two of the column selection lines.

9. The memory according to claim 5, characterized in that, The column selection module includes at least two column selection units arranged in the first direction, and each of the column selection units is electrically connected to at least two of the column selection lines via the electrical connection lines.

10. The memory according to claim 9, characterized in that, For the same module region, each of the column selection units is electrically connected to at least two adjacent-distributed column selection lines via the electrical connection.

11. The memory according to claim 9, characterized in that, For the same module region, each of the column selection units is electrically connected to at least two of the column selection lines that are spaced apart via the electrical connection lines.

12. The memory according to claim 9, characterized in that, Each of the column selection units is electrically connected to at least two of the column selection lines via the same electrical connection line; or each of the column selection units is electrically connected to at least two of the column selection lines via different electrical connection lines.

13. The memory according to claim 5, characterized in that, The number of the memory modules included in each module region is the same.

14. The memory according to claim 5, characterized in that, The number of the module regions is 3.

15. The memory according to claim 1, characterized in that, The first direction is perpendicular to the third direction; the second direction is the same as the third direction.

16. The memory according to claim 1, characterized in that, Further included is: a row decoding circuit, where the row decoding circuit and the column selection circuit are located on the same side of a plurality of the memory modules.

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