Wafer loading platform

Abstract

The present invention provides a chip carrier, which improves the thermal uniformity of the chip based on the chip carrier in which the first conductive layer and the second conductive layer at different heights are connected via a conductive portion. The chip carrier (10) is constructed as follows: a sub-RF electrode (21) (first conductive layer) and a jumper layer (22) (second conductive layer) are implanted at different heights inside a ceramic substrate (12) having a chip carrier surface (12a), and a conductive portion (30) is provided for electrically connecting the sub-RF electrode (21) and the jumper layer (22). The conductive portion (30) is a horizontally placed coil or a cylindrical body with holes.

Description

Technical Field

[0001] The present invention relates to a wafer loading platform. Background Art

[0002] In the past, there are known wafer carriers for processing wafers. As wafer carriers, there are: ceramic heaters, electrostatic chucks, bases (bases with built-in electrodes for plasma generation), etc. For example, Patent Document 1 discloses: as the wafer carrier, inside a ceramic substrate having a wafer loading surface, a first circular electrode and a second annular electrode having an outer diameter larger than that of the first electrode are implanted in parallel with the wafer loading surface from the side close to the wafer loading surface. The first electrode and the second electrode are electrically connected via a conductive portion. In Patent Document 1, as the conductive portion, examples of using a zigzag metal mesh and an example of placing a coil longitudinally are disclosed.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 2003-163259 Summary of the Invention

[0006] However, when a zigzag metal mesh or a longitudinally placed coil is used as the conductive portion, the conductive path of the conductive portion becomes considerably longer than the distance between the first electrode and the second electrode. This can easily lead to heat generation in the conductive portion, which can adversely affect thermal uniformity across the wafer.

[0007] The present invention has been made to solve the above-mentioned problems, and its main object is to improve the thermal uniformity of a wafer on a wafer placing table in which a first conductive layer and a second conductive layer at different heights are electrically connected via a conductive portion.

[0008] The wafer loading platform of the present invention is composed of:

[0009] A first conductive layer and a second conductive layer are implanted at different heights inside a ceramic base having a wafer placement surface, and a conductive portion is provided for electrically connecting the first conductive layer and the second conductive layer.

[0010] The wafer stage is characterized in that:

[0011] The conducting portion is a coil placed transversely or a cylindrical body with holes.

[0012] In this wafer stage, the conductive portion is a horizontally placed coil or perforated cylindrical body. Therefore, compared to a conductive portion using a zigzag metal mesh or a longitudinally placed coil, the conductive path of the conductive portion is closer to the distance between the first and second conductive layers. This reduces heat generation in the conductive portion, thereby improving thermal uniformity across the wafer. Examples of the perforated cylindrical body include a punched metal cylinder and a metal mesh cylinder.

[0013] In the wafer placement table of the present invention, the material of the ceramic base can enter the internal space of the conductive portion, thereby reducing density variation of the ceramic base and improving strength.

[0014] In the wafer placement table of the present invention, the cross-sectional shape of the conductive portion may be circular or elliptical. Thus, even if a compressive force is applied from above or below the conductive portion during the manufacturing process, the conductive portion can absorb the force.

[0015] In the wafer stage of the present invention, the conductive portion may be a coil, and at least one of the first conductive layer and the second conductive layer may have a hole extending through the thickness thereof. The coil may be inserted into the hole, so that the inner surface of the hole and the side surface of the coil come into contact. This increases the contact area compared to point contact between the coil and the conductive layers, thereby facilitating conductive contact.

[0016] In the wafer stage of the present invention, the second conductive layer may be a linear or rectangular conductive layer intersecting the first conductive layer in a plan view, and the axis of the conductive portion may be a straight line extending along the direction in which the second conductive layer extends. This allows the conductive portion to be relatively long, facilitating electrical continuity between the first and second conductive layers.

[0017] In the wafer stage of the present invention, the second conductive layer may be an annular or fan-shaped conductive layer that overlaps with the first conductive layer when viewed from above, and the axis of the conductive portion may be an arc-shaped circular portion concentric with the second conductive layer. This allows the conductive portion to be relatively long, facilitating electrical continuity between the first and second conductive layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a plan view of the wafer stage 10 .

[0019] Figure 2 yes Figure 1 AA cross-section diagram.

[0020] Figure 3 It is a side view of the conductive portion 30 and its surroundings.

[0021] Figure 4 yes Figure 3B view of .

[0022] Figure 5 It is an explanatory diagram showing the manufacturing process of the wafer stage 10.

[0023] Figure 6 It is an explanatory diagram of an example of use of the wafer stage 10.

[0024] Figure 7 It is a plan view of the wafer stage 110 .

[0025] Figure 8 yes Figure 7 CC cross-section diagram.

[0026] Figure 9 It is a plan view of the conductive portion 130 and its surroundings.

[0027] Figure 10 yes Figure 9 D view of .

[0028] Figure 11 It is an explanatory diagram showing a modified example of the first embodiment.

[0029] Figure 12 It is an explanatory diagram showing a modified example of the first embodiment.

[0030] Figure 13 It is an explanatory diagram showing a modified example of the first embodiment.

[0031] Figure 14 It is an explanatory diagram of the wafer placement table 310.

[0032] Figure 15 It is an explanatory diagram of the wafer placement table 410.

[0033] Figure 16 It is an explanatory diagram of the wafer placement table 510.

[0034] Figure 17 It is an explanatory diagram of the wafer placement table 610.

[0035] Figure 18 It is a three-dimensional diagram of a punched metal cylinder.

[0036] Explanation of symbols

[0037] 10 Wafer loading platform, 12 Ceramic substrate, 12a Wafer loading surface, 12b Back surface, 20 Main RF electrode, 20a Power supply rod, 21 Secondary RF electrode, 21b Hole, 22 Jumper layer, 22a Power supply rod, 22b Hole, 30 Conductive portion, 30a End portion, 30b Wire bundle portion, 31 Coil, 41 First ceramic molded body, 42 Second ceramic molded body, 42a Hole, 43 Third ceramic molded body, 44 Stacked body, 46 Ceramic substrate, 50 Cooling plate, 80 Chamber, 90 Shower head, 110 Wafer loading platform, 112 Ceramic substrate, 112a Wafer loading surface, 112b Back surface, 121 First RF electrode, 121a Power supply rod, 122 Second RF electrode, 130, 230 Conductive portions. DETAILED DESCRIPTION

[0038] [First embodiment]

[0039] Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. Figure 1 is a plan view of the wafer stage 10, Figure 2 yes Figure 1 AA cross-section diagram, Figure 3 is a side view of the conductive portion 30 and its surroundings, Figure 4 yes Figure 3 View B of the wafer stage 10. It should be noted that in this specification, the terms "up" and "down" indicate relative positions, not absolute positions. Therefore, depending on the orientation of the wafer stage 10, "up" and "down" may become "down" and "up," or "left" and "right," or "front" and "back."

[0040] The wafer stage 10 is used for performing CVD, etching, and other processes on wafers using plasma, and is located within a chamber (not shown) used in semiconductor processing. The wafer stage 10 includes a main RF electrode 20, a secondary RF electrode 21, a jumper layer 22, and a conductive portion 30 within a ceramic base 12.

[0041] The ceramic substrate 12 is a disc-shaped plate formed from a ceramic material such as aluminum nitride, silicon carbide, silicon nitride, or aluminum oxide. The ceramic substrate 12 includes a circular wafer placement surface 12a and a back surface 12b opposite the wafer placement surface 12a. Inside the ceramic substrate 12, a circular main RF electrode 20 and an annular sub-RF electrode 21 are arranged concentrically on the same plane. A rectangular jumper layer 22 is provided on a surface of the ceramic substrate 12 that is different from the plane in which the main RF electrode 20 and sub-RF electrode 21 are arranged. The wafer placement surface 12a is formed with a plurality of irregularities (not shown) by embossing. A heat transfer gas (e.g., He gas) is supplied from the back surface 12b through a gas supply path (not shown) between the recessed portion provided in the wafer placement surface 12a and the wafer placed on the wafer placement surface 12a.

[0042] The main RF electrode 20 is a circular plate electrode concentric with the ceramic substrate 12 and is positioned opposite and parallel to the wafer loading surface 12a. Parallel not only includes completely parallel but also includes parallelism within an acceptable range (e.g., tolerance) (the same applies hereinafter). The main RF electrode 20 is composed primarily of Mo, Nb, W, Ta, their carbides, or a high-melting-point composite metal containing two or more of these, and is formed from a metal mesh, perforated metal, or metal plate. The term "primary component" refers to the component with the highest concentration among the components (the same applies hereinafter). To generate plasma in the space above the central region of a wafer loaded on the wafer loading surface 12a, an RF voltage is applied between the main RF electrode 20 and the upper electrode (shower head 90, described below). The main RF electrode 20 is connected to a power supply rod 20a inserted into the back surface 12b of the ceramic substrate 12. The power supply rod 20a is positioned so as not to contact the jumper layer 22.

[0043] The sub-RF electrode 21 is an annular electrode having an outer diameter larger than that of the main RF electrode 20 and being concentric with the ceramic base 12. A gap is provided between the inner periphery of the sub-RF electrode 21 and the outer periphery of the main RF electrode 20. The sub-RF electrode 21 is formed of a metal mesh, punched metal, or metal plate made of the same material as the main RF electrode 20. To generate plasma in the space above the outer periphery of a wafer placed on the wafer placement surface 12a, an RF voltage is applied between the sub-RF electrode 21 and the upper electrode (shower head 90, described later).

[0044] The jumper layer 22 is a rectangular, planar conductive layer extending along the diameter of the ceramic substrate 12. The jumper layer 22 is formed of a metal mesh, punched metal, or metal plate made of the same material as the main RF electrode 20. The jumper layer 22 is connected to a power supply rod 22a inserted into the back surface 12b of the ceramic substrate 12.

[0045] The conductive portion 30 is a component that electrically connects the secondary RF electrode 21 and the jumper layer 22, and is provided at two locations where the secondary RF electrode 21 and the jumper layer 22 overlap when viewed from above. The conductive portion 30 is a coil placed horizontally. A coil placed horizontally means that the axis of the coil is facing the horizontal direction (the same below). The so-called horizontal: in addition to the completely horizontal situation, it also includes the situation where it is horizontal within an allowable range (such as tolerance) (the same below). The conductive portion 30 is configured so that the axis of the coil is linear along the extension direction of the jumper layer 22 (here, the diameter direction of the ceramic substrate 12). The coil is formed of a material mainly composed of Mo, Nb, W, Ta, their carbides, or a high-melting-point composite metal containing two or more of them. The coil can be formed of the same material as the main RF electrode 20, or it can be formed of a different material. The wire diameter of the coil is preferably 0.6 mm or less. As Figure 4As shown, the shape of the coil is elliptical, and the short diameter is consistent with the distance between the secondary RF electrode 21 and the jumper layer 22. The end portion 30a of the coil constituting the conductive portion 30 is located inside the outer diameter of the coil (refer to Figure 4 ).

[0046] Next, use Figure 5 , a manufacturing example of the wafer placement table 10 is described. Figure 5 It is an explanatory diagram showing the manufacturing process of the wafer stage 10.

[0047] First, a first disk-shaped ceramic molded body 41 is made by using ceramic powder with an average particle size of several μm to several tens of μm, and a jumper layer 22 is formed on one surface thereof (see Figure 5 (A)). For example, the first ceramic molded body 41 can be obtained by tape casting. When forming the jumper layer 22, a metal mesh or the like can be placed on the upper surface of the first ceramic molded body 41, or a conductive paste forming the jumper layer 22 can be printed on the upper surface of the first ceramic molded body 41.

[0048] Next, a second ceramic molded body 42 made in the same manner as the first ceramic molded body 41 is placed on the surface of the first ceramic molded body 41 on which the jumper layer 22 is formed, and the two are integrated. Thereafter, a hole 42a that reaches the jumper layer 22 is drilled in the second ceramic molded body 42 at the position where the conductive portion 30 is to be provided (see FIG. Figure 5 (B)).

[0049] Next, place the circular or oval coil 31 transversely in the hole 42a (see Figure 5 (C)). Then, ceramic powder is filled into the gap of the coil 31, and the main RF electrode 20 and the sub-RF electrode 21 are formed on the upper surface of the second ceramic molded body 42 (see Figure 5 (D)).

[0050] Next, a third ceramic compact 43, which is manufactured in the same manner as the first ceramic compact 41, is placed on the upper surface of the second ceramic compact 42 to integrate them, thereby obtaining a laminate 44 (see FIG. Figure 5 (E)).

[0051] Next, the laminate 44 is hot-pressed and fired, whereby the ceramic powder contained in the laminate 44 is sintered to form a disc-shaped ceramic base 46 (see Figure 5(F)). The horizontally placed coil 31 is compressed in the vertical direction during hot pressing, deforming into an elliptical shape to form the conductive portion 30. Since the conductive portion 30 is a compressed elliptical coil, it strongly contacts the secondary RF electrode 21 and the jumper layer 22. The circular ceramic base 46 is then contoured and provided with holes for inserting the power supply rods 20a and 22a. The power supply rod 20a is then bonded to the main RF electrode 20, and the power supply rod 22a is bonded to the jumper layer 22. This completes the wafer stage 10 having the ceramic base 12.

[0052] Next, use Figure 6 , an example of using the wafer stage 10 is described. Figure 6 It is an explanatory diagram of an example of use of the wafer stage 10.

[0053] After attaching a metal cooling plate 50 to the back surface 12b of the ceramic base 12, the wafer stage 10 is placed in the chamber 80. The power rods 20a and 22a are electrically insulated from the cooling plate 50. A shower head 90 is provided in the chamber 80 at a position opposite the wafer stage 10. A disk-shaped wafer W is placed on the wafer placement surface 12a of the wafer stage 10. In this state, the interior of the chamber 80 is set to a predetermined vacuum atmosphere (or reduced pressure atmosphere), and while process gas is supplied from the shower head 90, plasma is generated in the space above the wafer W. Specifically, high-frequency power is supplied to the main RF electrode 20 via the power rod 20a, and high-frequency power is supplied to the sub-RF electrode 21 independently of the main RF electrode 20 via the power rod 22a, the jumper layer 22, and the conductive portion 30, thereby generating plasma. Since different high-frequency powers (e.g., powers of the same frequency but different wattages, powers of the same frequency but different wattages, powers of different frequencies and different wattages, etc.) can be supplied to the main RF electrode 20 and the sub-RF electrode 21, the plasma density on the wafer W placed on the wafer placement surface 12a can be made uniform. This plasma is then used to perform CVD film formation or etching on the wafer W. The temperature of the wafer W can be controlled by adjusting the temperature of the coolant supplied to the coolant passage (not shown) of the cooling plate 50 attached to the back surface of the wafer placement table 10.

[0054] Here, the correspondence between the components of this embodiment and the components of the present invention is clarified: the ceramic base 12 of this embodiment corresponds to the ceramic base of the present invention, the secondary RF electrode 21 corresponds to the first conductive layer, the jumper layer 22 corresponds to the second conductive layer, and the conductive portion 30 corresponds to the conductive portion.

[0055] In the wafer stage 10 described above, the conductive portion 30 is a horizontally placed coil. Therefore, compared to the case where a zigzag metal mesh or a vertically placed coil is used as the conductive portion, the conductive path of the conductive portion 30 is close to the distance between the sub-RF electrode 21 and the jumper layer 22. Specifically, the conductive path of the conductive portion 30 is a substantially semi-elliptical path (see Figure 4 Therefore, it is possible to suppress heat generation in the conductive portion 30, and thus improve thermal uniformity of the wafer.

[0056] Furthermore, since the same ceramic material as that of the ceramic base body 12 enters the internal space of the coil constituting the conduction portion 30 , density variation of the ceramic base body 12 is reduced and strength is improved.

[0057] The conductive portion 30 is formed of an elliptical coil. During the manufacturing process, a compressive force is applied from above and below the horizontally placed circular or elliptical coil. The coil absorbs the force and becomes elliptical.

[0058] Furthermore, the jumper layer 22 is a rectangular conductive layer that intersects the secondary RF electrode 21 in a plan view, and the axis of the coil constituting the conductive portion 30 is a straight line extending along the direction in which the jumper layer 22 extends. Therefore, the length of the coil placed horizontally can be relatively long, making it easier to ensure electrical continuity between the secondary RF electrode 21 and the jumper layer 22.

[0059] [Second embodiment]

[0060] Hereinafter, a second embodiment of the present invention will be described with reference to the drawings. Figure 7 is a plan view of the wafer stage 110. Figure 8 yes Figure 7 CC cross-section diagram, Figure 9 is a plan view of the conductive portion 130 and its surroundings, Figure 10 yes Figure 9 D view of .

[0061] The wafer stage 110 is used for performing CVD, etching, etc. on a wafer using plasma, and is located in a chamber (not shown) used for semiconductor processing. The wafer stage 110 includes a first RF electrode 121, a second RF electrode 122, and a conductive portion 130 within a ceramic base 112.

[0062] The ceramic substrate 112 is a disc-shaped plate formed from a ceramic material such as aluminum nitride, silicon carbide, silicon nitride, or aluminum oxide. The ceramic substrate 112 includes a circular wafer placement surface 112a and a back surface 112b opposite the wafer placement surface 112a. Within the ceramic substrate 112, a first RF electrode 121 and a second RF electrode 122 are sequentially implanted parallel to the wafer placement surface 112a, starting from the side closest to the wafer placement surface 112a. The wafer placement surface 112a is formed with a plurality of irregularities (not shown) through embossing. A heat transfer gas (e.g., He gas) is supplied from the back surface 112b through a gas supply path (not shown) between the recess provided in the wafer placement surface 112a and the wafer placed on the wafer placement surface 112a.

[0063] The first RF electrode 121 is a circular plate electrode concentric with the ceramic substrate 112 and positioned opposite the wafer placement surface 112a. The first RF electrode 121 is primarily composed of Mo, Nb, W, Ta, their carbides, or a high-melting-point composite metal containing two or more of these, and is formed from a metal mesh, perforated metal, or metal plate. To generate plasma in the space above the central region of a wafer placed on the wafer placement surface 112a, an RF voltage is applied between the first RF electrode 121 and an upper electrode (not shown). The first RF electrode 121 is connected to a power supply rod 121a inserted into the back surface 112b of the ceramic substrate 112.

[0064] The second RF electrode 122 is a ring-shaped electrode having a larger outer diameter than the first RF electrode 121 and is concentric with the ceramic base 112. The second RF electrode 122 is formed of a metal mesh, punched metal, or metal plate, the same material as the first RF electrode 121. The second RF electrode 122 is positioned so as to overlap the first RF electrode 121 when viewed from above. To generate plasma in the space above the outer peripheral region of a wafer placed on the wafer placement surface 112a, an RF voltage is applied between the second RF electrode 122 and an upper electrode (not shown).

[0065] The conductive portion 130 is a component that electrically connects the first RF electrode 121 and the second RF electrode 122, and is provided at a plurality of locations in the overlapping portion of the first RF electrode 121 and the second RF electrode 122 when viewed from above. Figure 7 As shown, a plurality of conductive portions 130 (here 8) are provided at equal intervals along the circumference of the wafer carrier 10. The conductive portion 130 is a coil placed horizontally. The conductive portion 130 is arranged so that the axis of the coil is in an arc shape (here, an arc shape that is concentric with the second RF electrode 122). The coil is formed of the same material as the first RF electrode 121. The wire diameter of the coil is preferably less than 0.6 mm. Figure 8As shown, the shape of the coil is elliptical, and the short diameter is consistent with the distance between the first RF electrode 121 and the second RF electrode 122.

[0066] The manufacturing example and the usage example of the wafer stage 110 refer to the manufacturing example and the usage example of the wafer stage 10 , and therefore, their description is omitted here.

[0067] Here, the correspondence between the components of this embodiment and the components of the present invention is clarified. The ceramic base 112 of this embodiment corresponds to the ceramic base of the present invention, the first RF electrode 121 corresponds to the first conductive layer, the second RF electrode 122 corresponds to the second conductive layer, and the conductive portion 130 corresponds to the conductive portion.

[0068] In the wafer stage 110 described above, the conductive portion 130 is a horizontally placed coil. Therefore, compared to a case where a zigzag metal mesh or a vertically placed coil is used as the conductive portion, the conductive path of the conductive portion 130 is close to the distance between the first RF electrode 121 and the second RF electrode 122. Specifically, the conductive path of the conductive portion 130 is a substantially semi-elliptical path (see Figure 10 Therefore, it is possible to suppress heat generation in the conductive portion 130, and thus improve thermal uniformity of the wafer.

[0069] Furthermore, since the same ceramic material as that of the ceramic base 112 enters the internal space of the coil constituting the conductive portion 130 , density variation of the ceramic base 112 is reduced and the strength is improved.

[0070] The coil constituting the conductive portion 130 is an elliptical coil. During the manufacturing process, a compressive force is applied from above and below the horizontally placed circular or elliptical coil. The coil absorbs this force and becomes elliptical.

[0071] Furthermore, the second RF electrode 122 is an annular conductive layer that overlaps with the first RF electrode 121 in a plan view, and the axis of the coil constituting the conductive portion 130 is an arc-shaped circle concentric with the annular second RF electrode 122. Therefore, the length of the coil placed horizontally can be relatively long, making it easier to ensure electrical conduction between the first RF electrode 121 and the second RF electrode 122.

[0072] It should be noted that the present invention is not limited to the above-described embodiment and can be implemented in various forms as long as they fall within the technical scope of the present invention.

[0073] In the first embodiment described above, if Figure 11As shown, a hole 21b extending through the thickness of the sub-RF electrode 21 (the first conductive layer) and a hole 22b extending through the thickness of the jumper layer 22 (the second conductive layer) can be provided. The coil constituting the conductive portion 30 is inserted into these holes 21b and 22b, so that the inner surfaces of the holes 21b and 22b contact the side surfaces of the coil. This increases the contact area compared to a case where the coil constituting the conductive portion 30 makes point contact with the sub-RF electrode 21 and jumper layer 22, making it easier to ensure electrical continuity. It should be noted that the hole can be provided in either the sub-RF electrode 21 or the jumper layer 22. Furthermore, the hole can also be provided in the second embodiment.

[0074] While an elliptical coil is used in the first and second embodiments, a circular coil or a polygonal coil may also be used. When a polygonal coil is used, preferably at least one corner of the polygon is disposed between the first conductive layer and the second conductive layer, and more preferably two or more corners are disposed. Figure 12 This is an example in which a hexagonal coil is used as the conductive portion 230 in the first embodiment. Figure 12 In the embodiment, two corners are arranged between the sub-RF electrode 21 (first conductive layer) and the jumper layer 22 (second conductive layer).

[0075] In the first embodiment, the jumper layer 22 is used. However, it can be Figure 13 In the illustrated embodiment, a wire bundle portion 30 b is used instead of the jumper layer 22 , in which the terminal portion of the coil constituting the conductive portion 30 is stretched in parallel with the surface of the sub-RF electrode 21 .

[0076] In the first embodiment, the annular sub-RF electrode 21 serving as the first conductive layer and the rectangular jumper layer 22 serving as the second conductive layer are connected via the conductive portion 30. In the second embodiment, the circular first RF electrode 121 serving as the first conductive layer and the annular second RF electrode 122 serving as the second conductive layer are connected via the conductive portion 130. However, the shapes of the first and second conductive layers are not particularly limited to those described above, and various shapes may be employed.

[0077] In the first embodiment described above, the first conductive layer is exemplified as an RF electrode and the second conductive layer is a jumper layer, but the present invention is not particularly limited to this. For example, the first conductive layer may be an electrostatic electrode and the second conductive layer may be a jumper layer, or the first conductive layer may be a heater electrode (resistive heating element) and the second conductive layer may be a jumper layer. In addition, in the second embodiment described above, the first and second conductive layers are both RF electrodes, but the present invention is not particularly limited to this. For example, the first and second conductive layers may both be electrostatic electrodes, or both may be heater electrodes.

[0078] In the first embodiment, the ceramic molded body is produced by tape casting, but the present invention is not particularly limited thereto. For example, a ceramic molded body obtained by compacting ceramic powder or a ceramic molded body produced by casting may be used, or a combination thereof may be used.

[0079] In the first and second embodiments, a step for placing a known focus ring can be provided on the outer periphery of the upper surface of the ceramic base 12, 112. The focus ring has the function of stably generating plasma up to the outer periphery of the wafer and protecting the surface of the wafer stage.

[0080] In addition to the first and second embodiments described above, the following are examples of preferred embodiments to which the present invention is applied: Figures 14 to 17 The chip placement platforms 310, 410, 510, and 610 are provided.

[0081] Figure 14 is an explanatory diagram of the wafer loading platform 310. Figure 14 (A) is a plan view, Figure 14 (B) is the EE cross-section diagram, Figure 14 (C)~ Figure 14 (E) is a cross-sectional view of the wafer stage 310 horizontally cut through the first conductive layer 321, the conductive portion 330, and the second conductive layer 322. The wafer stage 310 is a monopolar electrostatic chuck comprising a ceramic base 312 with a wafer placement surface 312a. The ceramic base 312 is a circular plate with a stepped surface 312b provided on the outer periphery of its upper surface. The first conductive layer 321 is a circular electrostatic electrode embedded in the ceramic base 312. A power supply rod 321a is connected to the central lower surface of the first conductive layer 321. The second conductive layer 322 is an annular electrostatic electrode embedded at a different height than the first conductive layer 321. The conductive portion 330 is a horizontally placed coil with a circular (or elliptical) cross section that electrically connects the first conductive layer 321 to the second conductive layer 322. The conductive portion 330 is an annular component formed by endlessly connecting coils and is arranged concentrically with the second conductive layer 322. When direct current is supplied to the power supply rod 321 a of the wafer stage 310 , a direct current voltage is simultaneously applied to the first conductive layer 321 and the second conductive layer 322 .

[0082] Figure 15 is an explanatory diagram of the wafer placement table 410. Figure 15 (A) is a plan view, Figure 15 (B) is the FF cross-sectional view, Figure 15 (C)~ Figure 15(E) is a cross-sectional view of the wafer carrier 410 when cut horizontally through the first conductive layers 421 and 423, the conductive portions 430 and 432, and the second conductive layers 422 and 424. The wafer carrier 410 is a bipolar electrostatic chuck having a ceramic base 412 with a wafer placement surface 412a. The ceramic base 412 is in the shape of a circular plate, with a stepped surface 412b provided on the outer periphery of the upper surface. The first conductive layers 421 and 423 are semicircular (fan-shaped) electrostatic electrodes separately implanted in the ceramic base 412. A power supply rod 421a is connected to the lower surface of the first conductive layer 421, and a power supply rod 423a is connected to the lower surface of the first conductive layer 423. The second conductive layers 422 and 424 are semicircular (fan-shaped) electrostatic electrodes separately implanted at different heights from the first conductive layers 421 and 423. Conductive section 430 is a horizontally positioned coil that electrically connects first conductive layer 421 and second conductive layer 422. Conductive section 432 is a horizontally positioned coil that electrically connects first conductive layer 423 and second conductive layer 424. Conductive sections 430 and 432 are coils with circular (or elliptical) cross-sections and arc-shaped axes, and are positioned concentrically with second conductive layers 422 and 424. Connecting the positive electrode to power supply rod 421a and the negative electrode to power supply rod 423a on wafer stage 410 creates positive electrodes for first conductive layer 421 and second conductive layer 422, while creating negative electrodes for first conductive layer 423 and second conductive layer 424.

[0083] Figure 16 is an explanatory diagram of the wafer loading platform 510. Figure 16 (A) is a plan view, Figure 16 (B) is the GG cross-section diagram, Figure 16 (C)~ Figure 16(E) is a cross-sectional view of the wafer stage 510, cut horizontally through the comb-tooth electrodes 521 and 523, the conductive portion 530, and the conductive layer 522. The wafer stage 510 is a bipolar electrostatic chuck comprising a ceramic base 512 with a wafer placement surface 512a. The ceramic base 512 is disk-shaped, with a stepped surface 512b provided on the outer periphery of its upper surface. The bipolar comb-tooth electrodes 521 and 523 are a pair of electrostatic electrodes separately implanted in the ceramic base 512. A power supply rod 521a is connected to the lower surface of the comb-tooth electrode 521, and a power supply rod 523a is connected to the lower surface of the comb-tooth electrode 523. The conductive layer 522 is a ring-shaped electrostatic electrode implanted at a different height than the comb-tooth electrodes 521 and 523. The conductive portion 530 is a horizontally positioned coil that electrically connects the comb-tooth electrode 521 (first conductive layer) and the conductive layer 522 (second conductive layer). Conductive portion 530 is a coil with a circular (or elliptical) cross section and an arc-shaped axis, and is arranged concentrically with conductive layer 522. When the positive electrode is connected to power supply rod 521a of wafer stage 510 and the negative electrode is connected to power supply rod 523a, comb-tooth electrode 521 and conductive layer 522 become the positive electrode, while comb-tooth electrode 523 becomes the negative electrode.

[0084] Figure 17 is an explanatory diagram of the wafer loading platform 610. Figure 17 (A) is a plan view, Figure 17 (B) is the HH cross-sectional view, Figure 17 (C)~ Figure 17 (E) is a cross-sectional view of the wafer carrier 610 when cut horizontally through the upper conductive layers 621 and 623, the conductive portions 630 and 632, and the lower conductive layer 622. The wafer carrier 610 is a bipolar electrostatic chuck having a ceramic base 612 with a wafer placement surface 612a. The ceramic base 612 is in the shape of a circular plate, with a stepped surface 612b provided on the outer periphery of the upper surface. The upper conductive layers 621 and 623 are electrostatic electrodes separately implanted in the ceramic base 612. The upper conductive layer 621 is annular, and the upper conductive layer 623 is circular. A power supply rod 623a is connected to the lower surface of the circular upper conductive layer 623. The lower conductive layer 622 is an annular electrostatic electrode implanted at a different height from the upper conductive layers 621 and 623, and a power supply rod 622a is connected to the lower surface. Two conductive sections 630 and 632 are horizontally positioned coils that electrically connect the annular upper conductive layer 621 (first conductive layer) to the circular lower conductive layer 622 (second conductive layer). Conductive section 630 is a coil with a circular (or elliptical) cross-section and an arc-shaped axis, and is positioned concentrically with lower conductive layer 622. Connecting the positive electrode to power supply rod 622a on wafer stage 610 and the negative electrode to power supply rod 623a creates a positive electrode for upper and lower conductive layers 621 and 622, while upper conductive layer 623 becomes a negative electrode.

[0085] The first and second embodiments described above, Figures 14 to 17 In the embodiment shown, a coil placed horizontally is used as the conducting portion. However, a cylindrical body with holes placed horizontally may be used as the conducting portion. The cylindrical body with holes is constituted by providing holes on the side of the conductive cylindrical body. Examples of the cylindrical body with holes include: a punched metal cylindrical body (see Figure 18 ), metal mesh cylindrical body, etc. For the perforated cylindrical body, the material of the ceramic matrix can enter the interior through the hole on the side. As the material of the perforated cylindrical body, as with the coil, materials with Mo, Nb, W, Ta, their carbides, or high-melting-point composite metals containing two or more of these as the main component can be used. Even when a horizontally placed perforated cylindrical body is used instead of a horizontally placed coil, the same effect as when using a coil is obtained.

Claims

1. A wafer loading platform, wherein: A first conductive layer and a second conductive layer are implanted at different heights inside a ceramic base having a wafer placement surface, and a conductive portion is provided for electrically connecting the first conductive layer and the second conductive layer. The wafer stage is characterized in that: The conducting part is a coil placed horizontally or a cylindrical body with holes. The second conductive layer is a ring-shaped or fan-shaped conductive layer that overlaps with the first conductive layer when viewed from above. The axis of the conductive portion is in an arc shape that is concentric with the second conductive layer.

2. The wafer stage according to claim 1, wherein: The material of the ceramic base enters the inner space of the conducting portion.

3. The wafer stage according to claim 1, wherein: The cross-section of the conducting portion is circular or elliptical.

4. The wafer stage according to claim 2, wherein: The cross-section of the conducting portion is circular or elliptical.

5. The wafer placement table according to any one of claims 1 to 4, wherein: The conducting part is a coil, At least one of the first conductive layer and the second conductive layer has a hole penetrating in a thickness direction, and the coil enters the hole so that an inner surface of the hole and a side surface of the coil come into contact with each other.

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