Method for manufacturing semiconductor memory device and semiconductor memory device

Abstract

Embodiments of the present invention provide a manufacturing method of a semiconductor storage device capable of reducing a gap formed between a step-down portion and a step-up portion facing each other in a region where a contact is arranged, and a semiconductor storage device. The manufacturing method of the semiconductor storage device of one embodiment includes a first resist forming step, a first stage forming step, a second resist forming step, and a second stage forming step. In the first resist forming step, a first resist layer is formed on an upper surface of a laminate, the first resist layer being formed with a first opening pattern exposing a part of the upper surface of the laminate. In the first stage forming step, a lower side region of a first stage portion that is one of the step-down portion and the step-up portion and an upper side region of a second stage portion that is the other of the step-down portion and the step-up portion are simultaneously formed by etching processing through the first opening pattern. In the second resist forming step, a second resist layer is formed on the upper surface of the laminate, the second resist layer being formed with a second opening pattern exposing a part of an intermediate bottom that is a lowermost step of the first stage portion and the second stage portion formed by the first stage forming step and the lower side region of the first stage portion. In the second stage forming step, an upper side region of the first stage portion and a lower side region of the second stage portion are simultaneously formed by etching processing through the second opening pattern.

Description

[0001] Reference to relevant applications

[0002] This application claims priority to Japanese Patent Application No. 2021-202457 (filed on December 14, 2021), which is the basic application. This application incorporates the entire contents of the basic application by reference. Technical Field

[0003] The present invention relates to a method for manufacturing a semiconductor memory device and a semiconductor memory device. Background Technology

[0004] As a semiconductor memory device, a three-dimensional stacked memory is utilized, in which multiple memory cells are arranged in a three-dimensional shape on a stack formed by alternating layers of conductive and insulating layers. In this type of three-dimensional stacked memory, the stack is sometimes formed in a stepped shape to increase the number of contacts that can extract charge from the memory cells. In particular, there are cases where a step-down portion and a step-up portion are formed facing each other in a specific direction. In this case, the gap formed between the step-down portion and the step-up portion becomes an area where contacts cannot be placed, so it is ideal to minimize this gap as much as possible. However, conventional manufacturing methods have not been able to sufficiently minimize this gap. Summary of the Invention

[0005] The objective of this invention is to provide a method for manufacturing a semiconductor memory device and a semiconductor memory device that can reduce the gap formed between the descending and ascending portions facing each other in the area where the contact elements are disposed.

[0006] According to one embodiment, a method for manufacturing a semiconductor memory device is provided. The semiconductor memory device has a de-leveling portion and a leveling portion formed on a multilayer body formed by stacking multiple unit layers comprising groups of conductive and insulating layers. The de-leveling portion is a portion of the unit layer that is de-leveled in a first direction. The leveling portion is a portion of the unit layer that is leveled in the first direction and faces the de-leveling portion. The manufacturing method includes a first resist forming step, a first stage forming step, a second resist forming step, and a second stage forming step. In the first resist forming step, a first resist layer is formed on the upper surface of the multilayer body, and the first resist layer has a first opening pattern that exposes a portion of the upper surface of the multilayer body. In the first stage forming step, an etch process performed through the first opening pattern simultaneously forms a lower region of a first stage portion, which is one of the de-leveling portion and the leveling portion, and an upper region of a second stage portion, which is the other of the de-leveling portion and the leveling portion. In the second resist formation step, a second resist layer is formed on the upper surface of the laminate. This second resist layer has a second opening pattern that exposes a portion of the middle bottom of the lowest level of the first stage portion and the second stage portion formed in the first stage formation step, as well as the lower side region of the first stage portion. In the second stage formation step, the upper side region of the first stage portion and the lower side region of the second stage portion are simultaneously formed by etching through the second opening pattern. Attached Figure Description

[0007] Figure 1 This is a top view showing an example of the overall configuration of a semiconductor memory device according to an embodiment.

[0008] Figure 2 This is a perspective view illustrating an example of the construction of a storage cell array according to an implementation method.

[0009] Figure 3 This is a perspective view showing an example of the structure of the descending and ascending parts in the embodiment.

[0010] Figure 4 This illustrates an example of the structure of mutually opposing descending and ascending portions in an embodiment. Figure 3 Sectional view of AA.

[0011] Figure 5 This is a flowchart illustrating an example of the steps in a method for manufacturing a semiconductor memory device according to an embodiment.

[0012] Figure 6 This is a cross-sectional view showing an example of the stacked body state in the first resist formation step of the embodiment.

[0013] Figure 7 This is a top view showing an example of the stacked body state in the first resist formation step of the embodiment.

[0014] Figure 8 This is a cross-sectional view showing an example of the state of the laminate in the first stage formation step of the implementation method.

[0015] Figure 9 This is a top view showing an example of the stack state in the first stage formation step of the implementation method.

[0016] Figure 10 This is a cross-sectional view showing an example of the stacked body state in the second resist formation step of the embodiment.

[0017] Figure 11 This is a top view showing an example of the stacked state during the second resist formation step.

[0018] Figure 12 This is a cross-sectional view showing an example of the laminated body state in the second stage formation step of the embodiment.

[0019] Figure 13 This is a top view showing an example of the stacked body state in the second stage formation step of the implementation method.

[0020] Figure 14 This is a cross-sectional view showing an example of the stacked body state in the first resist formation step of a variation example.

[0021] Figure 15 This is a cross-sectional view showing an example of the state of the laminate in the first stage of the formation step of the variation example.

[0022] Figure 16 This is a cross-sectional view showing an example of the stacked body state in the second resist formation step of a variation example.

[0023] Figure 17 This is a cross-sectional view showing an example of the state of the laminate in the second stage of the formation step of the variation example. Detailed Implementation

[0024] Hereinafter, with reference to the accompanying drawings, a semiconductor memory device according to embodiments and a method for manufacturing the same will be described in detail. However, this invention is not limited to these embodiments. Furthermore, the cross-sectional views, etc., of the semiconductor memory devices used in the following embodiments are schematic diagrams, and the relationship between layer thickness and width, the ratio of the thickness of each layer, etc., may sometimes differ from actual conditions.

[0025] Figure 1 This is a top view showing an example of the overall configuration of the semiconductor memory device 1 according to the embodiment. Figure 1 In the diagram, the X direction (an example of the first direction) corresponds to a right-to-left direction on the paper, the Y direction corresponds to an upward direction on the paper, and the Z direction corresponds to a direction from the inside of the paper towards the front. In other figures, the X, Y, and Z directions correspond to... Figure 1 The X, Y, and Z directions.

[0026] like Figure 1 As shown, the semiconductor memory device 1 of this embodiment is configured by arranging a plurality of cells 2 (eight in this embodiment) on a substrate S. Each of the plurality of cells 2 includes a memory cell array 11, a down-order section 12, and an up-order section 13.

[0027] The memory cell array 11 is a portion in which multiple memory cells are arranged in a three-dimensional manner inside a stacked body formed by stacking multiple unit layers containing groups of conductive layers and insulating layers along the Z direction.

[0028] The reduction section 12 and the elevation section 13 are portions configured with multiple contacts capable of outputting the charge of each memory cell to the outside. The reduction section 12 is a stepped portion formed by reducing the order of multiple unit layers of the laminate in the X direction. The elevation section 13 is a stepped portion formed by raising the order of multiple unit layers of the laminate in the X direction.

[0029] A gap 14 containing an insulating layer is formed between two adjacent cells 2, thus electrically isolating the two adjacent cells 2. Therefore, each cell 2 constitutes a separate independent storage region. That is, the semiconductor storage device 1 of this embodiment has eight independent storage regions on a single substrate S.

[0030] Figure 2 This is a perspective view showing an example of the construction of the storage cell array 11 in the embodiment. Figure 2 In the text, the insulating layer that forms part of the laminate LB is omitted.

[0031] On a substrate S, a source line SL containing a conductive layer is provided. On the source line SL, a plurality of pillars P containing silicon oxide or the like are provided, extending in the Z direction. Each pillar P has a channel layer containing polysilicon or the like and a memory layer formed by stacking multiple insulating layers on its side surface. The insulating layer on the side surface of the pillar P has, for example, a configuration formed by stacking a magnetic tunneling insulating film, a charge accumulation film, and a barrier insulating film from the channel layer side. In addition, on the source line SL, a stacked body LB is provided, formed by alternately stacking multiple unit layers with interlayer insulating layers in between. Each unit layer contains a conductive layer containing tungsten or the like and an insulating layer containing silicon oxide or the like. Each pillar P extends through the stacked body LB.

[0032] In the stacked layer LB, the bottommost conductive layer functions as the source-side select gate line (SGS), and the topmost conductive layer functions as the drain-side select gate line (SGD). The select gate line SGD is divided by each pillar P arranged along the X direction. Multiple conductive layers sandwiched between the select gate lines SGS and SGD function as multiple word lines (WL). The number of stacked word lines WL (the number of memory cells MS) can be arbitrarily set according to the application. Insulating layers are disposed between the select gate lines SGS, SGD, and the multiple word lines WL, but... Figure 2 The diagram is omitted. Each column P is connected to a bit line BL on the stacked volume LB. Each bit line BL is connected to multiple columns P arranged along the Y direction.

[0033] According to the configuration, memory cells MC arranged along the height direction of each pillar P are disposed at the connection points between each pillar P and each word line WL. Source-side selection transistors STS and drain-side selection transistors STD are disposed at the connection points between each pillar P and the select gate lines SGS and SGD, respectively. A memory string MS is constituted by the selection transistors STS arranged along the height direction of one pillar P, the multiple memory cells MC, and the selection transistors STD. According to this configuration, a memory cell array 11 is formed by arranging multiple memory cells MC in a three-dimensional (matrix) configuration inside the stacked layer LB.

[0034] Multiple word lines WL are led out to the outside of the memory cell array 11 and connected to contacts in the following de-order section 12 and de-order section 13.

[0035] Figure 3 This is a perspective view showing an example of the structure of the descending part 12 and the ascending part 13 in the embodiment. Figure 3 In the middle, an illustrative example is shown with Figure 1 The portion corresponding to region 20, indicated by a single-point chain line, schematically represents a portion of two adjacent units 2A and 2B (an example of the first and second units) along the X direction.

[0036] like Figure 3 As shown, a step-down section 12 is provided on the left side (positive side in the X direction) of the memory cell array 11, and a step-up section 13 is provided on the right side (negative side in the X direction) of the memory cell array 11. The step-down section 12 has multiple step sections 25 that are reduced in the X direction, and the step-up section 13 has multiple step sections 26 that are increased in the X direction. A contact member 15 is provided on each step section 25 and each step section 26. The step-down section 12 of one cell 2A and the step-up section 13 of another cell 2B are arranged facing each other with a gap 14 between them.

[0037] Figure 4 This illustrates an example of the structure of the mutually opposing descending portion 12 and ascending portion 13 in an embodiment. Figure 3 AA sectional view. For example... Figure 4 As shown, the laminated body LB constituting the step-down section 12 and the step-up section 13 is constructed by laminating multiple unit layers L, each containing a word line WL and an insulating layer IS. Each step portion 25 of the step-down section 12 and each step portion 26 of the step-up section 13 is composed of an insulating layer IS. The contact member 15 penetrates the insulating layer IS of the step portions 25 and 26 and is connected to the word line WL directly below the insulating layer IS.

[0038] In this embodiment, the step-reducing section 12 is divided into a lower region 12L and an upper region 12H. In this embodiment, the step-reducing section 12 as a whole comprises a 15-step stepped section 25, the lower region 12L comprises a 7-step stepped section 25, and the upper region 12H comprises an 8-step stepped section 25. Similarly, in this embodiment, the step-increasing section 13 is divided into a lower region 13L and an upper region 13H. In this embodiment, the step-increasing section 13 as a whole comprises a 15-step stepped section 26, the lower region 13L comprises a 7-step stepped section 26, and the upper region 13H comprises an 8-step stepped section 26. Furthermore, the number of steps in the stepped sections 25 of the step-reducing section 12, the number of steps in the stepped sections 26 of the step-increasing section 13, the number of steps in the lower regions 12L and 13L, and the number of steps in the upper regions 12H and 13H are not limited to the above-described cases and can be arbitrarily set according to the application, etc.

[0039] The gap 14 formed between the descending section 12 and the ascending section 13, that is, between two adjacent units 2A and 2B along the X direction, is made of the insulating layer IS of the bottom layer of the laminate LB. The gap 14 is an area where the contact 15 cannot be arranged, so it is desirable to minimize the gap 14 as much as possible.

[0040] The manufacturing method of semiconductor memory device 1 will be described below. The manufacturing method of this embodiment is to simultaneously form a de-leveling portion 12 of one unit 2A and a leveling portion 13 of another unit 2B by photolithography on the stacked material LB. The manufacturing method includes a method for reducing the gap 14.

[0041] Figure 5 This is a flowchart illustrating an example of the steps in the manufacturing method of the semiconductor memory device 1 according to an embodiment. In the manufacturing method of this embodiment, firstly, a first resist forming step (S101) is performed to form a first resist layer, wherein the first resist layer has a first opening pattern formed on the upper surface of the laminate LB.

[0042] Figure 6 This is a cross-sectional view showing an example of the state of the laminate LB in the first resist formation step of the embodiment. Figure 7 This is a top view showing an example of the state of the laminate LB in the first resist formation step of the embodiment.

[0043] In the first resist formation step, such as Figure 6 and Figure 7 As shown, a first resist layer R1 is formed on the upper surface of the laminate LB, and the first resist layer R1 has a first opening pattern P1 that exposes a portion of the upper surface of the laminate LB (the uppermost insulating layer IS). Figure 6 and Figure 7 The diagram shows the gap forming region 30, which represents the area where the gap 14 will eventually form. The first opening pattern P1 is formed such that its width in the X direction is wider than the width of the gap forming region 30 in the X direction. In this embodiment, the first opening pattern P1 is formed as a portion including the gap forming region 30 and the region where the step 13 will eventually form (the region further to the left of the gap forming region 30 in the diagram). Furthermore, Figure 7 The image shows the contact configuration position 31, which indicates the final position for the contact 15 to be configured.

[0044] After that, as Figure 5 As shown, the first stage forming step (S102) is performed. In the first stage forming step, the lower region 12L of the de-leveling portion 12 of unit 2A (an example of the first stage portion) and the upper region 13H of the ascending portion 13 of another unit 2B (an example of the second stage portion) are simultaneously formed by etching through the first opening pattern P1.

[0045] Figure 8 This is a cross-sectional view showing an example of the state of the laminate LB in the first stage formation step of the embodiment. Figure 9 This is a top view showing an example of the state of the laminate LB in the first stage formation step of the implementation method.

[0046] The first stage formation steps can be performed, for example, by repeatedly performing an etching process and an ashing process a specific number of times. The etching process involves etching the exposed portion of the laminate LB through the first opening pattern P1, and the ashing process involves ashing the first resist layer R1 by expanding the width of the first opening pattern P1 in the X direction. That is, firstly, through... Figure 6 and Figure 7 The first opening pattern P1 in the state shown is etched, and then the width of the first opening pattern P1 in the X direction is increased by an amount equivalent to one order of the reduced-order portion 12 and the increased-order portion 13 through an ashing process. Then, the first opening pattern P1, which has been increased by this ashing process, is etched again. This etching and ashing process is repeated by an amount corresponding to the order of the lower region 12L of the reduced-order portion 12 and the upper region 13H of the increased-order portion 13. Thus, the lower region 12L of the reduced-order portion 12 and the upper region 13H of the increased-order portion 13 are simultaneously formed in the laminate LB. At the end of the first stage formation step, as shown... Figure 8 and Figure 9As shown, the structure is formed with a lower region 12L of the descending section 12 and an upper region 13H of the ascending section 13. At this time, the width of the intermediate bottom 35 formed between the lower region 12L of the descending section 12 and the upper region 13H of the ascending section 13 in the X direction is... Figure 6 and Figure 7 The width of the initial first opening pattern P1 shown is approximately the same as that of the gap forming region 30 in the X direction.

[0047] After that, as Figure 5 As shown, the second resist formation step (S103) is performed. In the second resist formation step, a second resist layer having a second opening pattern is formed on the upper surface of the laminate LB.

[0048] Figure 10 This is a cross-sectional view showing an example of the state of the laminate LB in the second resist formation step of the embodiment. Figure 11 This is a top view showing an example of the state of the laminate LB in the second resist formation step.

[0049] Figure 10 and Figure 11 The image shows a state in which a second resist layer R2 with a second opening pattern P2 is formed on the upper surface of the laminate LB. At this time, the second opening pattern P2 is formed such that a portion of the intermediate bottom 35 formed by the first stage forming step and the lower side region 12L of the step reduction portion 12 are exposed.

[0050] After that, as Figure 5 As shown, the second-stage forming step (S104) is performed. In the second-stage forming step, the upper region 12H of the downgraded portion 12 of unit 2A and the lower region 13L of the upgraded portion 13 of another unit 2B are simultaneously formed by etching through the second opening pattern P2.

[0051] Figure 12 This is a cross-sectional view showing an example of the state of the laminate LB in the second stage formation step of the embodiment. Figure 13 This is a top view showing an example of the state of the laminate LB in the second stage formation step of the implementation method.

[0052] The second-stage formation step is similar to the first-stage formation step, for example, it can be performed by repeatedly performing etching and ashing processes a specific number of times. The etching process involves etching the exposed portion of the laminate LB through the second opening pattern P2, and the ashing process involves ashing the second resist layer R2 by expanding the width of the second opening pattern P2 in the X direction. That is, firstly, through... Figure 10 and Figure 11The second opening pattern P2, as shown, is etched. Then, an ashing process is performed to expand the width of the second opening pattern P2 in the X direction by an amount equivalent to one order of the reduced-order portion 12 and the increased-order portion 13. Afterward, the expanded second opening pattern P2 is etched again. This etching and ashing process is repeated by an amount corresponding to the order of the upper region 12H of the reduced-order portion 12 and the lower region 13L of the increased-order portion 13. Thus, the upper region 12H of the reduced-order portion 12 and the lower region 13L of the increased-order portion 13 are simultaneously formed in the laminate LB. At the end of the second stage forming step, as... Figure 12 and Figure 13 As shown, the process is complete with both the reduced-order portion 12 and the increased-order portion 13, and a second resist layer R2 remains on the upper region 13H of the increased-order portion 13. At this time, the width of the gap 14 formed between the reduced-order portion 12 and the increased-order portion 13 in the X direction is smaller than the initial width of the first opening pattern P1 formed in the first resist layer R1 in the X direction (see reference). Figure 6 and Figure 7 ), and the initial X-direction width of the second opening pattern P2 formed in the second resist layer R2 (refer to Figure 10 and Figure 11 ).

[0053] After that, as Figure 5 As shown, a stripping step (S105) is performed. In the stripping step, the second resist layer R2 remaining in the laminate LB is removed. Thus, the formation of the descending portion 12 and the ascending portion 13 facing each other is completed.

[0054] Subsequently, by performing specific steps such as setting the contact 15 at the contact configuration position 31 and forming the wiring pattern of the substrate S, a product is manufactured. Figure 1 The illustrated semiconductor memory device 1.

[0055] As described above, according to this embodiment, when forming the opposing descending portion 12 and ascending portion 13, the lower region 12L of the descending portion 12 and the upper region 13H of the ascending portion 13 are formed simultaneously first, and then the upper region 12H of the descending portion 12 and the lower region 13L of the ascending portion 13 are formed simultaneously. According to this manufacturing method, compared to the case where the entire order of the descending portion 12 and the entire order of the ascending portion 13 are formed simultaneously, the gap 14 ultimately formed between the descending portion 12 and the ascending portion 13 can be reduced, thereby enabling the overall miniaturization of the semiconductor memory device 1.

[0056] Furthermore, according to the manufacturing method of this embodiment, when the order of the down-order portion 12 and the order of the up-order portion 13 are each set to 3 or more, the width of the gap 14 in the X direction can be set to 1 μm or less.

[0057] Furthermore, in the above description, an example was shown where the lower region 12L of the reduced-order portion 12 and the upper region 13H of the increased-order portion 13 were formed first, followed by the formation of the upper region 12H of the reduced-order portion 12 and the lower region 13L of the increased-order portion 13. However, the formation order can also be reversed. That is, the upper region 12H of the reduced-order portion 12 and the lower region 13L of the increased-order portion 13 can also be formed first, followed by the formation of the lower region 12L of the reduced-order portion 12 and the upper region 13H of the increased-order portion 13.

[0058] Figure 14 This is a cross-sectional view showing an example of the state of the laminate LB in the first resist formation step of a variation example. Figure 15 This is a cross-sectional view showing an example of the state of the laminate LB in the first stage formation step of a variation example. Figure 16 This is a cross-sectional view showing an example of the state of the laminate LB in the second resist formation step of a variation example. Figure 17 This is a cross-sectional view showing an example of the state of the laminate LB in the second stage formation step of the variation example.

[0059] In this variation example, such as Figure 14 As shown, the first opening pattern P1 of the first resist layer R1 is formed as a part of the region including the gap forming region 30 and the region where the step reduction portion 12 is finally formed (in the figure, the region to the right of the gap forming region 30). Additionally, as... Figure 15 As shown, at the end of the first stage forming step, the upper region 12H of the descending section 12 and the lower region 13L of the ascending section 13 are formed. Additionally, as... Figure 16 As shown, the second opening pattern P2 of the second resist layer R2 is formed to expose a portion of the intermediate bottom 35 formed by the first stage formation step and the lower side region 13L of the stepped portion 13. Additionally, as... Figure 17 As shown, at the end of the second stage formation step, the second resist layer R2 remains on the upper region 12H of the reduced-step portion 12. This variation can achieve the same effect as the described embodiment.

[0060] Furthermore, while the above description illustrates the case where the degraded portion 12 and the ascending portion 13, which are facing each other, are electrically disconnected, the relationship between the degraded portion 12 and the ascending portion 13 is not limited to this. For example, the degraded portion and the ascending portion, which are facing each other, can also be electrically connected. The manufacturing method of this embodiment can be widely applied to cases where degraded portions and ascending portions are formed in a positional relationship facing each other.

[0061] Several embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms and can be omitted, substituted, and modified in various ways without departing from the spirit of the invention. These embodiments or variations thereof are included in the scope or spirit of the invention and are included in the scope of the invention as set forth in the claims and their equivalents.

[0062] [Explanation of Symbols]

[0063] 1 conductor storage device

[0064] Units 2, 2A, 2B

[0065] 11-cell array

[0066] 12 descending sections

[0067] 12H upper region

[0068] 2L lower area

[0069] 13th Rank

[0070] 13H upper area

[0071] 13L lower area

[0072] 14 gaps

[0073] 15 contacts

[0074] Steps 25 and 26

[0075] 30 gap formation area

[0076] 31 Contact configuration position

[0077] 35 Middle Bottom

[0078] IS insulation layer

[0079] L-unit layer

[0080] LB stack

[0081] MS storage unit

[0082] P1 First Opening Pattern

[0083] P2 Second Opening Pattern

[0084] R1 First Anti-corrosion Layer

[0085] R2 Second Anti-corrosion Layer

[0086] S substrate

[0087] WL lettering.

Claims

1. A method for manufacturing a semiconductor memory device, wherein the semiconductor memory device comprises, on a multilayer body formed by stacking multiple unit layers comprising groups of conductive layers and insulating layers, a reduced-order portion of the unit layers in a first direction, an increased-order portion of the unit layers in the first direction facing the reduced-order portion, a first unit and a second unit adjacent to each other and separating the reduced-order portion and the increased-order portion, wherein the first unit is connected to the reduced-order portion and the second unit is connected to the increased-order portion, the method for manufacturing the semiconductor memory device comprising the following steps: In the first resist forming step, a first resist layer is formed on the upper surface of the laminate, the first resist layer having a first opening pattern that exposes a portion of the upper surface of the laminate; The first stage forming step involves simultaneously forming a lower region of the first stage portion, which is one of the reduced-order portion and the increased-order portion, and an upper region of the second stage portion, which is the other of the reduced-order portion and the increased-order portion, through etching via the first opening pattern, without simultaneously forming the upper region of the first stage portion. In the second resist forming step, a second resist layer is formed on the upper surface of the laminate, the second resist layer having a second opening pattern that exposes a portion of the middle bottom of the lowest step of the first stage portion and the second stage portion formed by the first stage forming step, and the lower side region of the first stage portion. The second-stage forming step involves simultaneously forming the upper region of the first-stage portion and the lower region of the second-stage portion through etching via the second opening pattern, and forming a gap between the descending portion and the ascending portion; and A contact for taking out charge from the first unit is arranged on the stepped portion of the descending section, and a contact for taking out charge from the second unit is arranged on the stepped portion of the ascending section.

2. The method for manufacturing a semiconductor memory device according to claim 1, wherein... The width of the first opening pattern in the first direction and the width of the second opening pattern in the first direction are wider than the width of the gap in the first direction formed between the descending part and the ascending part after the second stage forming step.

3. The method for manufacturing a semiconductor memory device according to claim 2, wherein... The width of the gap in the first direction is less than 1 μm.

4. The method for manufacturing a semiconductor memory device according to claim 1, wherein... The width of the first direction of the middle bottom is wider than the width of the first direction of the gap formed between the descending part and the ascending part after the second stage forming step.

5. The method for manufacturing a semiconductor memory device according to claim 4, wherein... The width of the gap in the first direction is less than 1 μm.

6. The method for manufacturing a semiconductor memory device according to claim 1, wherein... The reduced-order section is electrically disconnected from the increased-order section.

7. The method for manufacturing a semiconductor memory device according to claim 1, wherein... The first unit and the second unit are electrically disconnected. The conductive layer of the reduced-order section is connected to the memory cell included in the first unit. The conductive layer of the upgraded section is connected to the memory cell contained in the second unit.

8. The method for manufacturing a semiconductor memory device according to claim 1 or 2, wherein The gap is formed by the insulating layer of the bottommost layer of the laminate.

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