Semiconductor device and method of forming the same

Abstract

A semiconductor device and a method of forming the same are provided. The semiconductor device includes a semiconductor substrate of a first conductivity type; a region of a second conductivity type within the semiconductor substrate; a drift region in the region of the second conductivity type, the drift region having the first conductivity type; a source structure disposed apart from a first side of the drift region; a first gate structure on a top surface of the region of the second conductivity type and corresponding to the first side of the drift region; a drain structure disposed apart from a second side of the drift region; a second gate structure on the region of the second conductivity type and adjacent to the second side of the drift region, the second gate structure being between the drift region and the drain structure; and a conductive layer on the second gate structure, and an insulating layer between the second gate structure and the conductive layer. The conductive layer electrically connects the drain structure, the second gate structure, and the drift region. The device has significantly reduced on-resistance and can effectively reduce the required device area.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor device and a method of forming the same, and more particularly to a semiconductor device with electron as the conduction carrier and a method of forming the same. BACKGROUND

[0002] In the field of integrated circuit (IC), semiconductor devices such as vertical diffused metal oxide semiconductor (VDMOS) devices and laterally diffused metal oxide semiconductor (LDMOS) devices have been widely used in various fields such as display driver IC components, power supplies, power management, communications, automotive electronics or industrial control. For example, in power management IC, LDMOS devices are not only used for output buffer power MOS, but also used for high voltage circuit logic operation (HV circuit logic operation), and how to make LDMOS devices suitable for different application requirements is an important issue. For LDMOS devices, breakdown voltage (such as drain-source breakdown voltage, BVdss) and on-resistance (such as specific on-resistance) are two important key parameters for evaluating LDMOS devices, and thus become the performance indicators of LDMOS devices.

[0003] LDMOS devices can be divided into N-type LDMOS devices and P-type LDMOS devices according to the conduction type. N-type LDMOS devices are often used in product design because they have a better figure of merit (FOM), which is a function of drain-source breakdown voltage and on-resistance. Since P-type LDMOS devices are conducted by hole carriers, the transmission speed is slower than N-type LDMOS devices conducted by electrons, and if applied to product design, the area occupied by P-type LDMOS devices will be larger than that of N-type LDMOS devices to achieve the same electrical performance. For example, in circuit design to achieve the same driving current, the array size of P-type LDMOS devices is about twice that of N-type LDMOS devices. However, the circuit design of P-type LDMOS devices is relatively simple, and some products gradually adopt P-type LDMOS devices.

[0004] Thus, while existing semiconductor devices can cope with their originally intended purposes, there are still problems in the structure of the semiconductor devices that need to be overcome. How to improve the semiconductor devices to enhance the electrical properties of the semiconductor devices and to significantly reduce the size of the process chip is an important issue for the related industry. SUMMARY

[0005] Some embodiments of the present disclosure disclose a semiconductor device, comprising a semiconductor substrate having a first conductivity type; a second conductivity type region within the semiconductor substrate and extending downward from a top surface of the semiconductor substrate; a drift region within the second conductivity type region and extending downward from a top surface of the second conductivity type region, wherein the drift region has a first side and a second side, and the drift region has the first conductivity type; a source structure disposed apart from the first side of the drift region, the source structure comprising a first top doped region having the second conductivity type and a second top doped region having the first conductivity type, and the second top doped region is adjacent to the first top doped region; a first gate structure disposed corresponding to the first side of the drift region and on the top surface of the second conductivity type region; a drain structure disposed apart from the second side of the drift region opposite to the first side, the drain structure comprising a third top doped region having the first conductivity type and a fourth top doped region having the second conductivity type, and the fourth top doped region is adjacent to the third top doped region; a second gate structure on the top surface of the second conductivity type region, the second gate structure is adjacent to the second side of the drift region and between the drift region and the drain structure; and a conductive layer on the second gate structure, and an insulating layer between the second gate structure and the conductive layer. In some embodiments, the conductive layer electrically connects the drain structure, the second gate structure, and the drift region.

[0006] According to some embodiments of the present application, a method for forming a semiconductor device is disclosed, including providing a semiconductor substrate having a first conductivity type, the semiconductor substrate including a second conductivity type region, and the second conductivity type region extending downward from a top surface of the semiconductor substrate; forming a drift region in the second conductivity type region, the drift region having the first conductivity type and formed with a first side and a second side, and the drift region extending downward from the top surface of the second conductivity type region; forming a source structure and a drain structure disposed apart from the first side and the second side opposite to the first side of the drift region, respectively, the source structure including a first top doped region having the second conductivity type and a second top doped region having the first conductivity type, and the second top doped region adjacent to the first top doped region, the drain structure including a third top doped region having the first conductivity type and a fourth top doped region having the second conductivity type, and the fourth top doped region adjacent to the third top doped region; forming a first gate structure on the top surface of the second conductivity type region, and the first gate structure corresponding to the first side of the drift region; forming a second gate structure on the top surface of the second conductivity type region, and the second gate structure adjacent to the second side of the drift region and between the drift region and the drain structure; forming a conductive layer on the second gate structure, wherein an insulating layer is on the second gate structure, and the conductive layer is on the insulating layer; and electrically connecting the conductive layer to the drain structure, the second gate structure, and the drift region.

[0007] The semiconductor device of the embodiments of the present application has the benefits of significantly reduced on-resistance and effectively reduced device area, thereby improving the electrical performance of the semiconductor device and achieving miniaturization. In addition, the manufacturing method of the semiconductor device of the embodiments is compatible with the steps of the existing process, and the manufacturing method is simple and does not significantly increase the manufacturing cost. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figures 1-3 FIG. 1 shows a schematic diagram of forming a semiconductor device according to some embodiments of the present application, wherein Figure 1 is a top view of an intermediate stage of a semiconductor device according to some embodiments of the present application; Figure 2 is a cross-sectional schematic diagram of an intermediate stage of a semiconductor device according to some embodiments of the present application, and Figure 2 is drawn according to the position of the cross-sectional line A-A' in Figure 1 ; Figure 3 FIG. 4 shows a cross-sectional schematic diagram of an intermediate stage of a semiconductor device according to some embodiments of the present application, wherein Figure 3 is a cross-sectional schematic diagram of forming a conductive component after the process of Figure 2 ;

[0009] Figure 4is a cross-sectional schematic view corresponding to an intermediate stage of another semiconductor structure according to some embodiments of the invention.

[0010] Figure 5 is a cross-sectional schematic view corresponding to an intermediate stage of yet another semiconductor structure according to some embodiments of the invention.

[0011] Figure 6A illustrates a top view of an active region and a drift region of a semiconductor device according to some embodiments of the invention. Figure 5

[0012] Figure 6B illustrates a top view of another active region and a drift region of a semiconductor device according to some embodiments of the invention. Figure 5

[0013] Figure 7 is a schematic view of a circuit structure of a semiconductor structure according to some embodiments of the invention.

[0014] Reference Signs

[0015] 100: semiconductor substrate

[0016] 110: region of second conductivity type

[0017] 120: drift region

[0018] 121, 122, 123, 124, 125: drift portions

[0019] 120-1: first side of drift region

[0020] 120-2: second side of drift region

[0021] 130: field oxide layer

[0022] 1321: first field oxide portion

[0023] 1322: second field oxide portion

[0024] 141: first gate structure

[0025] 1412: first gate dielectric layer

[0026] 1414: first gate electrode

[0027] 142: second gate structure

[0028] 1422: second gate dielectric layer

[0029] 1424: second gate electrode

[0030] 151: first well (second conductivity type base region)​​

[0031] 152: second well (first conductivity type base region)

[0032] 161: first top doped region

[0033] 162: second top doped region

[0034] 163: third top doped region

[0035] 164: fourth top doped region

[0036] 165: first conductivity type heavily doped region

[0037] 166: first conductivity type heavily doped region

[0038] 166s: sidewall of first conductivity type heavily doped region

[0039] 170: insulating layer

[0040] 172: conductive layer

[0041] 180: dielectric layer

[0042] 100a, 110a, 180a: top surface

[0043] 190-1: first conductive part

[0044] 191M: first conductive line

[0045] 191V: first conductive hole

[0046] 192V: second conductive hole

[0047] 193V: third conductive hole

[0048] 190-2: second conductive part

[0049] 192M: second conductive line

[0050] 194V: fourth conductive hole

[0051] 195V: fifth conductive hole

[0052] 196V: sixth conductive hole

[0053] 190-3: third conductive part

[0054] 193M: third conductive line

[0055] 197V: seventh conductive hole

[0056] 198V: eighth conductive hole

[0057] R1: first resistance value

[0058] R2: second resistance value

[0059] A-A': cross-sectional line

[0060] D1: first direction

[0061] D2: second direction

[0062] D3: third direction

[0063] A A : active region

[0064] E1, E2: side edge of active region

[0065] d1, d2: distance

[0066] Vg, Vs, Vd, Vp: voltage

[0067] Id: current

[0068] S: source terminal

[0069] D: drain terminal DETAILED DESCRIPTION

[0070] The following description is directed to semiconductor devices and methods of forming the same. It should be appreciated that the following description provides different embodiments or examples for implementing the various aspects of the application. The following description is not intended to limit the scope of the application, but rather is intended to provide a description of different embodiments of the application. In the following description, numerous specific details are discussed in order to provide a thorough understanding of the application. However, it will be apparent to one skilled in the art that the application can be practiced without these specific details. In other instances, well-known methods have not been described in detail in order to avoid unnecessarily obscuring the application. In addition, it is to be appreciated that the use of certain terms to describe the application is not intended to limit the scope of the application. For example, the terms "first," "second," or the like are used herein to describe various elements, however, the elements should not be limited by these terms. The terms "and" and "or" used in a phrase such as A and / or B or A and / or C are intended to mean A, B, C, A and B, A and C, B and A, B and C, A, B and C, unless otherwise indicated by the context. Also, the use of the "inclusive OR" (e.g., A or B) means A, or B, or both A and B. Moreover, phrases such as A and / or B and / or C include any combination of A, B, and / or C. The use of the "inclusive OR" (e.g., A or B) means A, or B, or both A and B. In addition, the use of letter symbols in the claims to represent different elements should not be construed as limiting of the application. For example, the use of the letter "C" in a claim should not be construed as limiting the scope of the application to only those embodiments in which the element represented by the letter "C" is present. Rather, the letter "C" is merely used to simplify the claims and is intended to encompass all embodiments of the application.

[0071] Some variations of the embodiments are described below. Like reference numerals can be used to describe similar elements throughout various embodiments and illustrations. It is to be understood that additional operations can be provided before, during, and after the methods, and some operations described can be removed, or implemented in a different order. In addition, some of the operations can be implemented by different components or a different number of components.

[0072] Moreover, spatially relative terms, such as "beneath", "below", "lower", "above", "upper", and the like, can be used herein for ease of description to describe one element or component's relationship to another element(s) or component(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0073] As used herein, the terms "about" and "approximately" generally mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%. A given amount that is about a given amount means that the given amount can be implied without a specific recitation of "about" or "approximately."

[0074] Embodiments of semiconductor devices are disclosed, and embodiments can be included in integrated circuits (ICs) such as microprocessors, memory elements, power elements, and / or other elements, such as can be used in output buffer power Metal-Oxide-Semiconductor (MOS) devices, or in high voltage logic circuits. Integrated circuits to which embodiments can be applied can also include different passive and active microelectronic elements such as thin-film resistors, other types of capacitors such as metal-insulator-metal capacitors (MIMCAPs), inductors, diodes, MOS field-effect transistors, complementary MOS transistors, bipolar junction transistors (BJTs), lateral diffused MOS transistors, high power MOS transistors, or other types of transistors. Those skilled in the art will appreciate that semiconductor devices of embodiments can also be used in integrated circuits that include other types of semiconductor elements.

[0075] Some embodiments of the present application provide a semiconductor device and a method of forming the same. The semiconductor device includes a structure design of a P-type laterally diffused metal oxide semiconductor (PLDMOS) element and an N-type laterally diffused metal oxide semiconductor (NLDMOS) element embedded in each other. The semiconductor device can maintain or only slightly increase the size of the original device. Furthermore, the semiconductor device uses the PLDMOS element as a trigger source of the NLDMOS element, and uses electrons as the conduction carriers for internal carrier conduction. Therefore, the semiconductor device behaves like a NLDMOS element, and has the advantages of a NLDMOS element, such as a significant reduction in the on-resistance (Ron) of the semiconductor device and a significant reduction in the required device area. Therefore, the semiconductor device can have the advantages of both a PLDMOS element and a NLDMOS element, such as a simple circuit design, a small circuit layout area, and good electrical properties, thereby improving the electrical properties of the semiconductor device and achieving miniaturization.

[0076] Reference is made to Figures 1-3 , which illustrates a schematic diagram of forming a semiconductor device according to some embodiments of the present application. Figure 1 For some embodiments of the present application, a top view of an intermediate stage of a semiconductor device. Figure 2 , Figure 3 For some embodiments of the present application, a cross-sectional schematic diagram of an intermediate stage of a semiconductor device, wherein Figure 2 , Figure 3 Corresponding to the position of the cross-sectional line A-A' in Figure 1 .

[0077] Please refer to Figure 1 and Figure 2According to some embodiments, a semiconductor substrate 100 is provided, and a second conductive type region 110 is formed in or over the semiconductor substrate 100, wherein the second conductive type region 110 extends downward from a top surface 100a of the semiconductor substrate 100. The semiconductor substrate 100 can be an elemental semiconductor substrate including silicon, germanium; or a compound semiconductor substrate including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; or an alloy semiconductor substrate including silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP), or a combination thereof.

[0078] In addition, the semiconductor substrate 100 can also be a semiconductor on insulator (SOI) substrate. In some embodiments, the semiconductor substrate 100 can be a lightly doped first conductive type (e.g., P-type) or second conductive type (e.g., N-type) substrate. In this embodiment, the semiconductor substrate 100 has a first conductive type, e.g., P-type, with P-type dopants, e.g., boron (B), inside.

[0079] Subsequently, wells (e.g., drift regions and body regions) or doped regions are formed in the second conductive type region 110, and these wells and doped regions also extend downward from a top surface 110a of the second conductive type region 110; that is, the aforementioned wells and doped regions are located close to the top surface 100a of the semiconductor substrate 100 / the top surface 110a of the second conductive type region 110.

[0080] In some embodiments, the second conductive type region 110 is a second conductive type well region, e.g., an N-type well. In high voltage device applications, the second conductive type region 110 can be a high voltage N-type well. In some embodiments, the second conductive type region 110 can be a second conductive type epitaxy layer, e.g., an N-type epitaxy layer (N-epilayer), disposed on the semiconductor substrate 100.

[0081] In some embodiments, the method for forming the above-described N-type well (second conductivity type region 110) includes an ion implantation process and a thermal drive-in process. For example, when an N-type well is used as the second conductivity type region 110, its doping concentration is approximately 1 x 10⁻⁶. 15 atoms / cm 3 Up to approximately 5x10 17 atoms / cm 3 Within the range.

[0082] In some other embodiments, the aforementioned N-type epitaxial layer (second conductivity type region 110) may be formed by metal-organic chemical vapor deposition (MOCVD), plasma-enhanced chemical vapor deposition (PECVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), liquid phase epitaxy (LPE), chloride-vapor phase epitaxy (Cl-VPE), other similar processes, or combinations of the aforementioned processes.

[0083] In some embodiments, refer to Figure 1 , Figure 2 A drift region 120 having a first conductivity type is formed in the second conductivity type region 110, and the drift region 120 extends downward from the top surface 110a of the second conductivity type region 110. The first conductivity type is, for example, P-type, and the drift region 120 contains a P-type dopant, such as boron. In some embodiments, the drift region 120 may include a plurality of drift portions, such as... Figure 1 The drift portions 121, 122, 123, 124, and 125 are shown. These drift portions 121-125 extend from the top surface 110a of the second conductivity type region 110 along a first direction D1 (e.g., the X direction) and are spaced apart from each other in a second direction D2 (e.g., the Y direction), wherein the second direction D2 is different from the first direction D1, for example, the second direction D2 is perpendicular to the first direction D1. In some embodiments, these drift portions 121-125 are arranged parallel to each other. Furthermore, several drift portions 121-125 extend downward from the top surface 110a of the second conductivity type region 110 along a third direction D3.

[0084] In some embodiments, the injection dose of the drift region 120 is, for example, approximately 3.0 x 10⁻⁶.12 atoms / cm 2 Up to approximately 5.0x10 13 atoms / cm 2 Within the range. Furthermore, in some embodiments, the doping concentration of the dopant in the drift region 120 is, for example, approximately 1 x 10⁻⁶. 16 atoms / cm 3 Up to approximately 5x10 18 atoms / cm 3 Within the range of ).

[0085] In some embodiments, refer to Figure 2 An isolation structure, such as a field oxide layer 130, can be formed at the top surface 110a of the second conductivity type region 110. The field oxide layer 130 may contain one or more spaced-apart field oxide portions. Figure 2 In the example, a field oxide section is illustrated to illustrate the field oxide layer 130, but this disclosure is not limited thereto. Furthermore, refer to... Figure 1 , Figure 2 In some embodiments, the field oxide layer 130 ( Figure 2 The two ends of ) can respectively correspond to the active region A. A The two side edges E1 and E2 ( Figure 1 ).

[0086] In some embodiments, refer to Figure 2 The field oxide layer 130 is located above the drift region 120. Figure 1 The field oxide layer 130 is omitted from the drawing to clearly show the distribution of the plurality of drift portions 121-125 included in the drift region 120 in some embodiments of the semiconductor device, and the drift region 120 relative to other components (e.g., active region A). A And the configuration of the gate structure.

[0087] In some embodiments, the field oxide layer 130 (or field oxide portion) is made of silicon oxide and may be a local oxidation of silicon (LOCOS) isolation portion formed by thermal oxidation. In some other embodiments, the field oxide layer 130 (or field oxide portion) may be a shallow trench isolation (STI) structure formed by etching and deposition processes.

[0088] Next, according to some embodiments, after forming the field oxide layer 130, electrodes for related components are fabricated, such as forming a gate structure.

[0089] Refer to Figure 1 ,Figure 2 In some embodiments, a first gate structure 141 and a second gate structure 142 are formed on the top surface 110a of the second conductivity type region 110. In some embodiments, the first gate structure 141 and the second gate structure 142 correspond to the first side 120-1 and the second side 120-2 of the drift region 120, respectively, where the first side 120-1 is opposite to the second side 120-2.

[0090] In this example, the first gate structure 141 and the second gate structure 142 are adjacent to the first side 120-1 and the second side 120-2 of the drift region 120, respectively, and the first gate structure 141 covers a portion of the drift region 120. That is, the first gate structure 141 and the drift region 120 each has at least a portion overlapping. Further, the second gate structure 142 is disposed apart from the second side 120-2 of the drift region 120, as shown. Figure 1 、 Figure 2

[0091] In some embodiments, the first gate structure 141 includes a first gate dielectric layer 1412 and a first gate electrode 1414 disposed on the first gate dielectric layer 1412; and the second gate structure 142 includes a second gate dielectric layer 1422 and a second gate electrode 1424 disposed on the second gate dielectric layer 1422. The method of fabricating the gate structures can be, for example, by sequentially blanket depositing a dielectric material layer (to form the first gate dielectric layer 1412 and the second gate dielectric layer 1422) and a conductive material layer (to form the first gate electrode 1414 and the second gate electrode 1424) on the second conductivity type region 110, and then patterning the dielectric material layer and the conductive material layer by photolithography and etching processes, respectively, to form the first gate structure 141 and the second gate structure 142 including the gate dielectric layer and the gate electrode.

[0092] ​The material of the dielectric material layer (i.e., the material of the first gate dielectric layer 1412 and the second gate dielectric layer 1422) can include silicon oxide, silicon nitride, silicon oxynitride, high-k dielectric material, a combination thereof, or other suitable dielectric material. In some embodiments, the dielectric material layer can be formed by chemical vapor deposition (CVD) or spin coating. The material of the conductive material layer (i.e., the material of the first gate electrode 1414 and the second gate electrode 1424) can be amorphous silicon, polysilicon, one or more metals, metal nitride, conductive metal oxide, a combination thereof, or other suitable conductive material. The material of the conductive material layer can be formed by chemical vapor deposition (CVD), sputtering, resistive heating evaporation, electron beam evaporation, or other suitable deposition method. In one embodiment, polysilicon is used as the material of the first gate electrode 1414 and the second gate electrode 1424. In addition, the first gate structure 141 and the second gate structure 142 can include insulating spacers (not shown) disposed on the sidewalls of the gate structures.

[0093] Further, in some embodiments, the semiconductor device further includes a first well 151 and a second well 152, which respectively extend downward from the top surface 110a of the second conductivity type region 110. The first well 151 and the second well 152 have opposite conductivity types. According to some embodiments, the first well 151 has the second conductivity type, e.g., N-type, and the second well 152 has the first conductivity type, e.g., P-type. In this example, the first well 151 can also be referred to as a second conductivity type body region 151, e.g., an N-type body region (N-body region), and the second well 152 can also be referred to as a first conductivity type body region 152, e.g., a P-type body region (P-body region).

[0094] In some embodiments, the first well (second conductivity type body region) 151 is disposed at a distance dl from the first side 120-1 of the drift region 120. A portion of the bottom surface of the first gate structure 141, e.g., the bottom surface of the first gate dielectric layer 1412, overlaps with a portion of the underlying second conductivity type body region 151.

[0095] In some embodiments, the second well (first conductivity type body region) 152 is disposed at a distance d2 from the second side 120-2 of the drift region 120, where the distance d2 is greater than the distance dl. A portion of the bottom surface of the second gate structure 142, e.g., the bottom surface of the second gate dielectric layer 1422, overlaps with a portion of the underlying first conductivity type body region 152.

[0096] The formation methods of the first well (or second conductivity type substrate region) 151 and the second well (or first conductivity type substrate region) 152 include, for example, ion implantation and thermal drive-in processes. The semiconductor substrate 100 may be tilted at an appropriate angle for the ion implantation process. In some embodiments, the doping concentration of the first well (or second conductivity type substrate region) 151 and the second well (or first conductivity type substrate region) 152 is greater than the doping concentration of the second conductivity type region 110. In some embodiments, the doping concentration of the second conductivity type substrate region 151 and the first conductivity type substrate region 152 is approximately 5 x 10⁻⁶. 16 atoms / cm 3 Up to approximately 5x10 18 atoms / cm 3 Within the range.

[0097] According to some embodiments, after forming the first well (or second conductivity type substrate region) 151 and the second well (or first conductivity type substrate region) 152, the corresponding top-doped regions of the source and drain of the semiconductor device can be fabricated. According to this embodiment, two top-doped regions of opposite conductivity types (i.e., the first top-doped region 161 and the second top-doped region 162 described below) of the source structure of the semiconductor device are formed in the first well (or second conductivity type substrate region 151), and two top-doped regions of opposite conductivity types (i.e., the third top-doped region 163 and the fourth top-doped region 164 described below) of the drain structure of the semiconductor device are formed in the first conductivity type substrate region 152.

[0098] Reference Figure 1 , Figure 2 In some embodiments, a first top doping region 161 and a second top doping region 162 are formed in a first well (or a second conductivity type substrate region) 151, and the first top doping region 161 and the second top doping region 162 extend downward from the top surface 110a of the second conductivity type region 110. In this example, the first top doping region 161 has a second conductivity type, such as N-type, and the second top doping region 162 has a first conductivity type, such as P-type. The source structure of the embodiment includes the first top doping region 161 and the second top doping region 162.

[0099] Furthermore, according to some embodiments, the second top-doped region 162 is disposed at a distance from the first side 120-1 of the drift region 120, and the second top-doped region 162 is also separated from the sidewall of the second conductivity type substrate region 151 below the first gate structure 141 by a distance, such as... Figure 2 As shown.

[0100] In some embodiments, a third top doping region 163 and a fourth top doping region 164 are formed in the second well (or first conductivity type body region) 152, and the third top doping region 163 and the fourth top doping region 164 extend downward from a top surface 110a of the second conductivity type region 110. In this example, the third top doping region 163 has a first conductivity type, e.g., P-type, and the fourth top doping region 164 has a second conductivity type, e.g., N-type. The drain structure of embodiments includes the third top doping region 163 and the fourth top doping region 164, with the second gate structure 142 located between the drift region 120 and the drain structure.

[0101] Further, according to some embodiments, the fourth top doping region 164 is located apart from the second side 120-2 of the drift region 120, and the fourth top doping region 164 is also located apart from a sidewall of the first conductivity type body region 152 under the second gate structure 142, as shown. Figure 2

[0102] Further, in some embodiments, the above-mentioned top doping regions, e.g., the first top doping region 161, the second top doping region 162, the third top doping region 163, and the fourth top doping region 164, can be formed by ion implantation and thermal drive-in processes, or other suitable processes.

[0103] Although in this example, the first top doping region 161 and the second top doping region 162 are formed in the second conductivity type body region 151 for illustration of embodiments, the present disclosure is not limited thereto. In some other embodiments, e.g., semiconductor devices that are not operated at high voltage, the second conductivity type body region 151 can be omitted if the second conductivity type region 110 has a sufficient doping concentration of the second conductivity type dopants, e.g., N-type dopants.

[0104] According to some embodiments of the present disclosure, the semiconductor device further includes a conductive layer 172, and the conductive layer 172 is electrically connected to the above-mentioned drain structure (including the above-mentioned third top doping region 163 and the fourth top doping region 164), the second gate structure 142, and the drift region 120.

[0105] ​In some embodiments, the drift region 120 has a first resistance (Rl) and the conductive layer 172 comprises doped polysilicon and has a second resistance (R2). In operation, when the gate voltage (Vg) of the first gate structure 141 is 0V, the semiconductor device turns on (electron as the carrier) and current flows from the source structure (comprising the first top doped region 161 and the second top doped region 162) to the drain structure (comprising the third top doped region 163 and the fourth top doped region 164). In some embodiments of the present application, the voltage drop (Vp) of the second gate structure 142 at Vg = 0V of the first gate structure 141 can be adjusted according to the ratio of the first resistance (Rl) of the drift region 120 and the second resistance (R2) of the conductive layer 172 to turn on the semiconductor device. When the gate voltage (Vg) of the first gate structure 141 is equal to the power supply voltage (Vdd), the voltage drop (Vp) of the second gate structure 142 is very low or even zero, and the semiconductor device turns off and no current flows.

[0106] The relative size of the first resistance (Rl) and the second resistance (R2) is not particularly limited. The first resistance (Rl) can be greater than, equal to, or less than the second resistance (R2). As long as the ratio of the first resistance (Rl) and the second resistance (R2) allows the second gate structure 142 to obtain an appropriate voltage drop (Vp) to turn on the semiconductor device when the gate voltage (Vg) of the first gate structure 141 is 0V, the embodiments are applicable. The present application does not limit this.

[0107] In some embodiments, the conductive layer 172 can be formed by depositing an insulating layer 170 on the first gate structure 141 and the second gate structure 142, and this insulating layer 170 can be densified. In some embodiments, the insulating layer 170 covers the top surface 110a of the second conductivity type region 110, the first gate structure 141, and the second gate structure 142. The material of the insulating layer 170 is, for example, tetraethoxysilane (TEOS), or other suitable materials. Then, undoped polysilicon material is formed over the insulating layer 170 and patterned by photolithography and etching processes to form an undoped polysilicon layer. This undoped polysilicon layer, the underlying insulating layer 170, and the second gate structure 142 (its second gate electrode 1424) form a capacitor structure. Subsequently, in some embodiments, a doped portion is formed by ion implantation of the undoped polysilicon layer through a mask. This doped portion can serve as the conductive layer 172 of the semiconductor device in some embodiments. The concentration of ion implantation into the undoped polysilicon layer is such that the applied semiconductor device can achieve the desired second resistance value (R2).

[0108] Furthermore, although the embodiment is illustrated with the conductive layer 172 located directly above the second gate structure 142 as an example, the present invention is not limited thereto. The conductive layer 172 may be located at other positions on the insulating layer 170, such as above the third top doped region 163 or above other components. Electrical connections between the conductive layer 172 and the drain structure, the second gate structure 142, and the drift region 120 can also be achieved through appropriate wire / via configuration and connection.

[0109] Reference Figure 3 According to some embodiments, the semiconductor device further includes forming a first conductivity type heavily doped region 165, such as a P-type heavily doped region, in the drift region 120. The first conductivity type heavily doped region 165 may extend downward from the top surface 110a of the second conductivity type region 110, or be located below the field oxide layer 130. Figure 3 In the example, the first conductivity type heavily doped region 165 is located below the field oxide layer 130.

[0110] Figure 3 The illustration depicts a cross-sectional schematic diagram of an intermediate stage of a semiconductor device according to some embodiments of the present invention, wherein... Figure 3 Continued Figure 2 A cross-sectional schematic diagram of conductive components formed by the process.

[0111] Reference Figure 3According to some embodiments, a dielectric layer 180 is formed over the insulating layer 170 to cover the conductive layer 172, and desired conductive features are formed to complete the electrical connections of the relevant elements in the semiconductor device of the embodiments. In some embodiments, the conductive features are, for example, interconnect structures, which include a plurality of vias in the dielectric layer 180 and the insulating layer 170 and a plurality of conductive lines over the dielectric layer 180.

[0112] In some embodiments, the dielectric layer 180 can be a single layer of dielectric material or a multi-layer structure including two or more layers of dielectric materials. For simplicity of the drawings, a single layer of dielectric material is shown for the dielectric layer 180 to facilitate clear illustration. The dielectric material of the dielectric layer 180 can be, for example, silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric material, or other suitable dielectric material.

[0113] In some embodiments, a plurality of conductive features are formed to complete the electrical connections of the relevant elements in the semiconductor device. Referring to Figure 3 The semiconductor device further includes a first conductive feature 190-1, a second conductive feature 190-2, and a third conductive feature 190-3. In some embodiments, the first conductive feature 190-1 electrically connects the drift region 120, the second gate structure 142, and the conductive layer 172. Specifically, the first conductive feature 190-1 of an embodiment includes a first via 191V, a second via 192V, a third via 193V, and a first conductive line 191M. As shown in Figure 3 the first via 191V of this example extends through the dielectric layer 180, the insulating layer 170, and the field oxide layer 130 and contacts the first conductivity type heavily doped region 165. In some embodiments, the first conductivity type heavily doped region 165 can be formed by implanting the field oxide layer 130 through an additional mask after the first via 191V is formed. The second via 192V of this example extends through the dielectric layer 180 and the insulating layer 170 and connects the second gate structure 142. The third via 193V of this example extends through the dielectric layer 180 and connects the conductive layer 172. Further, the first conductive line 191M of this example is located on the top surface 180a of the dielectric layer 180 and connects the first via 191V, the second via 192V, and the third via 193V.

[0114] In some embodiments, the second conductive portion 190-2 is electrically connected to the conductive layer 172 and the third top-doped region 163. In this example, the second conductive portion 190-2 is further electrically connected to the conductive layer 172, the third top-doped region 163 having a first conductivity type, and the fourth top-doped region 164 having a second conductivity type. Specifically, the second conductive portion 190-2 in the embodiment may include a fourth via 194V, a fifth via 195V, a sixth via 196V, and a second conductive wire 192M. Figure 3 As shown, in this example, the fourth via 194V passes through the dielectric layer 180 and connects to the conductive layer 172. In this example, the fifth via 195V passes through the dielectric layer 180 and the insulating layer 170 and connects to the third top-doped region 163 having a first conductivity type (e.g., P-type). In this example, the sixth via 196V passes through the dielectric layer 180 and the insulating layer 170 and connects to the fourth top-doped region 164 having a second conductivity type (e.g., N-type). Furthermore, in this example, the second conductor 192M is located on the top surface 180a of the dielectric layer 180, and the second conductor 192M connects the fourth via 194V, the fifth via 195V, and the sixth via 196V.

[0115] Furthermore, in some embodiments, the third conductive portion 190-3 is electrically connected to the first top-doped region 161 and the second top-doped region 162. Specifically, the third conductive portion 190-3 includes a seventh via 197V, an eighth via 198V, and a third conductive wire 193M. For example... Figure 3 As shown, in this example, the seventh via 197V passes through the dielectric layer 180 and the insulating layer 170, and connects to the first top-doped region 161 having a second conductivity type (e.g., N-type). In this example, the eighth via 198V passes through the dielectric layer 180 and the insulating layer 170, and connects to the second top-doped region 162 having a first conductivity type (e.g., P-type). Furthermore, in this example, the third conductor 193M is located on the top surface 180a of the dielectric layer 180, and the third conductor 193M connects the seventh via 197V and the eighth via 198V.

[0116] Accordingly, in some embodiments of the present application, the first gate structure 141 in the semiconductor device can be considered as a gate of a P-type laterally diffused metal oxide semiconductor (PLDMOS) element; the first top doped region 161 and the second top doped region 162 can be considered as a source region of the PLDMOS element; the third top doped region 163 having a first conductivity type (e.g. P-type) and the fourth top doped region 164 having a second conductivity type (e.g. N-type) can be considered as a drain region of the PLDMOS element. Further, the second gate structure 142 can be considered as a gate of an N-type laterally diffused metal oxide semiconductor (NLDMOS) element; the fourth top doped region 164 in the first conductivity type substrate region 152 (e.g. P-type substrate region) having the second conductivity type (e.g. N-type) can be considered as a source of the NLDMOS element. Therefore, the semiconductor device according to the embodiments includes an embedded PLDMOS element and an embedded NLDMOS element. Accordingly, the semiconductor device according to the embodiments can maintain the original size of the PLDMOS element with only a slight increase in size.

[0117] Further, the first conductive portion 190-1 according to the embodiments can electrically connect the second gate structure 142 (NLDMOS element) with the conductive layer 172, and also electrically connect the floating region 120 partially overlapping with the first gate structure 141 (PLDMOS element). The second conductive portion 190-2 according to the embodiments can electrically connect the conductive layer 172 with the drain of the PLDMOS element (including the third top doped region 163 and the fourth top doped region 164). Therefore, the semiconductor device according to the embodiments uses the PLDMOS element as a trigger source of the NLDMOS element, and the semiconductor device uses electrons as the carrier for internal carrier conduction, and thus operates as a NLDMOS element.

[0118] Therefore, the semiconductor device according to the embodiments not only maintains the original size of the PLDMOS element with only a slight increase in size due to the embedded PLDMOS element and NLDMOS element, but also has the advantages of the NLDMOS element, such as a significantly reduced on-resistance (Ron) and a significantly reduced device area. Therefore, the semiconductor device according to the embodiments has the advantages of both the PLDMOS element and the NLDMOS element, such as a simple circuit design, a small layout area, and good electrical properties, and thus improves the electrical properties and miniaturizes the semiconductor device.

[0119] Figure 4is a cross-sectional schematic view corresponding to another intermediate stage of another semiconductor structure according to some embodiments of the present application. Figure 4 As Figure 3 the same or similar elements are denoted by the same or similar element reference numerals. For the sake of simplicity, the same or similar elements as Figure 3 illustrated and their forming steps will not be repeated.

[0120] In some embodiments, with reference to Figure 4 , the semiconductor device includes a second-conductivity-type region 110 (e.g. a high-voltage N-type well or an N-type epitaxial layer) within a semiconductor substrate 100, and a drift region 120, a first well ( / second-conductivity-type base region) 151 and a second well ( / first-conductivity-type base region) 152 within the second-conductivity-type region 110 and extending downward from a top surface 110a thereof. The semiconductor device further includes two opposite-conductivity-type top doped regions within the first well ( / second-conductivity-type base region) 151, namely a first top doped region 161 having a second-conductivity-type (e.g. N-type) and a second top doped region 162 having a first-conductivity-type (e.g. P-type) as described above. The semiconductor device further includes two opposite-conductivity-type top doped regions within the second well, namely a third top doped region 163 having a first-conductivity-type (e.g. P-type) and a fourth top doped region 164 having a second-conductivity-type (e.g. N-type) as described above. Further, as Figure 1 shown, the drift region 120 can include a plurality of drift portions respectively extending along a first direction D1 and spaced apart from each other in a second direction D2. In some embodiments, the drift portions 121-125 are arranged in parallel to each other. The relative positions of the wells and top doped regions and their forming steps as shown can refer to the above description and will not be repeated here. Figure 4

[0121] In some embodiments, as Figure 4 shown, the semiconductor device further includes a first gate structure 141, a second gate structure 142, an insulating layer 170, a conductive layer 172 (e.g. doped polysilicon), a dielectric layer 180, a first conductive portion 190-1, a second conductive portion 190-2 and a third conductive portion 190-3, etc. above the second-conductivity-type region 110. The first conductive portion 190-1 can include a first via 191V, a second via 192V, a third via 193V and a first metal line 191M; the second conductive portion 190-2 can include a fourth via 194V, a fifth via 195V, a sixth via 196V and a second metal line 192M; and the third conductive portion 190-3 can include a seventh via 197V, an eighth via 198V and a third metal line 193M. The relative positions of the components of the above-mentioned material layers or conductive portions and their forming steps have been described in detail in the above description and will not be repeated here.

[0122] ​Figure 4 The semiconductor structure of the embodiment shown is similar to Figure 3 The semiconductor structure of the embodiment shown differs mainly in the arrangement of the field oxide layer 132 / 130 and the first conductivity type heavily doped region 166 / 165.

[0123] Figure 4 In the process, the field oxide layer 132 includes a first field oxide portion 1321 and a second field oxide portion 1322. The first field oxide portion 1321 and the second field oxide portion 1322 are formed at the top surface 110a of the second conductivity type region 110, and the first field oxide portion 1321 and the second field oxide portion 1322 are disposed at a distance from each other.

[0124] In such Figure 3 In the semiconductor structure shown, the first gate structure 141 and the second gate structure 142 extend to both ends of the field oxide layer 130 and partially overlap with it. The two ends of the field oxide layer 130 may correspond, for example, to the active region A. A The two side edges E1 and E2 ( Figure 1 Furthermore, the heavily doped region 165 of the first conductivity type is located below the field oxide layer 130. And in cases such as... Figure 4 In the semiconductor structure shown, the first conductivity type heavily doped region 166 (e.g., P+) extends downward from the top surface 110a of the second conductivity type region 110, and its formation location can be between the first field oxide portion 1321 and the second field oxide portion 1322.

[0125] Furthermore, in some embodiments, such as Figure 4 As shown, a heavily doped region 166 of the first conductivity type (e.g., P+) is located in the drift region 120 and can extend downward from the top surface of an active region. This serves as a contact pad for the first via 191V of the first conductive portion 190-1.

[0126] Specifically, such as Figure 4 As shown, the first field oxide portion 1321 is located between the first gate structure 141 and the first conductivity type heavily doped region (e.g., P+) 166, and both ends of the first field oxide portion 1321 are adjacent to the first gate structure 141 and the first conductivity type heavily doped region 166, respectively. Furthermore, the second field oxide portion 1322 is located between the second gate structure 142 and the first conductivity type heavily doped region (e.g., P+) 166, and both ends of the second field oxide portion 1322 are adjacent to the second gate structure 142 and the first conductivity type heavily doped region (e.g., P+) 166, respectively.

[0127] In some embodiments, the first field oxide 1321 and the second field oxide 1322 are made of silicon oxide and can be local oxidation of silicon (LOCOS) isolation formed by thermal oxidation. In some other embodiments, the first field oxide 1321 and the second field oxide 1322 can be shallow trench isolation (STI) structures formed by etching and deposition processes.

[0128] According to some embodiments of the present application, as shown in Figure 4 , the sidewall 166s of the first conductivity type heavily doped region 166 is adjacent to or abuts a side edge of the active region. Thus, in this example, the first conductivity type heavily doped region 166 can be formed in the overlapping area of the drift region 120 and the active region, and is exposed at the top surface of the second conductivity type region 110 between the first field oxide 1321 and the second field oxide 1322 to provide a setting of a contact (e.g., the first via 191V).

[0129] According to some embodiments of the present application, as shown in Figure 4 , the semiconductor device is similar to the semiconductor device shown in Figure 3 , and structurally includes the PLDMOS element and the NLDMOS element embedded in each other, and has the benefit of maintaining or only slightly increasing the size of the original device. Furthermore, the semiconductor device shown in Figure 4 also uses the PLDMOS element as a trigger source of the NLDMOS, but uses electrons as the conduction carriers for internal carrier conduction, so that the operation behavior is the same as that of the NLDMOS element, and has the same advantages as the NLDMOS element, such as significantly reducing the on-resistance (Ron) of the semiconductor device and reducing the required device area. Therefore, the semiconductor device shown in Figure 4 also has the advantages of simple circuit design of the PLDMOS and small circuit layout area and good electrical properties of the NLDMOS, thereby improving the electrical properties of the semiconductor device and achieving miniaturization.

[0130] Figure 5 is a cross-sectional view of another intermediate stage of a semiconductor structure according to some embodiments of the present application. Figure 5 Elements identical or similar to those in Figure 3 are denoted by identical or similar reference numerals. For the sake of simplicity, the elements shown in Figure 3 and the steps of forming the same will not be described again.

[0131] In some embodiments, reference is made to Figure 5The semiconductor device includes a second conductivity type region 110 (e.g., a high-voltage N-type well or an N-type epitaxial layer) within a semiconductor substrate 100, and a drift region 120, a second conductivity type substrate region 151, a first conductivity type substrate region 152, a first top-doped region 161 and a second top-doped region 162 of the second conductivity type (e.g., N-type) within the second conductivity type substrate region 151, a third top-doped region 163 of the first conductivity type (e.g., P-type) and a fourth top-doped region 164 of the second conductivity type (e.g., N-type) within the first conductivity type substrate region 152. Figure 5 The relative positions of the well and the top doped region, as well as their formation steps, can be referred to the above content and will not be repeated here.

[0132] In some embodiments, such as Figure 5 As shown, the semiconductor device also includes a first gate structure 141, a second gate structure 142, an insulating layer 170, a conductive layer 172 (e.g., doped polysilicon), a dielectric layer 180, a first conductive portion 190-1 (e.g., including a first via 191V, a second via 192V, a third via 193V, and a first conductive wire 191M), a second conductive portion 190-2 (e.g., including a fourth via 194V, a fifth via 195V, a sixth via 196V, and a second conductive wire 192M), and a third conductive portion 190-3 (e.g., including a seventh via 197V, an eighth via 198V, and a third conductive wire 193M), etc., above the second conductivity type region 110. The relative positions of these components and their formation processes can be referred to the above content and will not be repeated here.

[0133] Figure 5 The semiconductor structure of the embodiment shown is similar to Figures 1-3 The main difference in the semiconductor structure of the illustrated embodiments lies in the active region A. A And the setting of drift zone 120. Figures 1-3 The semiconductor structure of the embodiment shown has a drift region 120 that is generally located in the active region A. A The non-active zone between (refer to) Figure 1 ). Figure 5 The semiconductor structure of the embodiment shown has a drift region 120 that is generally located in the active region A. A Location. Active area A A It can be several parallel strip regions or a whole continuous region, which can also achieve the benefits of significantly reducing on-resistance and effectively reducing the required device area of ​​the semiconductor device of the present invention.

[0134] Figure 6A The illustrations depict some embodiments of the present invention, corresponding to Figure 5A top view of the active region and drift region of a semiconductor device. In some embodiments, such as Figure 6A As shown, in the semiconductor device, the active region A A It is composed of multiple elongated regions, and these elongated active regions A A They extend along a first direction D1 (e.g., the X direction) and are spaced apart and parallel to each other along a second direction D2 (e.g., the Y direction). In this example, these strip-shaped active areas A A They are separated by field oxide layers (such as LOCOS isolation layers) or shallow trench isolation (STI) structures.

[0135] Furthermore, in some embodiments, the drift region 120 may include a plurality of drift sections having a first conductivity type (e.g., P-type), for example... Figure 6A The drifting portions 121-125 shown extend along a first direction D1 (e.g., the X direction) and are spaced apart from each other in a second direction D2 (e.g., the Y direction). In some embodiments, these drifting portions 121-125 are arranged parallel to each other. Figure 6A As shown, in this example, for the elongated active region A... A Ion implantation is performed to form drift sections 121-125 of drift region 120, wherein drift sections 121-125 are respectively derived from active region A. A The top surface extends downwards. For example... Figure 6A As shown, the drift regions 121-125 formed after ion implantation are each associated with the corresponding elongated active region A. A Part of it overlaps.

[0136] Figure 6B The illustrations depict some embodiments of the present invention, corresponding to Figure 5 A top view of another active region and drift region of a semiconductor device. (And) Figure 6A Active area A A Including multiple elongated areas that are different, Figure 6B Active area A A This refers to a continuous region across the entire surface. In this example, within the active region A of the entire surface... A Ion implantation is performed to form multiple drift sections 121-125 of the drift region 120.

[0137] Figure 7 This is a schematic diagram of a circuit structure of a semiconductor structure according to some embodiments of the present invention. See also... Figure 3semiconductor structure. Compared to a general P-type laterally diffused metal oxide semiconductor (PLDMOS) device, the semiconductor device of some embodiments, for example, includes a P-type drift region and a P+ drain, which is structurally similar to a PLDMOS element but can be considered as a PLDMOS element and a NLDMOS element (as described above Figures 3-5 in a nested manner, thus the semiconductor device of the embodiments has the benefit of maintaining or only slightly increasing the size of the original device. In operation, as shown in Figure 7 , the drain terminal D of the semiconductor device of the embodiments is connected to the conductive layer 172 (having a second resistance R2), and the conductive layer 172 and the drift region 120 (having a first resistance Rl) are connected to the second gate structure 142. When the gate voltage Vg of the first gate structure 141 is 0 V, the PLDMOS element is turned on, and the P-point voltage Vp is high, at which time the NLDMOS element is turned on, and a current Id flows from the source terminal S to the drain terminal D, thus the semiconductor device is turned on (with electrons as carriers). When the gate voltage Vg of the first gate structure 141 is 0 V, the P-point voltage Vp obtained by the second gate structure 142 can be adjusted according to the ratio of the first resistance Rl of the drift region 120 and the second resistance R2 of the conductive layer 172, so that the semiconductor device is turned on. When the gate voltage Vg of the first gate structure 141 is the power supply voltage Vdd, the P-point voltage Vp is relatively low or even equal to zero, the NLDMOS element is turned off, and no current is generated, thus the semiconductor device is turned off. Accordingly, the semiconductor device of the embodiments has a structure similar to the simple design of a PLDMOS device, but the inside is an electron conduction mode of a NLDMOS, which reduces the on-resistance. Therefore, the semiconductor device of the embodiments has the advantages of the simple circuit design of a PLDMOS and the small circuit layout area and good electrical properties of a NLDMOS device.

[0138] In summary, the semiconductor device of some embodiments of the present application has a structure design that helps to effectively reduce the on-resistance (Ron) of the semiconductor device without increasing or even reducing the required device area. The semiconductor device of some embodiments has a structure that includes a PLDMOS element and a NLDMOS element embedded in each other, so that the original device size can be maintained or only slightly increased. Furthermore, the semiconductor device of some embodiments uses the PLDMOS element as the trigger source of the NLDMOS element, and uses electrons as the conduction carriers for internal carrier conduction. Therefore, the semiconductor device of some embodiments behaves like a NLDMOS element in operation, and has the advantages of a NLDMOS element, such as significantly reducing the on-resistance of the semiconductor device and further reducing the required device area. Therefore, even if the semiconductor device of some embodiments has a structure that includes a PLDMOS element and a NLDMOS element embedded in each other, which may slightly increase the size of the device compared to a general PLDMOS element, the benefit of significantly reducing the device area brought by the operation behavior (electron conduction) of the NLDMOS element still makes the semiconductor device of some embodiments effectively reduce the required area. Furthermore, the overall structure of the semiconductor device of some embodiments is similar to that of a PLDMOS element, which has the benefit of a simple circuit design. In summary, the semiconductor device of some embodiments has the benefits of significantly reduced on-resistance and effectively reduced required device area, thereby improving the electrical performance of the semiconductor device and achieving size miniaturization. In addition, the manufacturing method of the semiconductor device proposed by some embodiments is compatible with the steps of existing processes, and the manufacturing method is simple and does not significantly increase the manufacturing cost.

[0139] Although the present application has been disclosed in several preferred embodiments, it is not intended to limit the present application, and any modification and improvement made by those skilled in the art without departing from the spirit and scope of the present application is intended. Therefore, the scope of protection of the present application is defined by the appended claims.

Claims

1. A semiconductor device, characterized by comprising: Comprising: a semiconductor substrate having a first conductivity type; a second conductivity type region located within the semiconductor substrate and extending downward from a top surface of the semiconductor substrate; a drift region located in the second conductivity type region and extending downward from a top surface of the second conductivity type region, wherein the drift region has a first side and a second side, wherein the drift region has the first conductivity type; a source structure disposed apart from the first side of the drift region, the source structure including a first top doped region having the second conductivity type and a second top doped region having the first conductivity type, and the second top doped region being adjacent to the first top doped region; a first gate structure disposed corresponding to the first side of the drift region and located on the top surface of the second conductivity type region; a drain structure disposed apart from the second side of the drift region opposite to the first side, the drain structure including a third top doped region having the first conductivity type and a fourth top doped region having the second conductivity type, and the fourth top doped region being adjacent to the third top doped region; a second gate structure located on the top surface of the second conductivity type region, the second gate structure being adjacent to the second side of the drift region and being located between the drift region and the drain structure; and a conductive layer located on the second gate structure and an insulating layer located between the second gate structure and the conductive layer, wherein the conductive layer electrically connects the drain structure, the second gate structure and the drift region. A portion of a bottom surface of the first gate structure overlaps a portion of the drift region underneath.

2. The semiconductor device according to claim 1, wherein The drift region includes a plurality of drift portions respectively extending along a first direction and being disposed in parallel on the top surface of the second conductivity type region, and the drift portions are apart from each other in a second direction different from the first direction.

3. The semiconductor device according to claim 1, wherein Further comprising a first conductivity type body region extending downward from the top surface of the second conductivity type region, the third top doped region and the fourth top doped region of the drain structure being located in the first conductivity type body region, wherein a portion of a bottom surface of the second gate structure overlaps a portion of the first conductivity type body region underneath.

4. The semiconductor device according to claim 1, wherein Further comprising a second conductivity type body region extending downward from the top surface of the second conductivity type region, the first top doped region and the second top doped region of the source structure being located in the second conductivity type body region, wherein a portion of a bottom surface of the first gate structure overlaps a portion of the second conductivity type body region underneath.

5. The semiconductor device according to claim 1, wherein Further comprising a field oxide layer formed at the top surface of the second conductivity type region, wherein the field oxide layer is located between the first gate structure and the second gate structure, and two ends of the field oxide layer respectively contact the first gate structure and the second gate structure.

6. The semiconductor device according to claim 1, wherein The field oxide layer is located above the drift region.

7. The semiconductor device according to claim 6, wherein Further comprising:

8. The semiconductor device according to claim 1, wherein a first conductivity type heavily doped region located in the drift region and extending downward from the top surface of the second conductivity type region; ​ A first field oxide region is located between the first gate structure and the heavily doped region of the first conductivity type, and the two ends of the first field oxide region are respectively adjacent to the first gate structure and the heavily doped region of the first conductivity type; and A second field oxide section is located between the second gate structure and the first conductivity type heavily doped region, and the two ends of the second field oxide section are respectively adjacent to the second gate structure and the first conductivity type heavily doped region.

9. The semiconductor device according to claim 8, wherein The heavily doped region of the first conductivity type is exposed on the surface of an active region between the first field oxide and the second field oxide.

10. The semiconductor device as claimed in claim 1, characterized in that... The first top doped region, the second top doped region, the third top doped region, and the fourth top doped region extend downward from the top surface of the second conductivity type region; The second top-doped region is positioned at a distance from the first side of the drift region, and the second top-doped region is located between the first side and the first top-doped region; and The fourth top doped region is positioned at a distance from the second side of the drift region, and the fourth top doped region is located between the second side and the third top doped region.

11. The semiconductor device according to claim 1, wherein The conductive layer electrically connects the third top-doped region, the second gate structure, and the drift region.

12. The semiconductor device according to claim 1, wherein The first gate structure is adjacent to the second top-doped region, and the second gate structure is adjacent to the fourth top-doped region.

13. The semiconductor device according to claim 1, wherein Including: A heavily doped region of the first conductivity type is located in the drift region; and A dielectric layer is located above the second conductivity type region and covers the top surface of the second conductivity type region, and the dielectric layer covers the first gate structure, the second gate structure and the conductive layer.

14. The semiconductor device according to claim 13, wherein Including: A first via passes through the dielectric layer and connects to the heavily doped region of the first conductivity type; A second via passes through the dielectric layer and connects to the second gate structure; A third via, passing through the dielectric layer and connecting to the conductive layer; and A first conductor is located on the top surface of the dielectric layer, wherein the first conductor connects the first via, the second via, and the third via.

15. The semiconductor device according to claim 14, wherein Including: A fourth via passes through the dielectric layer and connects to the conductive layer; A fifth via passes through the dielectric layer and connects to the third top-doped region; A sixth via, passing through the dielectric layer and connecting to the fourth top-doped region; and A second conductor is located on the top surface of the dielectric layer, wherein the second conductor connects the fourth via, the fifth via, and the sixth via.

16. The semiconductor device according to claim 15, wherein Including: A seventh via passes through the dielectric layer and connects to the first top-doped region; An eighth via passes through the dielectric layer and connects to the second top-doped region; as well as A third conductor is located on the top surface of the dielectric layer, wherein the third conductor connects the seventh via and the eighth via.

17. A method of forming a semiconductor device, comprising: include: A semiconductor substrate having a first conductivity type is provided, the semiconductor substrate including a second conductivity type region, and the second conductivity type region extending downward from the top surface of the semiconductor substrate; A drift region is formed in the second conductivity type region, the drift region having the first conductivity type and having a first side and a second side, and the drift region extends downward from the top surface of the second conductivity type region; forming a source structure and a drain structure disposed away from the first side and the second side of the drift region, respectively, wherein the source structure includes a first top doped region having the second conductivity type and a second top doped region having the first conductivity type, and the second top doped region is adjacent to the first top doped region, and the drain structure includes a third top doped region having the first conductivity type and a fourth top doped region having the second conductivity type, and the fourth top doped region is adjacent to the third top doped region; forming a first gate structure on the top surface of the second conductivity type region, and the first gate structure corresponds to the first side of the drift region; forming a second gate structure on the top surface of the second conductivity type region, and the second gate structure is adjacent to the second side of the drift region and is located between the drift region and the drain structure; forming a conductive layer on the second gate structure, wherein an insulating layer is located on the second gate structure, and the conductive layer is located on the insulating layer; and electrically connecting the conductive layer to the drain structure, the second gate structure, and the drift region. The drift region includes a plurality of drift portions extending along a first direction and arranged in parallel on the top surface of the second conductivity type region, and the drift portions are spaced apart from each other in a second direction different from the first direction.

18. The method for forming a semiconductor device according to Claim 17, wherein Further comprising:

19. The method for forming a semiconductor device according to Claim 17, wherein forming a first conductivity type base region in the second conductivity type region, and the first conductivity type base region extends downward from the top surface of the second conductivity type region, the first conductivity type base region is adjacent to and disposed away from the second side of the drift region, wherein the third top doped region and the fourth top doped region are formed in the first conductivity type base region. Further comprising:

20. The method for forming a semiconductor device according to Claim 17, wherein forming a second conductivity type base region in the second conductivity type region, and the second conductivity type base region extends downward from the top surface of the second conductivity type region, the second conductivity type base region is adjacent to and disposed away from the first side of the drift region, wherein the first top doped region and the second top doped region are formed in the second conductivity type base region. Further comprising:

21. The method for forming a semiconductor device according to Claim 17, wherein forming a field oxide layer at the top surface of the second conductivity type region, wherein the field oxide layer is located between the first gate structure and the second gate structure, and two ends of the field oxide layer contact the first gate structure and the second gate structure, respectively, and the field oxide layer is located above the drift region. Further comprising:

22. The method for forming a semiconductor device according to Claim 21, wherein forming a first conductivity type heavily doped region in the drift region, and the field oxide layer is located above the first conductivity type heavily doped region. Further comprising:

23. The method for forming a semiconductor device according to Claim 17, wherein forming a first conductivity type heavily doped region in the drift region, and the first conductivity type heavily doped region extends downward from the top surface of the second conductivity type region; forming a first field oxide portion between the first gate structure and the first conductivity type heavily doped region, and two ends of the first field oxide portion are adjacent to the first gate structure and the first conductivity type heavily doped region, respectively; and forming a second field oxide portion between the second gate structure and the first conductivity type heavily doped region, and two ends of the second field oxide portion are adjacent to the second gate structure and the first conductivity type heavily doped region, respectively. a second field oxide portion is formed between the second gate structure and the first heavily doped region of the first conductivity type, and two ends of the second field oxide portion are respectively adjacent to the second gate structure and the first heavily doped region of the first conductivity type; wherein the first heavily doped region of the first conductivity type is exposed to a surface of an active region between the first field oxide portion and the second field oxide portion.

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