Low voltage flash memory integrated with vertical field effect transistors

Abstract

A circuit (400) includes a low voltage flash memory (200) integrated with a vertical field effect transistor and a non-volatile memory element (100). The low voltage flash memory is coupled with the non-volatile memory element through the vertical field effect transistor, one or more bit lines, and one or more word lines. The low voltage flash memory can provide a lower significant conductance and the non-volatile memory element can provide a higher significant conductance. The low voltage flash memory can include a source and a drain. The source can be separated from the drain by an epitaxial channel. The low voltage flash memory can include a floating gate. The floating gate can be separated from the epitaxial channel by a first dielectric layer. The low voltage flash memory can include a control gate. The control gate can be separated from the floating gate by a second dielectric layer.

Description

TECHNICAL FIELD

[0001] The present invention relates generally to semiconductor structures and methods of forming the same. More particularly, the present invention relates to a semiconductor structure including low voltage flash memory integrated with vertical field effect transistors (VFETs). BACKGROUND

[0002] Deep learning is a machine learning method based on artificial neural networks inspired by information processing in biological systems. In neuromorphic computing, electronic analog circuits are used to mimic the neurobiological architecture present in the nervous system. SUMMARY

[0003] According to one embodiment of the present invention, a circuit is provided. The circuit can include low voltage flash memory integrated with a vertical field effect transistor and a non-volatile memory element. The low voltage flash memory can be coupled to the non-volatile memory element through the vertical field effect transistor, one or more bit lines, and one or more word lines. The low voltage flash memory can provide a lower significant conductance, while the non-volatile memory element can provide a higher significant conductance. The low voltage flash memory can include a source and a drain. The source can be separated from the drain by an epitaxial channel. The low voltage flash memory can include a floating gate. The floating gate can be separated from the epitaxial channel by a first dielectric layer. The low voltage flash memory can include a control gate. The control gate can be separated from the floating gate by a second dielectric layer. The low voltage flash memory can be programmed by applying a voltage pulse of opposite polarity to the control gate. The low voltage flash memory can be programmed by turning off the vertical field effect transistor and applying a program voltage to the control gate of the low voltage flash memory. The low voltage flash memory can be read by turning on the vertical field effect transistor and applying a read voltage to the control gate of the low voltage flash memory. The source, the drain, and the epitaxial channel can be doped with n-type dopants. The non-volatile memory element can be phase change memory, resistive random access memory, magnetic random access memory, or flash memory.

[0004] According to another embodiment of the present application, a semiconductor structure is provided. The semiconductor structure can include a low voltage flash memory and a non-volatile memory element integrated with a vertical field effect transistor. The low voltage flash memory can be coupled to the non-volatile memory element through the vertical field effect transistor, one or more bit lines, and one or more word lines. The low voltage flash memory can include a first source drain, a second source drain, a floating gate, and a control gate. The second source drain can be separated from the first source drain by an epitaxial channel. The floating gate can be separated from the epitaxial channel by a first dielectric layer. The control gate can be separated from the floating gate by a second dielectric layer. The floating gate can have a doping type opposite a doping type of the epitaxial channel. The first source drain, the second source drain, and the epitaxial channel can be doped with n-type dopants. The first dielectric can be made of a high-k dielectric material. The low voltage flash memory can be vertical and can be separated from the vertical field effect transistor by a shallow trench isolation. The non-volatile memory element can be a phase change memory, a resistive random access memory, a magnetic random access memory, or a flash memory.

[0005] According to another embodiment of the present application, a method is provided. The method can include forming a low voltage flash memory and a non-volatile memory element integrated with a vertical field effect transistor. The method can include forming a shallow trench isolation between the low voltage flash memory and the vertical field effect transistor. The low voltage flash memory can be coupled to the non-volatile memory element through the vertical field effect transistor. Forming the low voltage flash memory can include growing a first source drain on a substrate, epitaxially growing an epitaxial channel on the first source drain, epitaxially growing a second source drain on the epitaxial channel, forming a floating gate around the epitaxial channel, and forming a control gate around the floating gate, the control gate separated from the floating gate by a first dielectric layer. The first dielectric layer can be made of a high-k dielectric material. The first source drain, the epitaxial channel, and the second source drain can be doped with n-type dopants. The non-volatile memory element can be a phase change memory, a resistive random access memory, a magnetic random access memory, or a flash memory. The floating gate can have a doping type opposite a doping type of the epitaxial channel. BRIEF DESCRIPTION OF DRAWINGS

[0006] The following detailed description will best be understood in conjunction with the accompanying drawings, of which:

[0007] Figure 1 is a cross-sectional view showing a dummy gate and a dielectric cap layer disposed on a substrate according to an example embodiment;

[0008] Figure 2 is a cross-sectional view showing a trench formed to expose a source according to an example embodiment;

[0009] Figure 3is a cross-sectional view illustrating an epitaxial layer and a dielectric cap, according to an exemplary embodiment;

[0010] Figure 4 is a cross-sectional view illustrating formation of a drain on an epitaxial channel, according to an exemplary embodiment;

[0011] Figure 5 is a cross-sectional view illustrating removal of dummy gate and oxide layer, according to an exemplary embodiment;

[0012] Figure 6 is a cross-sectional view illustrating deposition of a first dielectric layer and a floating gate material, according to an exemplary embodiment;

[0013] Figure 7 is a cross-sectional view illustrating removal of portions of the first dielectric layer and the floating gate material to form a floating gate, according to an exemplary embodiment;

[0014] Figure 8 is a cross-sectional view illustrating deposition of a second dielectric layer and a control gate material, according to an exemplary embodiment;

[0015] Figure 9 is a cross-sectional view illustrating removal of portions of the second dielectric layer and the control gate material to form a control gate, according to an exemplary embodiment;

[0016] Figure 10 is a cross-sectional view illustrating deposition of an interlayer dielectric and formation of contacts, according to an exemplary embodiment;

[0017] Figure 11 is a cross-sectional view illustrating a vertical field effect transistor and low voltage flash memory, according to an exemplary embodiment;

[0018] Figure 12 is a graph illustrating drain current as a function of total floating gate charge (c), according to an embodiment;

[0019] Figure 13 is a simplified circuit diagram of a memory array of simulated memory cells, according to an exemplary embodiment; and

[0020] Figure 14 is a simplified circuit diagram illustrating a vertical field effect transistor and low voltage flash memory, according to an exemplary embodiment.

[0021] The drawings are not necessarily to scale. The drawings are merely schematic representations, not intended to portray specific parameters of the application. The drawings are intended to depict only typical embodiments of the application. In the drawings, like numbers refer to like elements. DETAILED DESCRIPTION

[0022] Detailed embodiments of the claimed structures and methods are disclosed herein; however, it is understood that the disclosed embodiments are merely examples of the claimed structures and methods which can be embodied in various forms. The application can be implemented in numerous ways, including with both hardware and software implementations, either in or through software as a program running on hardware, or a program. However, this application should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the application to those skilled in the art. In the description, details of well-known features and techniques can be omitted to avoid unnecessarily obscuring present embodiments.

[0023] For purposes of the description hereinafter, the terms "upper", "lower", "right", "left", "vertical", "horizontal", "top", "bottom", and derivatives thereof shall relate to the disclosed structures and methods, as oriented in the drawing figures. The terms "overlying", "atop", "on", "located on" or "positioned on" mean that a first element is present on a second element wherein an intermediate element (e.g. a substrate) can be present between the first element and the second element. The term "direct contact" means that a first element (e.g. a first structure) and a second element (e.g. a second structure) are connected without any intermediate conductive, insulating or semiconductor layers at the interface of the two elements.

[0024] In order not to obscure the presentation of embodiments of the present application, in the following detailed description some processing steps or operations that are known in the art can be combined together for presentation and for illustration purposes and can not be described in detail in some instances. In other cases, some processing steps or operations that are known in the art can not be described at all. It should be understood that the following description is more focused on the distinguishing features or elements of the various embodiments of the present application.

[0025] Embodiments of the present application generally relate to semiconductor structures and methods of forming the same. More specifically, the present application relates to a semiconductor structure including low voltage flash memory integrated with vertical field effect transistors (VFETs).

[0026] Deep learning is a machine learning method based on artificial neural networks. The computation of deep neural networks can include both training and forward inference. For neuromorphic computation, memory elements that are sufficiently linear and have sufficiently long retention time are needed. However, conventional single-device memory elements are either sufficiently linear or have sufficiently long retention time, but not both. Thus, a hybrid design can be expected. Conventional hybrid designs integrate phase change memory cells with capacitors. The phase change memory can provide long retention time, and the capacitor can provide linearity. However, even with the hybrid design, the capacitor has low retention time. Thus, the capacitor needs to transfer the programmed state to the phase change memory to avoid data loss. Furthermore, with the phase change memory cell, in combination with the capacitor, a complex circuit including several transistors, phase change memory cells, and capacitors is needed. Thus, there is a need to fabricate a device that has sufficient linearity, has sufficiently long retention time, and allows a simple circuit design.

[0027] Embodiments of the present invention relate to a semiconductor structure including low voltage flash memory integrated with VFETs. More particularly, embodiments of the present invention provide a new circuit structure and integration technique for vertically fabricating low voltage flash memory integrated with VFETs, thereby reducing device footprint and allowing more devices to be integrated in a given chip area. The new circuit structure can include low voltage flash memory integrated with VFETs and non-volatile memory.

[0028] Figures 1-11 A method of fabricating a vertical low voltage flash memory is illustrated. Figures 12-14 An exemplary circuit structure including vertical low voltage flash memory integrated with VFETs and non-volatile memory is shown.

[0029] Reference is now made to Figure 1 A structure 100 according to an embodiment is shown. The structure 100 can include a substrate 102, a counter-doped layer 104, a source 106, a first spacer 108, a dummy gate 110, a second spacer 112, and a dielectric cap layer 114. The substrate 102 can include one or more semiconductor materials. Non-limiting examples of suitable substrate 102 materials can include Si (silicon), strained Si, Ge (germanium), SiGe (silicon germanium), Si alloys, Ge alloys, III-V materials (e.g., GaAs (gallium arsenide), InAs (indium arsenide), InP (indium phosphide), or aluminum arsenide (AlAs)), II-VI materials (e.g., CdSe (cadmium selenide), CdS (cadmium sulfide), CdTe (cadmium telluride), ZnO (zinc oxide), ZnSe (zinc selenide), ZnS (zinc sulfide), or ZnTe (zinc telluride)), or any combination thereof. In one embodiment, the substrate 102 can include silicon.

[0030] A counter-doped layer 104 is deposited on a top surface of the substrate 102. A source 106 is then disposed on the substrate 102, over the counter-doped layer 104. The source 106 and the counter-doped layer 104 can be formed on the substrate 102, incorporating dopants into the substrate 102 or forming an epitaxial growth on the substrate 102. In embodiments, the source 106 is heavily doped with an n-type dopant, such as phosphorous or arsenic. The dopant level in the source 106 is in a range from about 3E20 atoms / cm 3 to about 8E20 atoms / cm 3 In alternative embodiments, the source 106 is heavily doped with a p-type dopant, such as boron or gallium. In embodiments, the source 106 can be referred to as a first source drain.

[0031] The counter-doped layer 104 includes a dopant that is different / opposite to the dopant in the doped source 106. For example, when the doped source 106 includes an n-type dopant, the counter-doped layer 104 includes a p-type dopant, and when the doped source 106 includes a p-type dopant, the counter-doped layer 104 includes an n-type dopant. In embodiments, the counter-doped layer 104 is lightly doped with a p-type dopant, such as boron or gallium. The thickness of the counter-doped layer 104 can be in a range from about 5 to about 50 nm, or from about 10 to about 20 nm. The thickness of the source 106 can be in a range from about 50 nm to about 250 nm, or from about 70 nm to about 150 nm. The counter-doped layer 104 forms a diode and acts as an insulator, insulating the source 106 from the substrate 102, such that current does not dissipate into the substrate 102.

[0032] A dummy gate 110 is disposed on the source 106 between the first spacer 108 and the second spacer 112. The first spacer 108 is deposited on the source 106, the dummy gate 110 is deposited on the first spacer 108, and the second spacer 112 is deposited on the dummy gate 110.

[0033] The first spacer 108 and the second spacer 112 can include an insulating material, such as silicon dioxide, silicon nitride, SiOCN, or SiBCN. Other non-limiting examples of materials for the first spacer 108 and the second spacer 112 can include a dielectric oxide (e.g., silicon oxide), a dielectric nitride (e.g., silicon nitride), a dielectric oxynitride, or any combination thereof. The first spacer 108 and the second spacer 112 material is deposited by a deposition process, such as chemical vapor deposition (CVD) or physical vapor deposition (PVD). The first spacer 108 and the second spacer 112 can each have a thickness of about 3 to about 15 nm, or about 5 to about 10 nm.

[0034] The dummy gate 110 can include a sacrificial gate material, such as amorphous silicon (a-Si) or poly-silicon. The sacrificial material can be deposited by a deposition process, including but not limited to physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), inductively coupled plasma chemical vapor deposition (ICP CVD), or any combination thereof. The sacrificial material forming the dummy gate 110 can have a thickness of about 8 nm to about 100 nm, or about 10 nm to about 30 nm.

[0035] A dielectric cap layer 114 is deposited on the second spacer 112 above the dummy gate 110. The dielectric cap layer 114 can also be referred to as an oxide layer. Non-limiting examples of materials for the dielectric cap layer 114 can include silicon dioxide, tetraethyl orthosilicate (TEOS) oxide, high aspect ratio plasma (HARP) oxide, high temperature oxide (HTO), high density plasma (HDP) oxide, oxide formed by an atomic layer deposition (ALD) process (e.g., silicon oxide), or any combination thereof. The dielectric cap layer 114 can have a thickness in a range from about 30 nm to about 200 nm, or from about 50 nm to about 100 nm.

[0036] Referring now to Figure 2 FIG. 2 shows the structure 100 with a trench 116 according to an embodiment. The trench 116 extends from a top surface of the dielectric cap layer 114 to the source 106, thereby exposing a top surface of the source 106. The trench 116 is formed by performing an etch process that is selective (will not substantially remove) to the material of the source 106. The etch process can be, for example, a reactive ion etch.

[0037] A plurality of etching processes can be performed to form the trench 116 within the structure 100. For example, a first etching process can be performed to selectively remove a portion of the dielectric cap layer 114 relative to the material of the second spacer 112. Then, a second etching process can be performed to selectively remove portions of the second spacer 112 underlying portions of the trench 116 formed by the first etching process for the material of the dummy gate 110. Then, a third etching process can be performed to selectively remove a portion of the dummy gate 110 underlying portions of the trench 116 formed by the second etching process for the material of the first spacer 108. Then, a fourth etching process can be performed to remove a portion of the first spacer 108 to expose a top surface of the source 106. The resulting trench 116 can extend downward through the top surface of the dielectric cap layer 114 to the top surface of the exposed portion of the source 106. The width of the trench 116 can be about 3 nm to about 20 nm, or about 5 nm to about 10 nm. The depth of the trench 116 can be about 50 nm to about 300 nm, or from about 100 nm to about 200 nm.

[0038] Once the trench 116 is formed, the exposed portions of the dummy gate 110 sidewalls are oxidized. The oxidation allows for the formation of an oxide layer 118 along the sidewalls of the trench 116. The oxidation can be performed by a plasma oxidation process or any other oxidation process that forms the oxide layer 118. A portion of the first spacer 108 or the source 106 can also be oxidized. However, prior to performing the additional steps described herein with reference to Figures 3 to 11 any oxide formed in these regions can be removed.

[0039] Referring now to Figure 3 , a structure 100 having an epitaxial channel 120 and a dielectric cap 122 is shown in accordance with an embodiment. Once the exposed portions of the dummy gate 110 sidewalls are oxidized, an epitaxial layer is grown on the top surface of the source 106 to form the epitaxial channel 120. The epitaxial growth can include an epitaxial semiconductor material, and the epitaxial growth and / or deposition process can be selective to forming on a semiconductor surface and not depositing material on other surfaces, such as the oxide layer 118, the first spacer 108, or the second spacer 112.

[0040] The epitaxial channel 120 is doped with the same type of dopant as the source 106. In an embodiment, the epitaxial channel 120 is doped with an n-type dopant, such as phosphorous or arsenic. The level of dopant in the epitaxial channel 120 is lower than the level of dopant in the source 106. The level of dopant in the epitaxial channel 120 is about 5E20 atoms / cm 3 .

[0041] The epitaxial channel 120 can be grown using a suitable growth process, such as chemical vapor deposition (CVD) (liquid phase (LP) or reduced pressure chemical vapor deposition (RPCVD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), metal organic chemical vapor deposition (MOCVD), or other suitable process.

[0042] The source of the epitaxial channel material can be, for example, n-type silicon, germanium, or a combination thereof. The gas sources for depositing the epitaxial semiconductor material can include a silicon-containing gas source, a germanium-containing gas source, or a combination thereof. For example, the epitaxial silicon layer can be deposited from a silicon gas source selected from silane, disilane, trisilane, tetrasilane, hexachlorodisilane, tetrachlorosilane, dichlorosilane, trichlorosilane, and combinations thereof. The epitaxial germanium layer can be deposited from a germanium gas source selected from germane, digermane, halogenated germane, dichlorogermane, trichlorogermane, tetrachlorogermane, and combinations thereof. Combinations of these gas sources can be utilized to form an epitaxial silicon-germanium alloy layer. A carrier gas, such as hydrogen, nitrogen, helium, and argon, can be used.

[0043] [During the growth process, the epitaxial growth in the epitaxial channel 120 can extend over the dielectric cap layer 114 (not shown). A planarization process, such as a chemical mechanical polishing (CMP) process, can be used to remove the excess epitaxial growth over the dielectric cap layer 114. Additionally, the epitaxial channel 120 can be partially recessed and then backfilled with the dielectric cap 122. The epitaxial channel 120 can be partially recessed to a level that is still within the dielectric cap layer 114 but above the second spacer 112. The epitaxial channel 120 can be recessed by etching, such as by a reactive ion etching or a wet etching process.

[0044] The opening formed over the recessed epitaxial channel 120 is filled with a dielectric material, thereby forming a dielectric cap 122 over the epitaxial channel 120. The dielectric cap 122 can be made of a dielectric material, such as a dielectric oxide (e.g., silicon oxide), a dielectric nitride (e.g., silicon nitride), a dielectric oxynitride, or any combination thereof. The dielectric material is deposited by a deposition process, such as chemical vapor deposition (CVD) or physical vapor deposition (PVD). After it is formed, the dielectric cap 122 is planarized by, for example, CMP.

[0045] Reference is now made to Figure 4FIG. 1 illustrates a structure 100 with a drain 124 according to embodiments. The dielectric cap layer 114 is substantially removed, exposing the top surface of the second spacer 112. The dielectric cap layer 114 can be etched using a process that is selective to the second spacer 112 (does not substantially remove). Once the dielectric cap layer 114 is removed, the drain 124 is epitaxially grown from the exposed sidewalls of the epitaxial channel 120. The drain 124 is doped with the same type of dopant as the source 106 and the epitaxial channel 120. In embodiments, the drain is doped with an n-type dopant, such as phosphorous or arsenic. The dopant level in the drain 124 is higher than the dopant level in the epitaxial channel 120. The dopant level in the drain 124 is about 3E20 atoms / cm 3 In embodiments, the drain 124 and the source 106 have a higher doping concentration than the epitaxial channel 120. In embodiments, the drain 124 can be referred to as a second source-drain.

[0046] The drain 124 is disposed between the dielectric cap 122 and the epitaxial channel 120. The drain 124 is also disposed between the dielectric cap 122 and the dummy gate 110. Prior to forming the drain 124, the portion of the epitaxial channel 120 on the second spacer 112 can be recessed along the sidewalls. The drain 124 is a multi-faceted epitaxial source-drain region of a vertical transistor. The multi-faceted drain 124 grows in a conical shape, with the pointed end of the drain 124 extending away from the epitaxial channel 120 horizontally. The conical shape of the drain 124 enhances the electric field at the pointed end.

[0047] Referring now to FIG. 1C, Figure 5 FIG. 1 illustrates a structure 100 with a drain 124 according to embodiments. The dielectric cap layer 114 is substantially removed, exposing the top surface of the second spacer 112. The dielectric cap layer 114 can be etched using a process that is selective to the second spacer 112 (does not substantially remove). Once the dielectric cap layer 114 is removed, the drain 124 is epitaxially grown from the exposed sidewalls of the epitaxial channel 120. The drain 124 is doped with the same type of dopant as the source 106 and the epitaxial channel 120. In embodiments, the drain is doped with an n-type dopant, such as phosphorous or arsenic. The dopant level in the drain 124 is higher than the dopant level in the epitaxial channel 120. The dopant level in the drain 124 is about 3E20 atoms / cm

[0048] Once the third spacers 126 are deposited, portions of the second spacers 112 and dummy gate 110 are removed. The second spacers 112 and dummy gate 110 are recessed to remove portions that extend horizontally beyond the third spacer 126 material. An etching process is performed that is selective to the first spacers 108 (will not be substantially removed). The etching process can be a dry etching process, such as a RIE process. Another etching process, such as a wet etching process including hot ammonia, is used to remove the remaining dummy gate under the second spacers 112 and oxide layer 118, such that the sidewalls of the epitaxial channel 120 are exposed.

[0049] Referring now to Figure 6 , a structure 100 having a first dielectric layer 128 and a floating gate material 130 is shown in accordance with an embodiment. The first dielectric layer 128 is deposited conformally along the top surface of the structure 100. The first dielectric layer 128 is disposed on the remaining portions of the second spacers 112 under the first spacers 108, epitaxial channel 120, third spacers 126, and drain 124.

[0050] The first dielectric layer 128 can be made of a high-k dielectric material having a dielectric constant greater than 3.9, 7.0, or 10.0. Non-limiting examples of suitable materials for the first dielectric layer 128 include oxides, nitrides, oxynitrides, silicates (e.g., metal silicates), aluminates, titanates, nitrides, or any combination thereof. Examples of high-k materials (having a dielectric constant greater than 7.0) include, but are not limited to, metal oxides such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. The high-k materials can also include dopants such as lanthanum and aluminum.

[0051] In embodiments, the first dielectric layer 128 has a thickness between 1-2 nm. The first dielectric layer 128 separates the epitaxial channel 120 from the floating gate material 130, thereby reducing the leakage current effect. The first dielectric layer 128 can have a lower conduction band offset from the epitaxial channel 120 than its valence band offset and a lower electron effective mass than a hole. Furthermore, the first dielectric layer 128 is a tunneling dielectric, which allows for direct tunneling of carriers as compared to conventional thicker dielectrics for Fowler-Nordheim tunneling.

[0052] The first dielectric layer 128 can be formed by a suitable deposition process, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), evaporation, physical vapor deposition (PVD), chemical solution deposition, or other similar processes.

[0053] A floating gate material 130 is deposited on a top surface of the first dielectric layer 128 such that a top portion of the floating gate material 130 and a top portion of the first dielectric layer 128 are substantially level. The floating gate material 130 can be a conductor. Non-limiting examples of materials used to form the floating gate material 130 can include aluminum (Al), platinum (Pt), gold (Au), tungsten (W), titanium (Ti), or any combination thereof, polysilicon, or a dielectric material such as silicon nitride. The conductive material can be deposited by a suitable deposition process such as CVD, PECVD, PVD, electroplating, thermal or e-beam evaporation, and sputtering. The floating gate material 130 can be doped with a dopant opposite to the dopant used to dope the epitaxial channel 120. For example, if the epitaxial channel 120 is doped with an n-type dopant, the floating gate material 130 can be doped with a p-type dopant.

[0054] After the floating gate material 130 is deposited, a planarization process such as a CMP process can be used to remove excess floating gate material 130 from a top surface of the structure 100. Thereafter, an anisotropic etch, such as a RIE process, can be performed to recess the floating gate material 130 such that a top surface of the floating gate material 130 extends above a top surface of the second spacer 112.

[0055] Referring now to Figure 7 , a structure 100 is shown with portions of the first dielectric layer 128 and the floating gate material 130 removed, in accordance with an embodiment. The structure 100 can undergo an etch process, such as a RIE process, to remove exposed portions of the first dielectric layer 128, exposing a sidewall of the third spacer 126 and a top portion of the dielectric cap 122. In addition, the floating gate material 130 is recessed to remove portions of the floating gate material 130 that horizontally extend beyond the third spacer 126 material, thus forming a floating gate 132. The etch process is performed with selectivity to the first dielectric layer 128 (will not be substantially removed). The etch process can be a dry etch process, such as a RIE process. The floating gate 132 can have a doping type opposite to a doping type of the epitaxial channel 120. In addition, the first dielectric layer 128 can have a lower barrier for tunneling of majority carriers from the epitaxial channel 120 into the floating gate 132 compared to a barrier for minority carriers in the epitaxial channel 120.

[0056] Referring now to Figure 8 , a structure 100 is shown with a second dielectric layer 134 and a control gate material 136, in accordance with an embodiment. The second dielectric layer 134 is conformally deposited along a top surface of the structure 100. The second dielectric layer 134 is disposed on the first dielectric layer 128, the third spacer 126, and the dielectric cap 122.

[0057] The second dielectric layer 134 can be made of a dielectric material having a dielectric constant greater than 3.9, 7.0, or 10.0. Non-limiting examples of suitable materials for the second dielectric layer 134 include oxides, nitrides, oxynitrides, silicates (e.g., metal silicates), aluminates, titanates, nitrides, or any combination thereof. Examples of high-k materials (having a dielectric constant greater than 7.0) include, but are not limited to, metal oxides such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. The high-k materials can also include dopants such as lanthanum and aluminum.

[0058] The second dielectric layer 134 separates the first dielectric layer 128 and the floating gate 132 from the control gate material 136. The second dielectric layer 134 can be formed by a suitable deposition process such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), evaporation, physical vapor deposition (PVD), chemical solution deposition, or other similar processes. The thickness of the second dielectric layer 134 can vary depending on the deposition process and the composition and amount of the high-k dielectric material used.

[0059] The control gate material 136 is deposited on top of the second dielectric layer 134 such that a top portion of the control gate material 136 is generally flush with a top portion of the second dielectric layer 134. The control gate material 136 can act as a conductor. Non-limiting examples of materials used to form the control gate material 136 can include aluminum (Al), platinum (Pt), gold (Au), tungsten (W), titanium (Ti), or any combination thereof, polysilicon, or a dielectric material such as silicon nitride. The conductive material can be deposited by a suitable deposition process such as CVD, PECVD, PVD, electroplating, thermal or e-beam evaporation, and sputtering.

[0060] After the control gate material 136 is deposited, a planarization process (e.g., a CMP process) can be used to remove excess control gate material 136 from the top surface of the structure 100. Thereafter, an anisotropic etch such as a RIE process can be performed to recess the control gate material 136. The control gate material 136 is recessed such that a top surface of the control gate material 136 extends above a top surface of the second spacer 112 and a bottom portion of the third spacer 126.

[0061] Reference is now made to Figure 9According to embodiments, structure 100 is shown with portions of second dielectric layer 134 and control gate material 136 removed to form control gate 138. Structure 100 can undergo an etching process, such as a RIE process, to remove exposed portions of second dielectric layer 134, exposing sidewalls of third spacer 126 and top portions of dielectric cap 122.

[0062] Once portions of second dielectric layer 134 are removed, control gate material 136 is patterned. The patterning can be performed by photolithography and etching. A pattern is transferred into control gate material 136, and using an etching process to remove a portion of control gate material 136 and define control gate 138. The etching process is selective to first spacer 108 (will not substantially remove). The etching process can be a dry etching process, such as a RIE process. Control gate 138 surrounds floating gate 132.

[0063] Reference is now made to Figure 10 According to embodiments, structure 100 is shown with interlayer dielectric (ILD) 140, control gate contact 142, and drain contact 144. Once control gate 138 is defined, ILD 140 can be deposited such that a top surface of ILD 140 is above the top surfaces of dielectric cap 122 and third spacer 126. ILD 140 can be formed from, for example, a low-k dielectric material (k < 4.0), including but not limited to silicon oxide, spin-on glass, flowable oxide, high-density plasma oxide, borophosphosilicate glass (BPSG), or any combination thereof. ILD 140 is deposited by a deposition process, including but not limited to CVD, PVD, plasma-enhanced CVD, atomic layer deposition (ALD), evaporation, chemical solution deposition, or similar processes. After ILD 140 is deposited, a planarization process, such as a CMP process, can be used to remove excess ILD 140 from the top surface of structure 100.

[0064] The control gate contact 142 extends from the surface of the ILD 140 to the control gate 138. The control gate contact 142 is formed by patterning a trench in the ILD 140. To remove the ILD 140 and form the control gate contact trench, a resist, such as a photoresist, can be deposited and patterned. An etching process, such as RIE, can be performed using the patterned resist as an etch mask to remove the ILD 140 until the control gate 138 is exposed. The control gate contact trench is filled with a conductive material or a combination of conductive materials to form the control gate contact 142. The conductive material can be a conductive metal, such as aluminum (Al), platinum (Pt), gold (Au), tungsten (W), titanium (Ti), or any combination thereof. The conductive material can be deposited by a suitable deposition process, such as CVD, PECVD, PVD, electroplating, thermal or e-beam evaporation, or sputtering. A planarization process, such as CMP, is performed to remove any conductive material from the surface of the ILD 140.

[0065] The drain contact 144 extends through the ILD 140 and the dielectric cap 122 to the drain 124 and is formed within a trench. To remove the ILD 140 and form the drain trench, a resist, such as a photoresist, can be deposited and patterned. An etching process, such as RIE, can be performed using the patterned resist as an etch mask to remove the ILD 140 and the dielectric cap 122 until the drain 124 is exposed. The drain trench is filled with a conductive material or a combination of conductive materials to form the drain contact 144 (e.g., a bit line). The conductive material fill can be a conductive metal, such as aluminum (Al), platinum (Pt), gold (Au), tungsten (W), titanium (Ti), or any combination thereof. The conductive material can be deposited by a suitable deposition process, such as CVD, PECVD, PVD, electroplating, thermal or e-beam evaporation, or sputtering. A planarization process, such as CMP, is performed to remove any conductive material from the surface of the ILD 140.

[0066] Referring now to Figure 11 , a structure 300 according to an embodiment is shown. The structure 300 includes the structure 100 and the structure 200. The structure 100 is a low voltage flash memory while the structure 200 is a VFET. The structure 100 can be separated from the structure 200 by a shallow trench isolation (STI) 146. The STI 146 can be formed in a variety of ways known in the art, such as with a single etching process or multiple etching processes. The STI 146 is in the form of a dielectric plug that separates the structure 100 from the structure 200 so that current applied to the structure 100 does not affect the structure 200. Typically, the STI 146 extends through a portion of the substrate 102 to a depth that allows the two structures 100, 200 to be electrically separated.

[0067] As Figure 11As shown, the resulting structure 300 includes a vertical low voltage flash memory (structure 100) and a VFET (structure 200) separated by an STI 146. The vertical low voltage flash memory includes a floating gate 132 surrounded by a control gate 138.

[0068] Figures 12-14 A diagram showing an exemplary circuit including a vertical low voltage flash memory and a non-volatile storage element integrated with a VFET is shown.

[0069] Reference is now made to Figure 12 , according to an embodiment, a simulation graph showing drain current as a function of floating gate total charge (C) is shown. The floating gate of the vertical low voltage flash memory (structure 100) can be linearly charged as a function of time. Thus, this graph shows that the vertical low voltage flash memory can be programmed in a linear fashion. A substantially linear response is achieved up to at least fifty microseconds (50 μβ). The drain-source voltage (V DS ) is 0.0 V, and the control gate voltage V GS is 1.5 V.

[0070] Reference is now made to Figure 13 , a simplified memory array 400 according to an embodiment is shown. The memory array 400 can include an array block 150 and unit cells 152. The unit cells 152 can be standard unit cells 154 and shared unit cells 156.

[0071] The standard unit cells 154 can include one or more non-volatile storage elements, such as phase change memory (PCM) labeled G + and G - , as well as structure 100 (low voltage flash memory) and structure 200 (VFET). Other examples of non-volatile memory elements can include, but are not limited to, resistive random access memory, magnetic random access memory, or flash memory. The memory array 400 on the right can also include intermediate terminals 158 integrated in the standard unit cells 154 and shared unit cells 156. The intermediate terminals 158 can be located between the structure 100 and the structure 200.

[0072] The structure 100 (low voltage flash memory) provides a lower significant conductance, while the non-volatile memory provides a higher significant conductance. In a conventional cell, the lower significant conductance is provided by a capacitor. The low voltage flash memory provides a higher retention time compared to the capacitor in a traditional unit cell. As a result, the state of the memory does not have to be frequently transferred to the PCM in order to achieve long term storage. Furthermore, integrating the low voltage flash memory with the VFET and PCM provides a simpler circuit compared to a traditional circuit using a capacitor.

[0073] Reference is now made toFigure 14 A simplified circuit diagram shows a shared unit cell 156 or equivalently a standard unit cell 154 low voltage flash memory / VFET portion according to an embodiment, with a middle terminal 158 on the right side and without a middle terminal 158 on the left side. Without the middle terminal 158, when the VFET (structure 200) is turned off as a pass transistor, the low voltage flash memory (structure 100) operates in the linear (triode) region since there is no or very low current flowing through the VFET. Thus, the source and drain of the low voltage flash memory have approximately the same voltage as the bit line 160.

[0074] During the training phase, the VFET is turned off. By applying an appropriate voltage pulse of opposite polarity, e.g., a positive or negative voltage pulse, to the control gate 138, the resistance of the epitaxial channel 120 of the low voltage flash memory is increased or decreased by charging or discharging its floating gate 132, as shown, depending on the polarity of the voltage applied to the control gate 138. Thus, during programming, the low voltage flash memory is decoupled from the bit line 160 and / or word line. The low voltage flash memory can be programmed by charge carriers tunneling directly in and out of the floating gate 132. Figure 9 Figure 7 During the training phase, the VFET is turned off. By applying an appropriate voltage pulse of opposite polarity, e.g., a positive or negative voltage pulse, to the control gate 138, the resistance of the epitaxial channel 120 of the low voltage flash memory is increased or decreased by charging or discharging its floating gate 132, as shown, depending on the polarity of the voltage applied to the control gate 138. Thus, during programming, the low voltage flash memory is decoupled from the bit line 160 and / or word line. The low voltage flash memory can be programmed by charge carriers tunneling directly in and out of the floating gate 132.

[0075] Once training / programming is complete, the VFET can be turned on so that the resistance of the low voltage flash memory can be read and / or transferred to non-volatile memory. During reading, the low voltage flash memory is coupled to the bit line 160 and / or word line. An appropriate read voltage is applied to the control gate 138 of the low voltage flash memory. The current flowing through the bit line 160 is detected as a measure of the memory state by peripheral circuitry, which can include, for example, a sense amplifier. The peripheral circuitry can then transfer the detected memory state to non-volatile memory, e.g., by programming the corresponding change in conductance to non-volatile memory.

[0076] In some embodiments, the middle terminal 158 shown on the right side of the circuit diagram provides more flexibility in circuit programming. For example, having the middle terminal 158 allows the application of a desired programming voltage between the middle terminal 158 and the control gate 138 of the low voltage flash memory independent of the voltage on the bit line. In one embodiment, the middle terminal can be connected to a desired voltage, e.g., ground, allowing the low voltage flash memory to be biased with a desired voltage across its drain-source. In an example, where the low voltage flash memory is an n-channel device, the middle terminal 158 is biased at a voltage lower than the bit line 160 (thus acting as a source terminal), allowing the low voltage flash memory to be programmed to a first order independent of the bit line 160 voltage.

[0077] ​The description of the various embodiments of the application has been presented for purposes of illustration, but is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application, or technical improvement over technologies found in the marketplace, or to enable other ordinary skilled people to understand the embodiments disclosed herein.

Claims

1. A semiconductor structure, comprising: A low-voltage flash memory integrated with a vertical field-effect transistor and a non-volatile memory element, wherein the low-voltage flash memory is coupled to the non-volatile memory element via the vertical field-effect transistor, one or more bit lines, and one or more word lines. The low-voltage flash memory includes: First source / drain; The second source and drain are separated from the first source and drain through an epitaxial channel; A floating gate, wherein the floating gate is separated from the epitaxial channel by a first dielectric layer; and A control gate, which is separated from the floating gate by a second dielectric layer. The first source-drain of the low-voltage flash memory is connected to the bit line, the second source-drain of the low-voltage flash memory is connected to the first source-drain of the vertical field-effect transistor, and the second source-drain of the vertical field-effect transistor is connected to the word line.

2. The semiconductor structure according to claim 1, wherein the floating gate has a doping type opposite to that of the epitaxial channel.

3. The semiconductor structure according to claim 1, wherein, The first source and drain of the low-voltage flash memory, the second source and drain of the low-voltage flash memory, and the epitaxial channel are doped with n-type dopants.

4. The semiconductor structure according to claim 1, wherein the first dielectric layer is made of a high-k dielectric material.

5. The semiconductor structure according to claim 1, wherein the low-voltage flash memory is vertical.

6. The semiconductor structure of claim 1, wherein the low-voltage flash memory is isolated from the vertical field-effect transistor by shallow trench isolation.

7. The semiconductor structure according to claim 1, wherein the non-volatile memory element is a phase-change memory, a resistive random access memory, a magnetic random access memory, or a flash memory.

8. A circuit comprising the semiconductor structure as described in claim 1.

9. The circuit of claim 8, wherein the low-voltage flash memory provides lower significant conductance and the non-volatile memory element provides higher significant conductance.

10. The circuit of claim 8, wherein the low-voltage flash memory is programmed by applying voltage pulses of opposite polarity to the control gate.

11. The circuit of claim 8, wherein the low-voltage flash memory is programmed by turning off the vertical field-effect transistor and applying a programming voltage to the control gate of the low-voltage flash memory.

12. The circuit of claim 8, wherein the low-voltage flash memory is read by turning on the vertical field-effect transistor and applying a read voltage to the control gate of the low-voltage flash memory.

13. The circuit according to claim 8, wherein, The first source and drain of the low-voltage flash memory, the second source and drain of the low-voltage flash memory, and the epitaxial channel are doped with n-type dopants.

14. A method for forming a semiconductor structure, comprising: Forming a low-voltage flash memory integrated with a vertical field-effect transistor and a non-volatile memory element, wherein the low-voltage flash memory is coupled to the non-volatile memory element via the vertical field-effect transistor, wherein forming the low-voltage flash memory includes: The first source and drain electrodes are grown on the substrate; An epitaxial channel is epitaxially grown on the first source and drain electrodes; A second source / drain electrode is epitaxially grown on the epitaxial channel; A floating gate is formed around the epitaxial channel, the floating gate being separated from the floating gate by a first dielectric layer; and A control gate is formed around the floating gate, and the control gate is separated from the floating gate by a second dielectric layer. Connect the first source and drain of the low-voltage flash memory to the bit line; Connect the second source-drain of the low-voltage flash memory to the first source-drain of the vertical field-effect transistor; and Connect the second source and drain of the vertical field-effect transistor to the word line.

15. The method of claim 14, wherein the second dielectric layer is made of a high-k dielectric material.

16. The method of claim 14, wherein, The first source / drain, the epitaxial channel, and the second source / drain of the low-voltage flash memory are doped with n-type dopants.

17. The method of claim 14, wherein, The floating gate has a doping type opposite to that of the epitaxial channel.

18. The method of claim 14, wherein the non-volatile memory element is a phase-change memory, a resistive random access memory, a magnetic random access memory, or a flash memory.

19. The method of claim 14, further comprising: A shallow trench isolation is formed between the low-voltage flash memory and the vertical field-effect transistor.

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