Data latch circuit and semiconductor memory device

Abstract

The embodiments provide a miniaturized data latch circuit and semiconductor memory device. Generally, according to one embodiment, the data latch circuit includes a first transistor of a first conductivity type, a second transistor of a first conductivity type, a third transistor of a second conductivity type, and a fourth transistor of a second conductivity type. The third transistor and the fourth transistor are controlled to perform a first control action to store data in the data latch circuit, and a second control action to read the stored data.

Description

[0001] Cross-reference to related applications

[0002] This application is based on and claims priority to Japanese Patent Application No. 2021-204613, filed December 16, 2021, and U.S. Patent Application No. 17 / 898868, filed August 30, 2022, the entire contents of which are incorporated herein by reference. Technical Field

[0003] In summary, the implementations described herein relate to data latching circuits and semiconductor memory devices. Background Technology

[0004] By using multi-level cell (MLC) and three-dimensional stacking, the bit density of flash memory has been continuously increased. As the bit density increases, the area of ​​the peripheral circuitry also increases. Among the peripheral circuitry, the data latch circuitry (also known as the page buffer) occupies the largest area. When the data latch circuitry cannot be reduced in size, it is difficult to decrease the size of the flash memory chip. Summary of the Invention

[0005] The implementation provides a miniaturized data latch circuit and semiconductor memory device.

[0006] Generally, according to one embodiment, the data latch circuit includes a first transistor of a first conductivity type, a second transistor of a first conductivity type, a third transistor of a second conductivity type, and a fourth transistor of a second conductivity type. The third transistor and the fourth transistor are controlled to perform a first control action to store data in the data latch circuit, and a second control action to read the stored data. Attached Figure Description

[0007] Figure 1 This is a block diagram illustrating a schematic configuration of a semiconductor memory device including a data latch circuit according to a first embodiment.

[0008] Figure 2 This is a circuit diagram of the data latch circuit based on the comparative example.

[0009] Figure 3A This is a diagram illustrating the features of a data latch circuit according to a first embodiment.

[0010] Figure 3B This is a circuit diagram of the data latch circuit according to the first embodiment.

[0011] Figure 4A This is a diagram illustrating the operation of the data latch circuit according to the first embodiment.

[0012] Figure 4BIt shows when Figure 4A A diagram showing the voltages of the word lines and bit lines during data reading, writing, and storage in the data latch circuit.

[0013] Figure 5 This is a diagram illustrating the storage characteristics of a semiconductor memory device according to a first embodiment.

[0014] Figure 6 This is a layout diagram of the data latch circuit according to the first embodiment.

[0015] Figure 7 It is shown Figure 6 A cross-sectional view of the stacking position of each layer in the diagram.

[0016] Figure 8 It has Figure 6 The layout diagram of multiple data latch circuits arranged in the two-dimensional direction.

[0017] Figure 9A This is a layout diagram of a first variation of the data latch circuit according to the first embodiment.

[0018] Figure 9B It shows that Figure 9A The diagram shows a layout that shifts half a cycle to the left or right.

[0019] Figure 10A Multiple units with [specific features] are configured in both the first and second directions. Figure 9A The layout diagram of the data latch circuit is shown.

[0020] Figure 10B Multiple units with [specific features] are configured in both the first and second directions. Figure 9B The layout diagram of the data latch circuit is shown.

[0021] Figure 11A This is a diagram illustrating the features of a data latch circuit according to a second embodiment.

[0022] Figure 11B This is a circuit diagram of the data latch circuit according to the second embodiment.

[0023] Figure 11C It shows when Figure 11B A diagram showing the voltages of the word lines and bit lines during data reading, writing, and storage in the data latch circuit.

[0024] Figure 12 This is a layout diagram of the data latch circuit according to the second embodiment.

[0025] Figure 13 It has Figure 12The layout diagram of multiple data latch circuits arranged in the two-dimensional direction.

[0026] Figure 14A This is a layout diagram of a first variant of the data latch circuit according to the second embodiment.

[0027] Figure 14B This is the layout diagram for the second variation.

[0028] Figure 15A Multiple units with [specific features] are configured in both the first and second directions. Figure 14A The layout diagram of the data latch circuit is shown.

[0029] Figure 15B Multiple units with [specific features] are configured in both the first and second directions. Figure 14B The layout diagram of the data latch circuit is shown.

[0030] Figure 16A This is a diagram illustrating the features of a data latch circuit according to a third embodiment.

[0031] Figure 16B This is a circuit diagram of the data latch circuit according to the third embodiment.

[0032] Figure 16C It shows when Figure 16B A diagram showing the voltages of the word lines, bit lines, and control signals during the data latch circuit's reading, writing, and storage of data.

[0033] Figure 17 This is a layout diagram of the data latch circuit according to the third embodiment.

[0034] Figure 18 It has Figure 17 The layout diagram of multiple data latch circuits arranged in the two-dimensional direction.

[0035] Figure 19A This is a diagram illustrating the features of a data latch circuit according to a fourth embodiment.

[0036] Figure 19B This is a circuit diagram of the data latch circuit according to the fourth embodiment.

[0037] Figure 19C It shows when Figure 16B A diagram showing the voltages of the word lines, bit lines, and control signals during the data latch circuit's reading, writing, and storage of data.

[0038] Figure 20 This is a layout diagram of the data latch circuit according to the fourth embodiment.

[0039] Figure 21 It has Figure 20 The layout diagram of multiple data latch circuits arranged in the two-dimensional direction. Detailed Implementation

[0040] The following description, with reference to the accompanying drawings, details embodiments of the data latch circuit and semiconductor memory device. In this description, the main components of the data latch circuit and semiconductor memory device will be primarily described. The data latch circuit and semiconductor memory device may have components and functions not shown in the drawings or described in this specification. The following description does not exclude components or functions not shown in the drawings or described in this specification.

[0041] First Implementation Method

[0042] Figure 1 This is a block diagram illustrating a schematic configuration of a semiconductor memory device 1 including a data latch circuit 10 according to a first embodiment. Figure 1 The semiconductor memory device 1 shown in the diagram illustrates a schematic configuration of flash memory. The semiconductor memory device 1 according to this embodiment can be applied to various types of semiconductor memory other than flash memory. Specifically, the semiconductor memory device 1 according to this embodiment can be applied to non-volatile memory such as MRAM (magnetoresistive random access memory), and can also be applied to volatile memory such as DRAM (dynamic random access memory) and SRAM (static random access memory). Furthermore, the flash memory can be NAND flash memory or NOR flash memory, and the semiconductor memory device 1 according to this embodiment can be applied to both NAND flash memory and NOR flash memory. In the following description, an example of applying the semiconductor memory device 1 according to this embodiment to flash memory will be mainly described.

[0043] Figure 1 The semiconductor memory device 1 includes multiple memory modules 2, a serial conversion unit 3, an I / O signal processing unit 4, a high voltage generation circuit 5, a low voltage generation circuit 6, a synchronization control unit 7, a row control unit 8, and a column control unit 9.

[0044] Each of the memory modules 2 includes a memory cell array 11, a row decoder 12, a readout amplifier & data latch 13, a data transfer latch 14, and a column decoder 15.

[0045] The storage cell array 11 has a configuration that arranges multiple strings in a two-dimensional configuration, wherein the multiple strings have multiple NAND flash memory cells arranged therein in a common-source, common-gate (CAS) interconnection. A row decoder 12 decodes the row address signals and drives the corresponding word lines.

[0046] The sense amplifier and data latch unit 13 writes data to the memory cell array 11 via the bit line BL and reads data from the memory cell array 11. According to this embodiment, the sense amplifier and data latch unit 13 includes a data latch circuit (DL) 10, which is configured to store data to be written to the memory cell array 11 and to store data read from the memory cell array 11.

[0047] The data latch unit 14 temporarily stores data to be written to or read from the memory cell array 11. The data latch unit 14 also includes a data latch circuit 10 according to this embodiment.

[0048] The column decoder 15 performs prescribed arithmetic processing, including decoding of data to be written to or read from the memory cell array 11.

[0049] The serial converter 3 converts the data read from the memory cell array 11 into serial data and provides the converted data to the I / O signal processing unit 4. In addition, the serial converter 3 converts the serial data to be written and sent from the I / O signal processing unit 4 into parallel data and sends it to the column decoder 15.

[0050] The I / O signal processing unit 4 communicates with the controller 16 via high-speed serial communication. The high-voltage generation circuit 5 boosts the externally supplied power supply voltage VDD to generate high voltages VPGM, VERA, VPASS, etc., for use when writing or erasing data from the memory cell.

[0051] The low voltage generation circuit 6 generates the reference voltage, clock signal, low power supply voltage, etc. to be used in the semiconductor memory device 1.

[0052] The synchronization control unit 7 performs timing control, sequencing control and parameter control on each block in the semiconductor memory device 1.

[0053] The row control unit 8 controls the timing of the word lines driving each memory cell array 11. The column control unit 9 controls the timing of the bit lines driving each memory cell array 11.

[0054] As described above, the data latch circuit 10 according to this embodiment is provided with Figure 1 The data latch circuit 10 is located in the readout amplifier & data latch 13 and the data transfer latch 14 of the semiconductor memory device 1. According to this embodiment, the data latch circuit 10 can be provided in a location other than the readout amplifier & data latch 13 and the data transfer latch 14.

[0055] have Figure 1The block configuration of flash memory shown is currently the lowest-cost non-volatile memory and is commonly used as high-capacity memory in various applications. Figure 1 In the block configuration shown, components other than the memory cell array 11 can be referred to as peripheral circuitry. The data latch circuit 10 occupies most of the area of ​​the peripheral circuitry. The data latch circuit 10, serving as a temporary storage location, is configured to temporarily store data to be written to and read from the memory cell array 11.

[0056] In flash memories configured to change from a planar structure to a three-dimensional structure, bit density is increased by increasing the number of bits per cell, implementing multi-level cells (MLCs), and increasing the number of stacked word lines. Here, as bit density increases, the area of ​​the peripheral circuitry also increases.

[0057] When the ratio of the area of ​​the peripheral circuitry to the total area of ​​the flash memory chip increases, the number of bits per wafer decreases, and the cost per bit increases. As a solution to reduce the area of ​​the flash memory chip, CUA (CMOS under array) and CBA (CMOS bonded array) structures have been proposed, where the peripheral circuitry is located below the memory cell array 11. In the CBA structure, the wafer containing the memory cell array and the wafer containing the peripheral circuitry are bonded together. In both the CUA and CBA structures, when the area of ​​the peripheral circuitry is larger than the area of ​​the memory cell array 11, the area of ​​the flash memory chip also increases.

[0058] Therefore, the semiconductor memory device 1 according to this embodiment is characterized by a reduced area of ​​the data latch circuit 10 in the peripheral circuitry. Hereinafter, the circuit configuration of the general data latch circuit 100 according to the comparative example will be described first.

[0059] Figure 2 This is a circuit diagram of the data latch circuit 100 based on the comparative example. Figure 2 The data latch circuit 100 includes eight transistors Q1 to Q8. Of these eight transistors Q1 to Q8, four are NMOS transistors Q1 to Q4, and the remaining four are PMOS transistors Q5 to Q8.

[0060] The drain of transistor Q1 is connected to the gate of transistor Q2, the drain of transistor Q3, the drain of transistor Q7, and the gate of transistor Q8. The drain of transistor Q2 is connected to the gate of transistor Q1, the drain of transistor Q4, the gate of transistor Q7, and the drain of transistor Q8. The sources of transistors Q1 and Q2 are connected to the reference voltage node VSS (e.g., ground node).

[0061] Word line WL1 is connected to the gate of transistor Q3, and word line WL2 is connected to the gate of transistor Q4. Only one of word lines WL1 and WL2 goes high. The sources of transistors Q3 and Q4 are connected to bit line BL.

[0062] In this way, Figure 2 The data latch circuit 100 includes two word lines WL1 and WL2 and one bit line BL.

[0063] The source of transistor Q5 is connected to the power supply node VDD, and the drain of transistor Q5 is connected to the source of transistor Q7. The control signal Vctl is input to the gate of transistor Q5. The source of transistor Q6 is connected to the power supply node VDD, and the drain of transistor Q6 is connected to the source of transistor Q8. The control signal Vctl is input to the gate of transistor Q7. When the control signal Vctl is low, both transistors Q5 and Q6 are turned on. In this case, when word line WL1 or WL2 goes high, nodes n1 and n2 store data on bit line BL.

[0064] like Figure 2 As shown, the data latch circuit 100 according to the comparative example is formed by eight transistors Q1 to Q8. Therefore, as the number of data latch circuits 100 increases, the number of transistors increases by a factor of 8, which leads to an increase in the area of ​​the semiconductor memory device 1.

[0065] Figure 3A This is a diagram illustrating the features of the data latch circuit 10 according to the first embodiment. Figure 3B This is a circuit diagram of the data latch circuit 10 according to the first embodiment.

[0066] like Figure 3A As shown, the data latch circuit 10 according to the first embodiment has the following configuration: wherein, from according to Figure 2 In the comparative example, the data latch circuit 100 omits the first transistor group 21 including transistors Q5 and Q6, the second transistor group 22 including transistors Q7 and Q8, and VDD. Furthermore, the data latch circuit 10 according to the first embodiment includes PMOS transistors Q3a and Q4a, replacing... Figure 2 The NMOS transistors Q3 and Q4 in the diagram.

[0067] As described above, the data latch circuit 10 according to the first embodiment includes two NMOS transistors Q1 and Q2 and two PMOS transistors Q3a and Q4a.

[0068] like Figure 3BAs shown, the drain of transistor Q1 is connected to the gate of transistor Q2 and the source of transistor Q3a. This connection node is called node n1. The drain of transistor Q2 is connected to the gate of transistor Q1 and the source of transistor Q4a. This connection node is called node n2.

[0069] The sources of transistors Q1 and Q2 are connected to the ground node. The gate of transistor Q3a is connected to word line WL1, and the gate of transistor Q4a is connected to word line WL2. The drains of transistors Q3a and Q4a are connected to the bit line.

[0070] Figure 4A This diagram illustrates the operation of the data latch circuit 10 according to the first embodiment. The data latch circuit 10 according to the first embodiment performs data write operations, data storage operations, and data read operations. The two word lines WL1 and WL2 do not simultaneously become low. A data write operation is performed when one of the word lines WL1 and WL2 becomes high. For example, when word line WL1 is low and word line WL2 is high, transistor Q3a is turned on and transistor Q4a is turned off. Therefore, the voltage of bit line BL is transmitted to node n1 via transistor Q3a. For example, when bit line BL has a low voltage, node n1 also becomes low, and when bit line BL has a high voltage, node n1 also becomes high. Node n2 becomes the inverted logic voltage of node n1. Transistors Q1 and Q2 perform the operation of storing the potentials of nodes n1 and n2.

[0071] During data storage operations, both word lines WL1 and WL2 are set to a voltage level slightly lower than the supply voltage VDD. The bit line BL is set to VDD. A voltage level slightly lower than the supply voltage VDD is, for example, a voltage level 5% to 30% lower than the supply voltage VDD. Specifically, during data storage at nodes n1 and n2, the gate voltage levels of transistors Q3a and Q4a are reduced by the following percentage: any percentage within the range of 5% to 30% of the higher of the gate voltage levels of transistors Q3a and Q4a during data writing to nodes n1 and n2. The reason for setting word lines WL1 and WL2 to a voltage level slightly lower than the supply voltage VDD during data storage is to allow leakage current to flow through transistors Q3a and Q4a, whose gates are connected to word lines WL1 and WL2, respectively.

[0072] For example, when node n1 has a low voltage, transistor Q1 is turned on, and the voltage at node n1 is stored via transistor Q1 in the low voltage from the ground voltage node VSS, such as... Figure 4A The dashed arrow y1 is shown in the diagram. On the other hand, transistor Q2 is turned off, and the leakage current flowing from bit line BL through transistor Q4a stores the voltage at node n2 at a high voltage, as shown in the diagram. Figure 4A The dashed arrow y2 is shown in the figure.

[0073] In this way, word lines WL1 and WL2 are set to voltage levels slightly lower than the power supply voltage VDD, and bit line BL is set to VDD. Here, when node n1 has a high voltage, the leakage current flowing from bit line BL through transistor Q3a maintains the voltage level of node n1. Furthermore, when node n2 has a high voltage, the leakage current flowing from bit line BL through transistor Q4a maintains the voltage level of node n2.

[0074] Figure 4B It shows when Figure 4A The diagram shows the voltages of word lines WL1 and WL2 and bit line BL when the data latch circuit 10 reads, writes, and stores data. Figure 4B An example of accessing word line WL1 is shown. Here, when accessing word line WL2, Figure 4B The voltage relationship between the word lines WL1 and WL2 is reversed.

[0075] When the data latch circuit 10 reads data stored in nodes n1 and n2 via transistor Q3a, word line WL1 is set to ground voltage VSS (e.g., 0V), and word line WL2 is set to a voltage slightly lower than the power supply voltage VDD (e.g., VDD × 0.95-0.7V). Furthermore, bit line BL is pre-charged to the power supply voltage VDD. Therefore, data stored in nodes n1 and n2 is read via bit line BL via transistor Q3a.

[0076] When the data latch circuit 10 writes data to nodes n1 and n2 via transistor Q3a, word line WL1 is set to ground voltage VSS (e.g., 0V), and word line WL2 is set to power supply voltage VDD. When the data to be written is 0, bit line BL is set to ground voltage VSS (e.g., 0V). Therefore, data of "0" is stored in nodes n1 and n2 via transistor Q3a. Simultaneously, when the data to be written is 1, bit line BL is set to power supply voltage VDD.

[0077] When the data latch circuit 10 stores data in nodes n1 and n2, word lines WL1 and WL2 are set to a voltage slightly lower than the power supply voltage VDD (e.g., VDD × 0.95-0.7V), and bit line BL is set to the power supply voltage VDD.

[0078] Figure 5 This is a diagram illustrating the storage characteristics of the semiconductor memory device 1 according to the first embodiment. Figure 5 The horizontal axis in the graph represents the voltage level at node n2. Figure 5 The vertical axis represents the voltage level of node n1. Figure 5Curve w1 shows the change in voltage level at node n1 relative to the voltage at node n2, and curve w2 shows the change in voltage level at node n2 relative to the voltage at node n1. Figure 5 As shown in the diagram, nodes n1 and n2 are stable at points p1 and p2, respectively, and exhibit good storage characteristics. At point p1, the voltage level of node n1 is the power supply voltage VDD. At point p2, the voltage level of node n2 is the power supply voltage VDD.

[0079] Figure 6 This is a layout diagram of the data latch circuit 10 according to the first embodiment, and Figure 7 It is a display Figure 6 A cross-sectional view of the stacking position of each layer. (e.g.) Figure 7 As shown, the data latch circuit 10 according to the first embodiment is formed by stacking multiple layers with different layer heights, and includes multiple contacts CT0 and CT1 configured to electrically connect the respective layers. Figure 6 The diagram shows a planar structure of multiple layers with different layer heights as viewed in the stacking direction. The layout and cross-sectional views of the data latch circuit 10 according to the first embodiment are not necessarily limited to... Figure 6 and Figure 7 As shown in the diagram. Figure 6 The black and gray circles in the diagram represent contacts.

[0080] exist Figure 6 and Figure 7 In the example, the first diffusion region D1 and the second diffusion region D2 are located at the bottom layer. The first diffusion region D1 and the second diffusion region D2 can be referred to as the active region. The first diffusion region D1 and the second diffusion region D2 are separated from each other in the first direction X. The source and drain regions of transistors Q1 and Q2 are formed in the first diffusion region D1. The source and drain regions of transistors Q3a and Q4a are formed in the second diffusion region D2. The first diffusion region D1 and the second diffusion region D2 are formed by implanting impurity ions such as boron (B), phosphorus (P), and arsenic (As) into the semiconductor substrate and thermally diffusing them therein.

[0081] A first gate layer G1 connected to the gate of transistor Q3a and a second gate layer G2 connected to the gate of transistor Q4a are located on the second diffusion region D2 separated by an insulating layer. A third gate layer G3 connected to the gate of transistor Q1 and a fourth gate layer G4 connected to the gate of transistor Q2 are located on the first diffusion region D1 separated by an insulating layer.

[0082] The first gate layer G1 to the fourth gate layer G4 are located at the same layer height. Specifically, each of the first gate layer G1 to the fourth gate layer G4 extends in the second direction Y. Furthermore, the first gate layer G1 to the fourth gate layer G4 are separated from each other in the first direction X.

[0083] A first metal layer M1 is located on the first gate layer G1 to the fourth gate layer G4, separated by an insulating layer. The first metal layer M1 is made of tungsten (W), copper (Cu), aluminum (Al), etc. The first metal layer M1 includes a first wiring layer WR1, a second wiring layer WR2, a third wiring layer WR3, and a fourth wiring layer WR4, each wiring layer extending in a first direction X. Here, the first wiring layer WR1 to the fourth wiring layer WR4 are separated from each other in a second direction Y.

[0084] The first wiring layer WR1 is a bit line BL connected to the drain of transistor Q3a and the drain of transistor Q4a. The second wiring layer WR2 is connected to the drain of transistor Q1, the fourth gate layer G4, and the source of transistor Q3a. The third wiring layer WR3 is connected to the drain of transistor Q2, the third gate layer G3, and the source of transistor Q4a.

[0085] The fourth wiring layer WR4 is connected to the source regions of transistors Q1 and Q2 in the first diffusion region D1.

[0086] The second metal layer M2 is located on the first metal layer M1 through an insulating layer. The second metal layer M2 is made of tungsten (W), copper (Cu), aluminum (Al), etc.

[0087] The second metal layer M2 has a fifth wiring layer WR5. The fifth wiring layer WR5 is set to ground voltage VSS (first reference voltage). The fifth wiring layer WR5 is located above the first diffusion region D1 and extends in the second direction Y. The fifth wiring layer WR5 is connected to the fourth wiring layer WR4. Therefore, the fourth wiring layer WR4 is set to ground voltage VSS. Furthermore, since the fourth wiring layer WR4 is connected to the source regions of transistors Q1 and Q2 in the first diffusion region D1, these source regions are also set to ground voltage VSS.

[0088] Figure 6 The first diffusion region D1, the second diffusion region D2, the first gate layer G1 to the fourth gate layer G4, and the first wiring layer WR1 to the second wiring layer WR4 are arranged symmetrically.

[0089] Figure 8 It has Figure 6 The layout diagram shows the arrangement of multiple data latch circuits 10 in a two-dimensional direction. Figure 8 In the middle, having Figure 6 Multiple data latch circuits 10 are arranged in the layout along the first direction X and the second direction Y. The multiple data latch circuits located in the second direction Y share word lines WL1 and WL2. The multiple data latch circuits 10 located in the first direction X share bit line BL.

[0090] Figure 6 and Figure 8The layout shown is merely an example, and various variations can be considered. For instance, a point-symmetric layout configuration can be used.

[0091] Figure 9A This is a layout diagram of a first modified example of the data latch circuit 10 according to the first embodiment. Figure 9B This is the layout diagram of its second variation. Figure 9A and 9B All of them have a point-symmetric layout about the center of the layout area. Figure 9B In the configuration, Figure 9A The layout is staggered to the left or right by half a cycle. The following description will describe... Figure 9A The details of the layout are omitted. Figure 9B The description of the layout and arrangement. Figure 9A and Figure 9B The hierarchical relationship between the multiple layers shown in the figure is as follows: Figure 7 same.

[0092] exist Figure 9A In the layout, the first diffusion region D1, the second diffusion region D2, the third diffusion region D3, and the fourth diffusion region D4 are separated from each other in the second direction Y in the lowest layer. Each of the first diffusion region D1 to the fourth diffusion region D4 extends in the first direction X. The first gate layer G1, the second gate layer G2, the third gate layer G3, and the fourth gate layer G4 are separated from each other in the second direction Y above the first diffusion region D1 to the second diffusion region D4.

[0093] The first gate layer G1 overlaps with the second diffusion region D2 in the stacking direction. The second gate layer G2 overlaps with the third diffusion region D3 in the stacking direction. The third gate layer G3 overlaps with the first diffusion region D1 in the stacking direction. The fourth gate layer G4 overlaps with the fourth diffusion region D4 in the stacking direction.

[0094] The first metal layer M1 is located above the first gate layers G1 to the fourth gate layers G4. In the first metal layer M1, the second wiring layers WR2 to the ninth wiring layers WR9 are separated from each other in the first direction X. Each of the second wiring layers WR2 to the fifth wiring layers WR5 extends in the second direction Y.

[0095] The second wiring layer WR2 is word line WL1, connected to the first gate layer G1. The third wiring layer WR3 is word line WL2, connected to the second gate layer G2. The fourth wiring layer WR4 is connected to the drain region of transistor Q1 in the first diffusion region D1, the source region of transistor Q3a in the second diffusion region D2, and the fourth gate layer G4. The fifth wiring layer WR5 is connected to the third gate layer G3, the source region of transistor Q4a in the third diffusion region D3, and the drain region of transistor Q2 in the fourth diffusion region D4. The sixth wiring layer WR6 is connected to the source region of transistor Q1 in the first diffusion region D1. The seventh wiring layer WR7 is connected to the drain region of transistor Q3a in the second diffusion region D2. The eighth wiring layer WR8 is connected to the drain region of transistor Q2 in the fourth diffusion region D4. The ninth wiring layer WR9 is connected to the drain region of transistor Q4a in the third diffusion region D3.

[0096] The second metal layer M2 is located above the first metal layer M1, which includes the second wiring layer WR2 to the fifth wiring layer WR5. The second metal layer M2 includes the first wiring layer WR1, the tenth wiring layer WR10, and the eleventh wiring layer WR11. The first wiring layer WR1 is the bit line BL, and the tenth wiring layer WR10 and the eleventh wiring layer WR11 are wiring layers configured to ground voltage VSS.

[0097] The first routing layer WR1 is located between the second diffusion region D2 and the third diffusion region D3. The tenth routing layer WR10 is located near the first diffusion region D1. The eleventh routing layer WR11 is located near the fourth diffusion region D4.

[0098] The first routing layer WR1 is connected to the seventh routing layer WR7, and also to the ninth routing layer WR9. The tenth routing layer WR10 is connected to the sixth routing layer WR6. The eleventh routing layer WR11 is connected to the eighth routing layer WR8.

[0099] Figure 10A It has Figure 9A The layout diagram shows the arrangement of multiple data latch circuits 10 in the first direction X and the second direction Y. Figure 10B Multiple [equipment / functions] are configured in the first direction X and the second direction Y respectively. Figure 9B The layout diagram of multiple data latch circuits 10 in the middle.

[0100] Figure 10A and 10B All have Figure 9A and 9B The units are arranged in a point-symmetric layout and have a layout that is symmetric with respect to the axis extending along the second direction Y.

[0101] As described above, the data latch circuit 10 according to the first embodiment is formed by four transistors Q1, Q2, Q3a and Q4a, thereby connecting with the data latch circuit according to the first embodiment. Figure 2 Compared to the comparative example data latch circuit 100 shown, the circuit area is significantly reduced. Data is stored in nodes n1 and n2, and during data storage, a voltage slightly lower than the power supply voltage VDD is applied to word lines WL1 and WL2, thus the leakage current from the bit line BL can be used to stably store data in nodes n1 and n2. The data latch circuit 10 according to the first embodiment can be located as follows... Figure 6 In the linearly symmetrical layout shown, the following can also be used: Figure 9A or Figure 9B The points shown are arranged symmetrically.

[0102] Second Implementation Method

[0103] Although the data latch circuit 10 according to the first embodiment includes two word lines WL1 and WL2 and one bit line BL, each of which is connected to its corresponding component, the data latch circuit 10 may also have a configuration including one word line BL and two bit lines BL and bBL, each of which is connected to its corresponding component.

[0104] Figure 11A This is a diagram illustrating the features of the data latch circuit 10a according to the second embodiment. Figure 11B This is a circuit diagram of the data latch circuit 10a according to the second embodiment.

[0105] In the data latch circuit 10a according to the second embodiment, a word line WL and two bit lines BL and bBL are provided, each of which is connected to a corresponding component of the data latch circuit 10a. The common word line WL is connected to the gates of transistors Q3a and Q4a. The bit line BL is connected to the drain of transistor Q3a, and the bit line bBL is connected to the drain of transistor Q4a. The bit lines BL and bBL have logic levels opposite to each other. The connection relationships between the other transistors Q1 to Q4a are as follows. Figure 3A and 3B same.

[0106] Figure 11C It shows when Figure 11B The diagram shows the voltages of the word line WL, bit line BL, and bBL when the data latch circuit 10a reads, writes, and stores data.

[0107] When the data latch circuit 10a reads data stored in nodes n1 and n2, the word line WL is set to ground voltage VSS (e.g., 0V). Bit lines BL and bBL are pre-charged to the power supply voltage VDD. Therefore, the data stored in nodes n1 and n2 is read into bit lines BL and bBL via transistors Q3a and Q4a in reverse logic.

[0108] When data is written to nodes n1 and n2, the word line WL is set to ground voltage VSS (e.g., 0V). When the data to be written is 0, the bit line BL is set to ground voltage VSS (e.g., 0V), and the bit line bBL is set to the power supply voltage VDD. Therefore, transistors Q1 and Q2 perform the operation of storing "0" data. Meanwhile, when the data to be written is 1, the voltage levels of bit lines BL and bBL are... Figure 11C The voltage levels are opposite.

[0109] When storing data in nodes n1 and n2, the word line WL is set to a voltage slightly lower than the power supply voltage VDD (e.g., VDD × 0.95-0.7V), and the bit lines BL and bBL are set to the power supply voltage VDB.

[0110] Figure 12 This is a layout diagram of the data latch circuit 10a according to the second embodiment. Figure 12 The hierarchical relationship between the multiple layers shown is as follows: Figure 7 same.

[0111] exist Figure 12 In the layout, the first diffusion zone D1, the second diffusion zone D2, and the third diffusion zone D3 are located at the lowest layer. The first diffusion zone D1 and the second diffusion zone D2 are separated from each other in the second direction Y. The third diffusion zone D3 is separated from the first diffusion zone D1 and the second diffusion zone D2 in the first direction X.

[0112] A first gate layer G1, a second gate layer G2, and a third gate layer G3 are located on first diffusion regions D1 to third diffusion regions D3. The first gate layer G1 to the third gate layer G3 have the same layer height. The first gate layer G1 is a word line. The first gate layer G1 overlaps with the first diffusion region D1 and the second diffusion region D2 in the stacking direction. The first gate layer G1 is the layer connected to the gates of transistors Q3a and Q4a.

[0113] The second gate layer G2 and the third gate layer G3 overlap with the third diffusion region D3 in the stacking direction. The second gate layer G2 is the layer connected to the gate of transistor Q1. The third gate layer G3 is the layer connected to the gate of transistor Q2.

[0114] The first metal layer M1 is located on the first gate layer G1 to the third gate layer G3. The first metal layer M1 includes a first wiring layer WR1, a second wiring layer WR2, a third wiring layer WR3, a fourth wiring layer WR4, and a fifth wiring layer WR5. Here, the first wiring layer WR1 to the fifth wiring layer WR5 extend in the first direction X and are separated from each other in the second direction Y.

[0115] The first wiring layer WR1 is bit line BL, and the second wiring layer WR2 is bit line bBL. The first wiring layer WR1 overlaps with the first diffusion region D1 and the third diffusion region D3 in the stacking direction. The first wiring layer WR1 is connected to the drain region of transistor Q3a in the first diffusion region D1. The second wiring layer WR2 overlaps with the second diffusion region D2 and the third diffusion region D3 in the stacking direction. The second wiring layer WR2 is connected to the drain region of transistor Q4a in the second diffusion region D2.

[0116] The third wiring layer WR3 overlaps with the first diffusion region D1 and the third diffusion region D3 in the stacking direction. The third wiring layer WR3 is connected to the source region of transistor Q3a in the first diffusion region D1, the drain region of transistor Q1 in the third diffusion region D3, and the third gate layer G3.

[0117] The fourth wiring layer WR4 overlaps with the second diffusion region D2 and the third diffusion region D3 in the stacking direction. The fourth wiring layer WR4 is connected to the source region of transistor Q4a in the second diffusion region D2, the second gate layer G2 in the third diffusion region D3, and the drain region of transistor Q2 in the third diffusion region D3.

[0118] The fifth wiring layer WR5 overlaps with the third diffusion region D3 in the stacking direction. The fifth wiring layer WR5 is connected to the source regions of transistors Q1 and Q2 in the third diffusion region D3.

[0119] The second metal layer M2 is located on the first wiring layers WR1 to the fifth wiring layers WR5. The second metal layer M2 includes a sixth wiring layer WR6. The sixth wiring layer WR6 is set to ground voltage VSS. The sixth wiring layer WR6 is connected to the fifth wiring layer WR5.

[0120] Figure 13 It has Figure 12 The layout diagram shows the arrangement of multiple data latch circuits 10a in a two-dimensional direction. Figure 13 In the middle, multiple data latch circuits 10a are arranged symmetrically with respect to axes ax1 and ax2 extending along the second direction Y.

[0121] Figure 12 The layout shown is just an example, and various variations can be considered. For example, a point-symmetric layout can be used.

[0122] Figure 14A This is a layout diagram of a first modified example of the data latch circuit 10a according to the second embodiment. Figure 14B This is the layout diagram of its second variation. Figure 14A and Figure 14B A point-symmetric layout with respect to the center of the layout area. This will be described below. Figure 14A The details of the layout are omitted. Figure 14B The description of the layout and arrangement. Figure 14A and 14B The hierarchical relationship between the multiple layers shown is Figure 7 same.

[0123] exist Figure 14A In the layout arrangement, the first diffusion region D1, the second diffusion region D2, the third diffusion region D3, and the fourth diffusion region D4 are separated from each other in the second direction Y in the lowest layer. Each of the first diffusion region D1 to the fourth diffusion region D4 extends in the first direction X. The first gate layer G1, the second gate layer G2, the third gate layer G3, and the fourth gate layer G4 are separated from each other in the second direction Y on the first diffusion region D1 to the second diffusion region D4.

[0124] The first gate layer G1 overlaps with the second diffusion region D2 in the stacking direction. The second gate layer G2 overlaps with the third diffusion region D3 in the stacking direction. The third gate layer G3 overlaps with the first diffusion region D1 in the stacking direction. The fourth gate layer G4 overlaps with the fourth diffusion region D4 in the stacking direction.

[0125] The first metal layer M1 is located on the first gate layer G1 to the fourth gate layer G4. In the first metal layer M2, the third wiring layer WR3 to the ninth wiring layer WR9 are separated from each other in the first direction X. Each of the third wiring layer WR3 to the ninth wiring layer WR9 extends in the second direction Y.

[0126] The third wiring layer WR3 is connected to the first gate layer G1 and the second gate layer G2. The fourth wiring layer WR4 is connected to the first diffusion region D1, the second diffusion region D2, and the fourth diffusion region D4. The fifth wiring layer WR5 is connected to the first diffusion region D1, the third diffusion region D3, and the fourth diffusion region D4. The sixth wiring layer WR6 is connected to the first diffusion region D1. The seventh wiring layer WR7 is connected to the second diffusion region D2. The eighth wiring layer WR8 is connected to the fourth diffusion region D4. The ninth wiring layer WR9 is connected to the third diffusion region D3.

[0127] The second metal layer M2 is located on the first metal layer M1, which includes the third wiring layer WR3 to the ninth wiring layer WR9. In the second metal layer M2, the first wiring layer WR1, the second wiring layer WR2, the tenth wiring layer WR10, and the eleventh wiring layer WR11 are separated from each other in the second direction Y. The first wiring layer WR1 is a bit line BL, and the second wiring layer WR2 is a bit line bBL. The tenth wiring layer WR10 and the eleventh wiring layer WR11 are layers configured to be grounded at voltage VSS.

[0128] The tenth routing layer WR10 is connected to the sixth routing layer WR6. The first routing layer WR1 is connected to the seventh routing layer WR7. The eleventh routing layer WR11 is connected to the eighth routing layer WR8. The second routing layer WR2 is connected to the ninth routing layer WR9.

[0129] Figure 15A It has Figure 14A The layout diagram shows the arrangement of multiple data latch circuits 10a in the first direction X and the second direction Y. Figure 15B Multiple units with [specific features] are configured in the first direction X and the second direction Y. Figure 14B The layout diagram of the data latch circuit 10a is shown.

[0130] Figure 15A and 15B All have Figure 14A and 14B The unit has a point-symmetric layout and also has a line-symmetric layout about an axis extending along the second direction Y.

[0131] As described above, in the same manner as the first embodiment, the data latch circuit 10a according to the second embodiment is formed by four transistors Q1 to Q4a, thereby being consistent with the second embodiment. Figure 2 Compared to the comparative example data latch circuit 100 shown, the circuit area is significantly reduced. The data latch circuit 10a according to the second embodiment can have… Figure 12 The point-symmetric layout shown can also have Figure 14A or Figure 14B The layout shown is linearly symmetrical.

[0132] Third Implementation Method

[0133] In the first and second embodiments described above, a data latch circuit 10 comprising four transistors Q1 to Q4a is described. Alternatively, a data latch circuit 10b comprising six transistors may also be provided. Two additional transistors determine whether to supply a power supply voltage VDD to the data latch circuit 10b. That is, the two additional transistors enable a determination of whether the data latch circuit 10b is performing a data storage operation or a data reading operation.

[0134] Figure 16A This is a diagram illustrating the features of the data latch circuit 10b according to the third embodiment. Figure 16B This is a circuit diagram of the data latch circuit 10a according to the third embodiment. The data latch circuit 10b according to the third embodiment has the following configuration: wherein, from according to... Figure 2In the comparative example of the data latch circuit 100, the second transistor group 22, including transistors Q7 and Q8, is omitted. Transistors Q1 to Q4 are NMOS transistors, and transistors Q5 and Q6 are PMOS transistors.

[0135] like Figure 16B As shown, the source of transistor Q5 is connected to the power supply voltage node VDD. The drain of transistor Q5 is connected to the drain of transistor Q1, the gate of transistor Q2, and the drain of transistor Q3. The source of transistor Q6 is connected to the power supply voltage node VDD, and the drain of transistor Q6 is connected to the drain of transistor Q2, the gate of transistor Q1, and the drain of transistor Q4.

[0136] A common control signal Vct1 is input to the gates of transistors Q5 and Q6. During data storage, Vct1 is set to a voltage level slightly lower than the supply voltage VDD. For example, a voltage level slightly lower than the supply voltage VDD is a voltage level that is 5% to 30% lower than the supply voltage VDA. The reason for setting the gate voltage Vct1 of transistors Q5 and Q6 slightly lower than the supply voltage VDD during data storage is to allow leakage current to flow through transistors Q5 and Q6.

[0137] From the data storage state, one of the word lines WL1 and WL2 is set to high and the other is set to low, thereby enabling one of the transistors Q3 and Q4 to be turned on, and the state of node n1 or node n2 is read from the bit line.

[0138] When a high-level control signal is input to the gates of transistors Q5 and Q6, transistors Q5 and Q6 are turned off. In this state, one of the word lines WL1 and WL2 is set to high and the other is set to low, thereby turning on one of transistors Q3 and Q4 and writing the data on the bit line to nodes n1 and n2.

[0139] When a low-level control signal is input to the gates of transistors Q5 and Q6, transistors Q5 and Q6 are turned on, and the drains of transistors Q1 and Q2 become the power supply voltage VDD. This action can also be used to initialize the states of nodes n1 and n2.

[0140] Figure 16C It shows when Figure 16B The diagram shows the voltages of word lines WL1 and WL2, bit line BL, and control signal Vct1 during data latching circuit 10b reading, writing, and storing data. Figure 16C An example of accessing word line WL1 is shown. When accessing word line WL2... Figure 16C The voltage relationship between word lines WL1 and WL2 in the middle is reversed.

[0141] When the data latch circuit 10b reads data stored in nodes n1 and n2 via transistor Q3, word line WL1 is set to the power supply voltage VDD, and word line WL2 is set to ground voltage VSS. Furthermore, bit line BL is pre-charged to the power supply voltage VDD. Additionally, the control signal Vct1 is set to a voltage slightly lower than the power supply voltage VDD (e.g., VDD × 0.95-0.7). Therefore, data stored in nodes n1 and n2 is read to bit line BL via transistor Q3.

[0142] When the data latch circuit 10b writes data to nodes n1 and n2 via transistor Q3, word line WL1 is set to the power supply voltage VDD, and word line WL2 is set to the ground voltage VSS (e.g., 0V). When the data to be written is 0, bit line BL is set to the ground voltage VSS (e.g., 0V). Furthermore, the control signal Vct1 is set to the power supply voltage VDD. Therefore, data of "0" is stored in nodes n1 and n2 via transistor Q3. Simultaneously, when the data to be written is 1, bit line BL is set to the power supply voltage VDD.

[0143] When the data latch circuit 10b stores data in nodes n1 and n2, word lines WL1 and WL2 are set to a voltage slightly lower than the power supply voltage VDD (e.g., VDD × 0.95-0.7V), and bit line BL is set to the power supply voltage VDD. Furthermore, the control signal Vctl is set to a voltage slightly lower than the power supply voltage VDD (e.g., VDD × 0.95-0.7V).

[0144] Figure 17 This is a layout diagram of the data latch circuit 10b according to the third embodiment. The third embodiment has the following configuration: multiple layers with different layer heights are stacked on top of each other, and multiple contacts configured to electrically connect the respective layers are provided. Figure 17 The hierarchical relationship between the layers of the data latch circuit 10b is formed and Figure 7 The same as in.

[0145] exist Figure 17 In the layout, the first diffusion zone D1, the second diffusion zone D2, and the third diffusion zone D3 are located at the lowest layer. The first diffusion zone D1 and the second diffusion zone D2 are separated from each other in the second direction Y. The third diffusion zone D3 is separated from the first diffusion zone D1 and the second diffusion zone D2 in the first direction X.

[0146] The first gate layer G1, the second gate layer G2, the third gate layer G3, the fourth gate layer G4, and the fifth gate layer G5 are located on the first diffusion region D1 to the third diffusion region D3. The first gate layer G1 to the fifth gate layer G5 extend in the second direction Y, are separated from each other in the first direction X, and are located at the same layer height.

[0147] The first gate layer G1 is the word line WL1 and is connected to the gate of transistor Q3. The first gate layer G1 overlaps with the third diffusion region D3 in the stacking direction. The second gate layer G2 is the word line WL2 and is connected to the gate of transistor Q4. The second gate layer G2 overlaps with the third diffusion region D3 in the stacking direction.

[0148] The third gate layer G3 is connected to the gate of transistor Q1. The fourth gate layer G4 is connected to the gate of transistor Q2. The fifth gate layer G5 is connected to the gates of transistors Q5 and Q6.

[0149] The second wiring layer WR2 to the eleventh wiring layer WR11 are located on the first gate layer G1 to the fifth gate layer G5. The second wiring layer WR2 to the eleventh wiring layer WR11 extend in the second direction Y and are separated from each other in the first direction X.

[0150] The second wiring layer WR2 is set to the power supply voltage (second reference voltage) VDD. The third wiring layer WR3 is connected to the drain region of transistor Q5 in the first diffusion region D1. The fourth wiring layer WR4 is connected to the drain of transistor Q6 in the second diffusion region D2. The third wiring layer WR3 and the fourth wiring layer WR4 are separated from each other in the second direction Y.

[0151] The fifth wiring layer WR5 is set to ground voltage VSS. The sixth wiring layer WR6 is connected to the gate of transistor Q1. The seventh wiring layer WR7 is connected to the source region of transistor Q3 in the third diffusion region D3. The eighth wiring layer WR8 is connected to the first wiring layer WR1. The ninth wiring layer WR9 is connected to the drain region of the second transistor in the third diffusion region D3. The tenth wiring layer WR10 is connected to the twelfth wiring layer WR12. The eleventh wiring layer WR11 is set to ground voltage VSS.

[0152] The first wiring layer WR1, the twelfth wiring layer WR12, and the thirteenth wiring layer WR13 are located on the second wiring layer WR2 to the eleventh wiring layer WR11. The first wiring layer WR1, the twelfth wiring layer WR12, and the thirteenth wiring layer WR13 extend in the first direction X and are separated from each other in the second direction Y.

[0153] The first routing layer WR1 is the bit line BL and is connected to the eighth routing layer WR8. The twelfth routing layer WR12 is connected to the third routing layer WR3, the seventh routing layer WR7, and the tenth routing layer WR10. The thirteenth routing layer WR13 is connected to the fourth routing layer WR4, the sixth routing layer WR6, and the ninth routing layer WR9.

[0154] Figure 18 It has Figure 17The layout diagram shows the arrangement of multiple data latch circuits 10b in a two-dimensional direction. Figure 18 In this configuration, multiple data latch circuits 10b are arranged linearly symmetrically with respect to an axis extending along the second direction Y.

[0155] Figure 17 The layout shown is just an example, and various variations can be considered. For example, a point-symmetric layout can also be used.

[0156] As described above, the data latch circuit 10b according to the third embodiment is formed by six transistors Q1 to Q6, thereby connecting with the data latch circuit according to the third embodiment. Figure 2 Compared to the data latch circuit 100 of the comparative example shown, the circuit area can be reduced. Furthermore, unlike the first and second embodiments, during data storage, it is not necessary to set the word line voltage to a voltage slightly lower than the power supply voltage VDD; therefore, word line control becomes easier.

[0157] Fourth Implementation Method

[0158] Although the data latch circuit 10b according to the third embodiment includes two word lines WL1 and WL2 and one bit line BL, each of which is connected to its corresponding component, the data latch circuit 10b may also have a configuration including one word line BL and two bit lines BL-bBL, each of which is connected to its corresponding component.

[0159] Figure 19A This is a diagram illustrating the features of the data latch circuit 10c according to the fourth embodiment. Figure 19B This is a circuit diagram of the data latch circuit 10c according to the fourth embodiment.

[0160] The data latch circuit 10c according to the fourth embodiment includes a word line WL and two bit lines BL and bBL, each connected to its corresponding component. The common word line WL is connected to the gates of transistors Q3 and Q4. The bit line BL is connected to the drain of transistor Q3, and the bit line bBL is connected to the drain of transistor Q4. The bit lines BL and bBL are in opposite logic. The connection relationships between the other transistors Q1 to Q4 are as follows: Figure 3A and 3B The same.

[0161] Figure 19C It shows when Figure 19B The diagram shows the voltages of the word line WL, bit line BL and bBL, and control signal Vct1 during the data latch circuit 10c in the middle when reading, writing and storing data.

[0162] When the data latch circuit 10c reads data stored in nodes n1 and n2, the word line WL is set to the power supply voltage VDD. Bit lines BL and bBL are pre-charged to the power supply voltage VDD. Furthermore, the control signal Vctl is set to a voltage slightly lower than the power supply voltage VDD (e.g., VDD × 0.95-0.7V). Therefore, the data stored in nodes n1 and n2 is read to bit lines BL and bBL via transistors Q3 and Q4 in reverse logic.

[0163] When the data latch circuit 10c writes data to nodes n1 and n2, the word line WL is set to the power supply voltage VDD. When the data to be written is 0, the bit line BL is set to ground voltage VSS (e.g., 0V), and the bit line bBL is set to the power supply voltage VDD. The control signal Vct1 is set to the power supply voltage VDD. Therefore, transistors Q1 and Q2 perform the operation of storing "0" data. Simultaneously, when the data to be written is 1, the voltage levels of bit lines BL and bBL are... Figure 19C The voltage levels are opposite.

[0164] When the data latch circuit 10c stores data in nodes n1 and n2, the word line WL is set to the ground voltage VSS (e.g., 0V), and the bit lines BL and bBL are set to the power supply voltage VDD. Additionally, the control signal Vct1 is set to a voltage slightly lower than the power supply voltage VDD (e.g., VDD × 0.95-0.7V).

[0165] Figure 20 This is a layout diagram of the data latch circuit 10c according to the fourth embodiment. Figure 20 The hierarchical relationship between the multiple layers shown is as follows: Figure 7 The same as in.

[0166] exist Figure 20 In the layout, the first diffusion zone D1, the second diffusion zone D2, and the third diffusion zone D3 are located at the lowest layer. The first diffusion zone D1 and the second diffusion zone D2 are separated from each other in the second direction Y. The third diffusion zone D3 is separated from the first diffusion zone D1 and the second diffusion zone D2 in the first direction X.

[0167] The first gate layer G1, the second gate layer G2, the third gate layer G3, the fourth gate layer G4, and the fifth gate layer G5 are located on the first diffusion region D1 to the third diffusion region D3. The first gate layer G1 to the fifth gate layer G5 extend in the second direction Y and are separated from each other in the first direction X at the same layer height.

[0168] The first gate layer G1 is a word line WL and is connected to the gate of transistor Q3. The first gate layer G1 overlaps with the third diffusion region D3 in the stacking direction. The second gate layer G2 is also a word line WL and is connected to the gate of transistor Q4. The second gate layer G2 is a word line WL and overlaps with the third diffusion region D3 in the stacking direction. Since the first gate layer G1 and the second gate layer G2 have the same word line WL, the first gate layer G1 and the second gate layer G2 can be integrated into a single gate layer.

[0169] The third gate layer G3 is connected to the gate of transistor Q1. The fourth gate layer G4 is connected to the gate of transistor Q2. The fifth gate layer G5 is connected to the gates of transistors Q5 and Q6.

[0170] The third wiring layer WR3 to the twelfth wiring layer WR12 are located on the first gate layer G1 to the fifth gate layer G5. The third wiring layer WR3 to the twelfth wiring layer WR12 extend in the second direction Y and are separated from each other in the first direction X.

[0171] The third wiring layer WR3 is set to the power supply voltage VDD. The fourth wiring layer WR4 is connected to the drain region of transistor Q5 in the first diffusion region D1. The fifth wiring layer WR5 is connected to the drain of transistor Q6 in the second diffusion region D2. The fourth wiring layer WR4 and the fifth wiring layer WR5 are separated from each other in the second direction Y.

[0172] The sixth wiring layer WR6 is connected to the source region of transistor Q3 in the third diffusion region D3. The seventh wiring layer WR7 is connected to the drain region of transistor Q3 in the third diffusion region D3. The eighth wiring layer WR8 is connected to the gate of transistor Q1. The ninth wiring layer WR9 is set to ground voltage VSS. The tenth wiring layer WR10 is connected to the gate of transistor Q2. The eleventh wiring layer WR11 is connected to the drain region of transistor Q4 in the third diffusion region D3. The twelfth wiring layer WR12 is connected to the source region of transistor Q4 in the third diffusion region D3.

[0173] The first wiring layer WR1, the second wiring layer WR2, the thirteenth wiring layer WR13, and the fourteenth wiring layer WR14 are located on the third wiring layer WR3 to the twelfth wiring layer WR12. The first wiring layer WR1, the second wiring layer WR2, the thirteenth wiring layer WR13, and the fourteenth wiring layer WR14 extend in the first direction X and are separated from each other in the second direction Y.

[0174] The first routing layer WR1 is the bit line BL and is connected to the sixth routing layer WR6. The second routing layer WR2 is the bit line bBL and is connected to the twelfth routing layer WR12. The thirteenth routing layer WR13 is connected to the fourth routing layer WR4, the seventh routing layer WR7, and the tenth routing layer WR10. The fourteenth routing layer WR14 is connected to the fifth routing layer WR5, the eighth routing layer WR8, and the eleventh routing layer WR11.

[0175] Figure 21 It has Figure 20 The layout diagram of multiple data latch circuits 10c arranged in the middle is located in a two-dimensional direction. Figure 21 The multiple data latch circuits 10c shown are arranged linearly symmetrically with respect to an axis extending along the second direction Y.

[0176] Figure 21 The layout shown is just an example, and various variations can be considered. For example, a point-symmetric layout can be used.

[0177] As described above, since the data latch circuit 10c according to the fourth embodiment is formed by six transistors Q1 to Q6, the same effect as the third embodiment can be obtained.

[0178] Furthermore, each of the embodiments described above can be applied and used even in environments with temperatures of 50°C or lower, room temperature, or temperatures below that level achieved through methods such as immersion. Each of these embodiments can also be applied and used in extremely low-temperature environments, such as -40°C or lower up to -196°C at liquid nitrogen temperatures.

[0179] While certain embodiments have been described, they are presented by way of example only and are not intended to limit the scope of this disclosure. In fact, the novel embodiments described herein can be embodied in various other forms; furthermore, various omissions, substitutions, and changes can be made to the forms of the embodiments described herein without departing from the spirit of this disclosure. The appended claims and their equivalents are intended to cover these forms or variations that fall within the scope and spirit of this disclosure.

[0180] Label Explanation

[0181] 1: Semiconductor memory devices

[0182] 2: Memory module

[0183] 3: Serial conversion unit

[0184] 4: I / O Signal Processing Unit

[0185] 5: High-voltage generating circuit

[0186] 6: Low-voltage generation circuit

[0187] 7: Synchronization Control Unit

[0188] 8: Line Control Department

[0189] 9: Train Control Department

[0190] 10, 10a, 10b, 10c: Data latch circuits

[0191] 11: Memory cell array

[0192] 12: Line Decoder

[0193] 13: Readout Amplifier & Data Latch

[0194] 14: Data Latching Unit

[0195] 15: Column Decoder

[0196] 16: Controller

[0197] 21: First transistor group

[0198] 22: Second transistor group

[0199] 100: Data latch circuit

Claims

1. A data latch circuit, comprising: A first transistor of a first conductivity type and a second transistor of the first conductivity type; The third transistor of the second conductivity type and the fourth transistor of the second conductivity type; A first gate layer connected to the gate of the third transistor; A second gate layer connected to the gate of the fourth transistor; The first wiring layer is connected to the drain of the third transistor and the drain of the fourth transistor, and transmits data; The first diffusion region and the second diffusion region are separated from each other along a first direction on the semiconductor substrate; A third gate layer connected to the gate of the first transistor; as well as A fourth gate layer connected to the gate of the second transistor, wherein The third and fourth transistors are controlled to perform a first control action to store the data in the data latch circuit, and a second control action to read the stored data. The gate of the first transistor is connected to the drain of the second transistor. The gate of the second transistor is connected to the drain of the first transistor. The source of the first transistor and the source of the second transistor are connected to a predetermined first reference voltage node. The source of the third transistor is connected to the drain of the first transistor and the gate of the second transistor. The source of the fourth transistor is connected to the drain of the second transistor and the gate of the first transistor. By turning the third transistor or the fourth transistor on and off through the first gate layer and the second gate layer, the data is stored on the first wiring layer in the data latch circuit, or the stored data is read onto the first wiring layer. During the period of data storage, the voltage levels of the first gate layer and the second gate layer are reduced to any percentage of the highest voltage level in the first gate layer and the second gate layer during data storage, within the range of 5% to 30%. The source and drain of each of the first and second transistors are located on the first diffusion region. The source and drain of each of the third and fourth transistors are located on the second diffusion region. The first gate layer and the second gate layer extend in a second direction intersecting the first direction to overlap with the second diffusion region in the stacking direction. The first wiring layer extends in the first direction to overlap with the first diffusion region and the second diffusion region in the stacking direction. The third gate layer and the fourth gate layer extend in the second direction to overlap with the first diffusion region in the stacking direction, and are separated from each other in the first direction.

2. A data latch circuit, comprising: A first transistor of a first conductivity type and a second transistor of the first conductivity type; The third transistor and the fourth transistor of the first conductivity type are controlled to perform a first control action to store data in the data latch circuit, and to perform a second control action to read the stored data. A fifth transistor of the second conductivity type and a sixth transistor of the second conductivity type, wherein the fifth transistor and the sixth transistor are controlled to initialize data stored in the data latch circuit; a first gate layer connected to the gate of the third transistor; A second gate layer connected to the gate of the fourth transistor; The first wiring layer is connected to the source of the third transistor and the source of the fourth transistor, and transmits the data; The first diffusion region and the second diffusion region are separated from each other on the semiconductor substrate along a second direction that intersects the first direction; as well as A third diffusion region is separated from the first diffusion region and the second diffusion region in the first direction, wherein, The gate of the first transistor is connected to the drain of the second transistor and the drain of the fourth transistor. The gate of the second transistor is connected to the drain of the first transistor and the drain of the third transistor. The source of the first transistor and the source of the second transistor are connected to a predetermined first reference voltage node. The source of the fifth transistor and the source of the sixth transistor are connected to a specified second reference voltage node. The drain of the fifth transistor is connected to the drain of the first transistor. The drain of the sixth transistor is connected to the drain of the second transistor. A common control signal is input to the gate of the fifth transistor and the gate of the sixth transistor. The source and drain of each of the first to fourth transistors are located on the third diffusion region. The source and drain of the fifth transistor are located on the first diffusion region. The source and drain of the sixth transistor are located on the second diffusion region. The first gate layer and the second gate layer extend in the second direction to overlap with the third diffusion region in the stacking direction, and are separated from each other in the first direction. The first wiring layer extends in the first direction to overlap with the third diffusion region in the stacking direction and is located between the first diffusion region and the second diffusion region.

3. The data latch circuit according to claim 2, wherein, During the period when the data is held in the data latch circuit, a voltage of any percentage within the range of 5% to 30% of the power supply voltage level is applied to the gates of the fifth and sixth transistors.

4. A semiconductor memory device, comprising: Storage cell array; as well as The data latch circuit according to any one of claims 1 to 3.

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