Test system and test circuit thereof

Abstract

A test system and a test circuit thereof are disclosed. The test circuit includes a command decoder, a trigger signal generator, a delay control signal generator, a delay circuit, and a test data generator. The command decoder decodes a test command to generate an adjustment signal. The trigger signal generator generates a trigger signal according to a clock signal. The delay control signal generator generates a delay control signal according to the adjustment signal. The delay circuit generates a unit delay according to the delay control signal and delays the trigger signal based on the unit delay to generate a plurality of sampling clocks. The test data generator samples test data according to the sampling clocks to obtain a test output signal.

Description

Technical Field

[0001] This invention relates to a testing system and its testing circuit, and more particularly to a memory testing system and memory testing circuit. Background Technology

[0002] The mainstream input / output architecture for Dynamic Random Access Memory (DRAM) today is the Double Data Rate (DDR) architecture. Because the DDR architecture transmits data once on the rising edge and once on the falling edge of the bus clock, its data transfer frequency is twice the bus clock frequency. Taking the current fourth-generation Double Data Rate (DDR4) specification as an example, under normal use, its bus clock frequency can reach approximately 1.6 GHz, therefore, the data transfer frequency of DDR4 can reach up to 3.2 GHz.

[0003] However, in memory chip product testing applications, especially under wafer-level testing conditions, it is difficult to provide the frequencies required for normal use (e.g., 1.6GHz). High-speed wafer-level test chambers typically only provide a maximum test frequency of about 100MHz, far lower than the frequency required for DDR memory in normal use. Furthermore, due to the high cost of high-speed test chambers, significantly increasing the test frequency is virtually impossible under current conditions. Therefore, current wafer-level memory testing is limited by the test frequency of the test chamber, resulting in a clock frequency provided to the memory during testing that is far lower than the clock frequency required for normal use, significantly increasing test time and consequently raising the manufacturing cost of memory chips. Summary of the Invention

[0004] This invention provides a test circuit that can perform internal testing operations of a memory using a clock signal with a low frequency.

[0005] The test circuit of this invention includes a command decoding circuit, a trigger signal generator, a delay control signal generator, a delay circuit, and a test data generator. The command decoding circuit generates an adjustment signal based on a decoded test command. The trigger signal generator generates a trigger signal based on an input clock signal. The delay control signal generator is coupled to the command decoding circuit and generates a delay control signal based on the adjustment signal. The delay circuit is coupled to the delay control signal generator and the trigger signal generator to generate a unit delay based on the delay control signal, and delays the trigger signal based on the unit delay to generate multiple sampling clocks. The test data generator samples test data based on the multiple sampling clocks to obtain a test output signal.

[0006] The testing system of this invention includes a testing machine and a testing circuit. The testing machine is coupled to the testing circuit. The testing circuit includes a command decoding circuit, a trigger signal generator, a delay control signal generator, a delay circuit, and a test data generator. The command decoding circuit generates an adjustment signal based on a decoded test command. The trigger signal generator generates a trigger signal based on an input clock signal. The delay control signal generator is coupled to the command decoding circuit and generates a delay control signal based on the adjustment signal. The delay circuit is coupled to the delay control signal generator and the trigger signal generator to generate a unit delay based on the delay control signal, and delays the trigger signal based on the unit delay to generate multiple sampling clocks. The test data generator samples test data based on the multiple sampling clocks to obtain a test output signal. The testing machine provides test commands and an input clock signal to the testing circuit, receives the test output signal, and generates a test result based on the test output signal.

[0007] Based on the above, the test circuit and test system of the present invention can use a lower frequency external clock signal input to the test circuit to obtain a higher frequency test output signal to complete the internal testing of the memory. Without increasing the hardware cost of the test machine, the test circuit can output a higher frequency output signal than the external input clock signal, thus shortening the test time. Furthermore, the technical solution of the present invention, besides not increasing the hardware cost of the test machine, also does not require the use of a frequency multiplier coupled to the clock input terminal of the test circuit, such as a phase-locked loop (PLL), thus not increasing the cost or complexity of the test system. Attached Figure Description

[0008] Figure 1 A schematic diagram of a test circuit according to an embodiment of the present invention is shown.

[0009] Figure 2 A schematic diagram of a test circuit according to another embodiment of the present invention is shown.

[0010] Figure 3 A schematic diagram of a test circuit according to another embodiment of the present invention is shown.

[0011] Figures 4A to 4D Illustration of the present invention Figure 3 A schematic diagram illustrating the implementation of the delay line in this embodiment.

[0012] Figure 5 A schematic diagram illustrating an embodiment of the present invention is shown.

[0013] Figure 6 Illustration of the present invention Figure 5 Waveforms of the input clock signal and the test output signal in an embodiment of the test system.

[0014] Figure 7 A waveform diagram illustrating the test action of the latency adjustment mode of the test system of the present invention is shown.

[0015] Figure 8 A waveform diagram illustrating the test action of the unit delay calibration mode of the test system of the present invention is shown.

[0016] [Symbol Explanation]

[0017] 100, 200, 300, 510: Test circuit; 110, 210, 310, 511: Command decoder; 120, 220, 320, 512: Trigger signal generator; 130, 230, 330, 513: Delay control signal generator; 140, 240, 340, 514: Delay circuit; 150, 250, 350, 515: Test data generator; 341: Delay line.

[0018] 342: Selection Circuit

[0019] 500: Test System

[0020] 516: Output driver

[0021] 517: Test Receiver

[0022] 520: Testing Machine

[0023] BUF1~BUFn: Buffers

[0024] C: Capacitor

[0025] CLK: Clock signal

[0026] CMD: Test command

[0027] d1~d9: Test data signals

[0028] D1~Dn: Delay unit

[0029] Dctrl: Delay control signal

[0030] DOUT: Test output signal

[0031] EN: Enable signal

[0032] INV1~INVn: Inverters

[0033] LT_T: Latency

[0034] LTctrl: Latency control signal

[0035] PB: Preamplifier signal section

[0036] PD1~PDn: Test data

[0037] R: Resistance

[0038] RCN: Resistor-Capacitor Network

[0039] S0, S1~S8: Sampling points

[0040] SCK1~SCKn: Sampling clock

[0041] SDA: Serial Data

[0042] SEL: Test Selection Signal

[0043] T1, T2, T3, T4, T1', T2', T3', T4': Test actions

[0044] TCODE: Adjust signal

[0045] TG: Trigger signal

[0046] VCD1~VCDn: Voltage-controlled delay circuit Detailed Implementation

[0047] Please refer to Figure 1 , Figure 1 This is a schematic diagram of a test circuit according to an embodiment of the present invention. The test circuit 100 includes a command decoder 110, a trigger signal generator 120, a delay control signal generator 130, a delay circuit 140, and a test data generator 150. The delay control signal generator 130 is coupled to the command decoder 110 and the delay circuit 140, and the delay circuit 140 is also coupled to the trigger signal generator 120 and the test data generator 150.

[0048] Command decoder 110 receives and decodes test commands (CMD) provided by an external source, such as a test machine. Trigger signal generator 120 receives a clock signal (CLK) provided by an external source, such as a test machine. The clock signal (CLK) can be a periodic clock signal. Trigger signal generator 120 generates a trigger signal (TG) based on the clock signal (CLK). Trigger signal generator 120 can generate the trigger signal (TG) based on the transition edges of the clock signal (CLK), where the transition edges can be rising edges and / or falling edges. Test data generator 150 outputs a test output signal (DOUT).

[0049] Command decoder 110 decodes the test command CMD and generates an adjustment signal TCODE. Command decoder 110 provides the adjustment signal TCODE to delay control signal generator 130. Delay control signal generator 130 generates a delay control signal Dctrl based on the adjustment signal TCODE. Delay circuit 140 sets a unit delay based on the delay control signal Dctrl and, based on the set unit delay, delays trigger signal TG one to multiple times to sequentially generate multiple sampling clocks SCK1 to SCKn. It is worth noting that since the trigger signal TG is generated based on the waveform of clock signal CLK, and delay circuit 140 delays the trigger signal TG multiple times based on the unit delay to generate sampling clocks SCK1 to SCKn; that is, each cycle of clock signal CLK will generate sampling clocks SCK1 to SCKn. This means that the frequency of sampling clocks SCK1 to SCKn will be higher than the frequency of clock signal CLK, and the frequency of sampling clocks SCK1 to SCKn can be determined by the unit delay time.

[0050] The test data generator 150 samples multiple test data points PD1 to PDn according to the sampling clocks SCK1 to SCKn to generate a test output signal DOUT. The test data PD1 to PDn can be pre-written into a temporary register in the test circuit 100. Figure 1 The test data generator 150 can be a preset test data (not shown) or test data generated by the integrated circuit according to the test action (e.g., memory read data). The test data generator 150 can be a parallel to serial converter to convert the test data PD1 to PDn into serial data according to the sampling clock SCK1 to SCKn, and thereby generate the test output signal DOUT.

[0051] The test circuit 100 of this embodiment can be embedded in the memory chip under test. According to the above embodiment, the test circuit 100 of this embodiment can output a test output signal DOUT based on the input test command CMD and clock signal CLK to complete the internal testing of the memory. Furthermore, the test circuit 100 is characterized in that the frequency of the test output signal DOUT is higher than the frequency of the clock signal CLK.

[0052] Please refer to Figure 2 , Figure 2This is a schematic diagram of a test circuit according to another embodiment of the present invention. The test circuit 200 includes a command decoder 210, a trigger signal generator 220, a delay control signal generator 230, a delay circuit 240, and a test data generator 250. The delay control signal generator 230 is coupled to the command decoder 210 and the delay circuit 240, and the delay circuit 240 is also coupled to the trigger signal generator 220 and the test data generator 250. The command decoder 210 is used to receive the test command CMD, the trigger signal generator 220 is used to receive the clock signal CLK, and the test data generator 250 is used to generate the output test signal DOUT.

[0053] Test circuit 200 and Figure 1 The difference in the test circuit of this embodiment is that the delay circuit 240 includes a plurality of voltage-controlled delay units VCD1 to VCDn connected in series. For example... Figure 2 As shown, the input of voltage-controlled delay unit VCD1 is coupled to trigger signal generator 220, and the output of voltage-controlled delay unit VCD1 is connected in series with voltage-controlled delay units VCD2 to VCDn. Voltage-controlled delay units VCD1 to VCDn are collectively coupled to delay control signal generator 230, and the outputs of voltage-controlled delay units VCD1 to VCDn are respectively coupled to test data generator 250.

[0054] The delay control signal generator 230 generates a delay control signal Dctrl based on the adjustment signal TCODE generated by decoding the test command CMD from the command decoder 210. The delay control signal Dctrl may have a voltage value. Each of the voltage-controlled delay units VCD1 to VCDn can generate a unit delay based on the voltage value of the delay control signal Dctrl, and sequentially delay the trigger signal TG to generate multiple sampling clocks SCK1 to SCKn. In this embodiment, the duration of the unit delay can be determined by the voltage value of the delay control signal Dctrl. The duration of the unit delay can be positively or negatively correlated with the voltage value of the delay control signal Dctrl, without any fixed limitation.

[0055] Please refer to Figure 3 , Figure 3This is a schematic diagram of a test circuit according to another embodiment of the present invention. The test circuit 300 includes a command decoder 310, a trigger signal generator 320, a delay control signal generator 330, a delay circuit 340, and a test data generator 350. The delay control signal generator 330 is coupled to the command decoder 310 and the delay circuit 340, and the delay circuit 340 is also coupled to the trigger signal generator 320 and the test data generator 350. The command decoder 310 receives the test command CMD, the trigger signal generator 320 receives the clock signal CLK, and the test data generator 350 generates the output test signal DOUT.

[0056] Test circuit 300 and Figure 1 The difference in the test circuit of this embodiment is that the delay circuit 340 includes a delay line 341 and a selection circuit 342, wherein the delay line 341 may include a plurality of delay units D1 to Dn connected in series in sequence. Figure 3 As shown, the input of delay unit D1 is coupled to trigger signal generator 320, and the output of delay unit D1 is sequentially connected in series with delay units D2 to Dn. The outputs of delay units D1 to Dn are respectively coupled to selection circuit 342. Selection circuit 342 is coupled to delay control signal generator 330 and test data generator 350, and selectively provides multiple output signals from the outputs of delay units D1 to Dn to test data generator 350.

[0057] Each of the delay units D1 to Dn generates a unit analytical delay and sequentially delays the trigger signal TG before outputting it to the selection circuit 342. The delay control signal generator 330 generates a delay control signal Dctrl based on the adjustment signal TCODE. The selection circuit 342 then selects a portion of the output from the delay units D1 to Dn based on the delay control signal Dctrl to generate multiple sampling clocks SCK1 to SCKn, where two sampling clocks with close phase have a unit delay. For example, if the set unit delay length is three times the unit analytical delay length, the delay control signal generator 330 provides the delay control signal Dctrl to the selection circuit 342. The selection circuit 342 selects the delay signals generated by delay units D3, D6, D9… and provides them to the test data generator 350 to generate multiple sampling clocks SCK1 to SCKn.

[0058] Please refer to Figures 4A-4D , Figures 4A-4D Example Figure 3 Multiple implementations of the delay line 341 in the embodiment. In Figure 4A In the middle, delay line 341 includes multiple buffers BUF1 to BUFn connected in series in sequence. Additionally, in... Figure 4BIn the delay line 341, multiple resistor-capacitor networks are also included. Each resistor-capacitor network can be coupled to the input or output of a corresponding buffer BUF1 to BUFn, and is used to increase the length of the unit resolution delay mentioned above. Figure 4B In the example of the resistor-capacitor network RCN, the resistor-capacitor network RCN is coupled to the output terminal of the buffer BUF1. One end of the resistor R is coupled to the output terminal of the buffer BUF1, and the other end of the resistor R is coupled to one end of the capacitor C. The other end of the capacitor C can be coupled to the reference ground terminal.

[0059] exist Figure 4C In the middle, delay line 341 includes multiple inverters INV1 to INVn connected in series. And... Figure 4D In this circuit, delay line 341 also includes multiple resistor-capacitor networks. These networks can be coupled to the input or output of each of the inverters INV1 to INVn, and are used to increase the length of the unit resolution delay mentioned above.

[0060] Please refer to Figure 5 This is a schematic diagram of a test system according to an embodiment of the present invention. The test system 500 includes a test circuit 510 and a test machine 520. The test machine 520 is connected to the test circuit 510 to perform tests. The test machine 520 provides test commands CMD and clock signals CLK to the test circuit 510, and receives test output signals DOUT from the test circuit 510. In this embodiment, the test machine 520 may also provide a test selection signal SEL to the test circuit 510, enabling the test circuit 510 to perform tests.

[0061] Among them, such as Figure 5 As shown, the test circuit 510 includes a command decoder 511, a trigger signal generator 512, a delay control signal generator 513, a delay circuit 514, a test data generator 515, an output driver 516, and a test receiver 517. The command decoder 511 is coupled to the trigger signal generator 512, the delay control signal generator 513, and the test receiver 517. The trigger signal generator 512 is also coupled to the delay circuit 514 and the output driver 516. The delay control signal generator 513 is also coupled to the delay circuit 514. The delay circuit 514 is also coupled to the test data generator 515. The test data generator 515 is also coupled to the output driver 516. The command decoder 511 is coupled to the test unit 520 to receive the test command CMD. The trigger signal generator 512 is coupled to the test unit 520 to receive the clock signal CLK. The test receiver 517 is coupled to the test unit 520 to receive the test selection signal SEL. The output driver 516 is coupled to the tester 520 and is used to output the test output signal DOUT to complete the test.

[0062] The test circuit 510 in this embodiment, and Figure 1 The difference in the test circuit is that the command decoder 511 can decode the test command CMD to provide a latency control signal LTctrl to the trigger signal generator 512. The trigger signal generator 512 can also set a latency based on the latency control signal LTctrl. The trigger signal generator 512 can adjust the timing of generating the trigger signal TG according to the latency.

[0063] Furthermore, in this embodiment, the test circuit 510 includes a test data generator 515 that samples test data PD1 to PDn according to multiple sampling clocks SCK1 to SCKn to generate serial data SDA and provide it to the output driver 516. The output driver 516 also receives a trigger signal TG generated by the trigger signal generator 512. The output driver 516 generates a test output signal DOUT based on the trigger signal TG and the serial data SDA. The test output signal DOUT may include a preamble signal portion and a test data signal portion. The preamble signal portion may be generated by the output driver 516 according to the trigger signal TG, while the test data signal portion may be generated by the output driver 516 according to the serial data SDA.

[0064] In this embodiment, the test circuit 510 also receives the test selection signal SEL from the test machine 520 via the test receiver 517. When the integrated circuit corresponding to the test circuit 510 is a device under test (DUT), the test circuit 510 can generate an enable signal EN based on the selection signal SEL and provide the enable signal EN to the command decoder 511, so that the command decoder 511 can execute the decoding action of the test command CMD and then execute the subsequent test actions.

[0065] Please refer to the following: Figure 5 and Figure 6 , Figure 6 Example as Figure 5 In an embodiment of the test system, waveforms of the input clock signal and the test output signal are shown. Among them, in... Figure 6 In the test output signal DOUT, there is a preamplifier signal portion PB and the test data signal portion, for example... Figure 6 The test data signals d1 to d9... are shown. The preamplifier signal PB is generated based on the trigger signal TG provided by the trigger signal generator 512, and therefore has a latency time LT_T relative to the rising edge trigger time of the clock signal CLK. In this embodiment, one cycle of the clock signal CLK can correspond to eight test data signals (e.g., test data signals d1 to d8).

[0066] It is worth mentioning that the trigger signal generator 512 can periodically generate the trigger signal TG based on multiple rising edges of the clock signal CLK.

[0067] Please refer to the following as well. Figure 5 as well as Figure 7 , Figure 7 This is a waveform diagram showing the test action of the latency adjustment mode of the test system according to an embodiment of the present invention. The test system of this embodiment can set the latency based on the results of multiple tests. Figure 7 In the test system 500, the command decoder 511 can execute test actions T1 to T4 respectively by generating different latency control signals LTctrl. The latency times of test actions T1 to T4 can be different first to fourth latency times. Corresponding to different latency times, the output driver 516 can generate test output signals DOUT with different pre-signal occurrence times for test actions T1 to T4. In this embodiment, the pre-signal portion of the test output signal DOUT can be logic 0. The test machine 520 can sample the test output signal DOUT according to the set sampling point S0. Therefore, in the latency adjustment mode, the test machine 520 can compare the above sampling result with logic 0 to determine whether the occurrence time of the pre-signal portion of the test output signal DOUT is correct.

[0068] exist Figure 7 In test actions T1 and T4, the test machine 520 can determine that the occurrence time of the pre-signal of the test output signal DOUT is incorrect, while in test actions T2 and T3, the test machine 520 can determine that the occurrence time of the pre-signal of the test output signal DOUT is correct. Based on this, the test machine 520 can further average the second latency time and the third unit latency time corresponding to test actions T2 and T3 to generate the set latency time.

[0069] Please refer to the following as well. Figure 5 as well as Figure 8 , Figure 8 This is a waveform diagram of the test action in the unit delay calibration mode of the test system according to an embodiment of the present invention. The test system of this embodiment can set the unit delay based on the results of multiple tests. Figure 8In the test system 500, the delay control signal generator 513 can execute test actions T1' to T4' respectively by generating different delay control signals Dctrl. The unit delay of test actions T1' to T4' can be different first to fourth unit delays. Corresponding to different unit delays, the output driver 516 can generate test output signals DOUT with different phases in test actions T1' to T4'. The test machine 520 can sample the test output signal DOUT according to the set sampling points S1 to S8. In the unit delay calibration mode, the test output signal DOUT is generated based on pre-set test data PD1 to PDn. Therefore, the test machine 520 can compare the above sampling results with the test data PD1 to PDn to determine whether the test output signal DOUT is correct.

[0070] exist Figure 8 In test actions T1' and T4', the test machine 520 can determine that the test output signal DOUT is incorrect, while in test actions T2' and T3', the test machine 520 can determine that the test output signal DOUT is correct. Based on this, the test machine 520 can further average the second unit delay and the third unit delay corresponding to test actions T2' and T3' to generate a set unit delay.

[0071] In this embodiment of the invention, after the latency and unit delay are set, the test data generator 510 can be modified to receive data from inside the integrated circuit, such as read data from the memory. The test machine 520 can then sample the test output signal DOUT according to the set sampling points to obtain the output data of the read data from the memory, thereby completing the test inside the memory.

[0072] In summary, the test system and its test circuit disclosed in this invention can generate a relatively high-frequency sampling signal based on the clock signal input to the test circuit, and generate an output test signal through the sampling signal to complete the internal testing operations of the memory, thereby shortening the test time. In this way, without the need for a phase-locked loop (PLL), the test system and its test circuit disclosed in this invention can perform relatively high-frequency test operations, effectively improving the test speed and reducing test costs without using a high-order test machine.

Claims

1. A test circuit receiving a test command and an input clock signal to generate a test output signal, comprising: a command decoder generating an adjustment signal according to decoding the test command; a trigger signal generator generating a trigger signal according to the clock signal; a delay control signal generator coupled to the command decoder, generating a delay control signal according to the adjustment signal; a delay circuit coupled to the delay control signal generator and the trigger signal generator, generating unit delays according to the delay control signal, delaying the trigger signal based on the unit delays to generate a plurality of sampling clocks for each cycle of the clock signal; and a test data generator sampling a plurality of test data according to the sampling clocks to convert into serial data.

2. The test circuit of claim 1, wherein the delay circuit comprises a plurality of voltage controlled delay elements, the voltage controlled delay elements being sequentially connected in series, wherein each of the voltage controlled delay elements provides the unit delays according to the delay control signal, the voltage controlled delay elements sequentially delaying the trigger signal to generate the sampling clocks, respectively.

3. The test circuit of claim 1, wherein the delay circuit comprises: a plurality of delay elements, wherein the delay elements are sequentially connected in series; and a selection circuit, wherein the delay elements sequentially delay the trigger signal to generate a plurality of delay signals, the selection circuit selects part of the delay signals according to the delay control signal to generate the sampling clocks.

4. The test circuit of claim 3, wherein each of the delay elements is a buffer.

5. The test circuit of claim 4, wherein each of the buffers is further coupled to a resistor-capacitor network, the resistor-capacitor network being coupled to an input or an output of the buffer.

6. The test circuit of claim 3, wherein each of the delay elements is an inverter.

7. The test circuit of claim 6, wherein each of the inverters is further coupled to a resistor-capacitor network, the resistor-capacitor network being coupled to an input or an output of the inverter.

8. The test circuit of claim 1, wherein the command decoder is further coupled to the trigger signal generator, the command decoder generates a latency control signal according to the test command, the trigger signal generator delays a starting point of the trigger signal by a latency according to the latency control signal.

9. The test circuit of claim 8, further comprising: an output driver coupled to the test data generator, outputting the test output signal according to the serial data.

10. The test circuit of claim 9, wherein the output driver is further coupled to the trigger signal generator, outputting the test output signal according to the trigger signal and the serial data.

11. The test circuit of claim 1, wherein the test data generator further generates the test output signal according to the serial data.

12. A test system, comprising: a tester; and the test circuit of claim 1, the tester being coupled to the test circuit, wherein the tester is configured to: provide the test command and the input clock signal to the test circuit, and receive the test output signal, and generate a test result according to the test output signal. ​ ​ ​ 13. The test system of claim 12, wherein the tester adjusts the unit delay via the test command and generates a set unit delay based on the corresponding test result.

14. The test system of claim 13, wherein the tester generates a first unit delay via a first test command, generates a second unit delay via a second test command, and calculates an average of the first unit delay and the second unit delay to generate the set unit delay when the first test result and the second test result corresponding to the first test command and the second test command are both passed, wherein the first unit delay is different from the second unit delay.

15. The test system of claim 12, wherein the command decoder is further coupled to the trigger signal generator, the command decoder generates a latency control signal based on the test command, and the trigger signal generator delays a starting point of the trigger signal by a latency based on the latency control signal.

16. The test system of claim 15, wherein the tester adjusts the latency via the test command and generates a set latency based on the corresponding test result.

17. The test system of claim 16, wherein the tester generates a first latency via a first test command, generates a second latency via a second test command, and calculates an average of the first latency and the second latency to generate the set latency when the first test result and the second test result corresponding to the first test command and the second test command are both passed, wherein the first latency is different from the second latency.

18. The test system of claim 12, wherein the test circuit further comprises a test accepter coupled to the command decoder, the test accepter is configured to receive a test selection signal provided by the tester and to enable the command decoder based on the test selection signal.

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