Analog-to-digital conversion circuit and method with accelerated comparison mechanism

Abstract

The present application relates to an analog-to-digital conversion circuit and method with an accelerated comparison mechanism. An analog-to-digital conversion circuit with an accelerated comparison mechanism. A positive and a negative capacitor array receive a positive and a negative input voltage and output a positive and a negative output voltage. A first comparator compares the positive and the negative output voltage to generate a first comparison result. A second comparator compares the positive and the negative output voltage with a reference voltage to generate a second comparison result. A control circuit switches a capacitor enable combination of the positive and the negative capacitor array according to the first comparison result in each switching phase and outputs a digital code as a digital output signal when the positive and the negative output voltage are equal. The control circuit operates in an accelerated switching mode when a difference between the positive and the negative output voltage is outside a preset range related to the reference voltage and operates in a normal switching mode when the difference is within the preset range according to the second comparison result.

Description

Technical Field

[0001] This invention relates to analog-to-digital conversion technology, and more particularly to an analog-to-digital conversion circuit and method with an accelerated comparison mechanism. Background Technology

[0002] Analog-to-digital converters (ADCs) convert continuous analog signals or physical quantities (usually voltage) into digital signals. ADCs can be implemented using various architectures. One common approach is the traditional digital slope ADC, which tracks the input signal linearly by gradually switching capacitors in a capacitor array after sampling it. This architecture results in a slower operating speed and a longer overall processing time. Summary of the Invention

[0003] In view of the problems of the prior art, one object of the present invention is to provide an analog-to-digital conversion circuit and method with an accelerated comparison mechanism to improve the prior art.

[0004] This invention includes an analog-to-digital conversion (ADC) circuit with an accelerated comparison mechanism, comprising: a positive-terminal capacitor array, a negative-terminal capacitor array, a first comparator, a second comparator, and a control circuit. The positive-terminal capacitor array is configured to receive a positive input voltage and output a positive output voltage. The negative-terminal capacitor array is configured to receive a negative input voltage and output a negative output voltage. The first comparator is configured to compare the positive and negative output voltages to generate a first comparison result. The second comparator is configured to compare the positive and negative output voltages according to a reference voltage to generate a second comparison result. The control circuit is configured to receive the first and second comparison results. During various switching stages, the control circuit switches the capacitor enable combinations of the positive and negative capacitor arrays using a set of digital codes based on the first comparison result, and outputs the corresponding set of digital codes as a digital output signal when the positive and negative output voltages are equal. According to the second comparison result, the control circuit operates in accelerated switching mode when the difference between the positive terminal output voltage and the negative terminal output voltage is outside a preset range related to the reference voltage, so that the positive terminal capacitor array and the negative terminal capacitor array switch at a first capacitor switching speed, and operates in normal switching mode when the difference is within a preset range, so that the positive terminal capacitor array and the negative terminal capacitor array switch at a second capacitor switching speed, wherein the first capacitor switching speed is greater than the second capacitor switching speed.

[0005] The present invention also includes an analog-to-digital conversion method with an accelerated comparison mechanism, comprising: causing a positive terminal capacitor array to receive a positive terminal input voltage and output a positive terminal output voltage; causing a negative terminal capacitor array to receive a negative terminal input voltage and output a negative terminal output voltage; causing a first comparator to compare the positive terminal output voltage and the negative terminal output voltage to generate a first comparison result; causing a second comparator to compare the positive terminal output voltage and the negative terminal output voltage according to a reference voltage to generate a second comparison result; and causing a control circuit to receive the first comparison result, so as to switch the capacitor enable groups of the positive terminal capacitor array and the negative terminal capacitor array with a set of digital codes according to the first comparison result in each of the plurality of switching stages. The system combines the positive and negative output voltages and outputs the corresponding digital code as a digital output signal when the positive and negative output voltages are equal. It also receives a second comparison result and, based on this result, operates in accelerated switching mode when the difference between the positive and negative output voltages is outside a preset range related to the reference voltage, causing the positive and negative capacitor arrays to switch at a first capacitor switching speed. When the difference is within a preset range, it operates in normal switching mode, causing the positive and negative capacitor arrays to switch at a second capacitor switching speed, where the first capacitor switching speed is greater than the second capacitor switching speed.

[0006] The features, implementation, and effects of this application are described in detail below with reference to the accompanying drawings, using preferred embodiments. Attached Figure Description

[0007] [ Figure 1 [This diagram shows a block diagram of an analog-to-digital converter circuit with an accelerated comparison mechanism according to one embodiment of the present invention;]

[0008] [ Figure 2 This diagram shows a more detailed circuit diagram of the positive terminal capacitor array in one embodiment of the present invention.

[0009] [ Figure 3 This diagram shows a more detailed circuit diagram of the positive terminal capacitor array in another embodiment of the present invention.

[0010] [ Figure 4 [This illustrates an embodiment of the present invention where the positive terminal output voltage and the negative terminal output voltage vary with...] Figure 1 A schematic diagram showing how the operation of an analog-to-digital converter circuit changes; and

[0011] [ Figure 5 The diagram shows a flowchart of an analog-to-digital conversion method with an accelerated comparison mechanism according to an embodiment of the present invention. Detailed Implementation

[0012] One objective of this invention is to provide an analog-to-digital conversion circuit and method with an accelerated comparison mechanism, which switches the capacitor at different switching speeds based on the difference between the positive and negative output voltages, thereby accelerating the operation when the difference is large and maintaining accuracy when the difference is small.

[0013] Please refer to Figure 1 . Figure 1 The diagram illustrates a block diagram of an analog-to-digital converter circuit 100 with an accelerated comparison mechanism according to one embodiment of the present invention. The analog-to-digital converter circuit 100 includes: a positive terminal capacitor array 110, a negative terminal capacitor array 120, a first comparator 130, a second comparator 140, and a control circuit 150.

[0014] The positive terminal capacitor array 110 is configured to receive the positive terminal input voltage Vip and output the positive terminal output voltage Va. More specifically, in one embodiment, the positive terminal capacitor array 110 is connected to an analog signal source via a switch Sip to receive the positive terminal input voltage Vip, and after the switch Sip is disconnected from the analog signal source, it generates the positive terminal output voltage Va by switching the internal capacitor enable combination.

[0015] The negative-terminal capacitor array 120 is configured to receive the negative-terminal input voltage Vin and output the negative-terminal output voltage Vb. More specifically, in one embodiment, the negative-terminal capacitor array 120 is connected to an analog signal source via a switch Sin to receive the negative-terminal input voltage Vin, and after the switch Sin is disconnected from the analog signal source, the negative-terminal output voltage Vb is generated by switching the internal capacitor enable combination.

[0016] The first comparator 130 is configured to compare the positive terminal output voltage Va and the negative terminal output voltage Vb to produce a first comparison result CR1.

[0017] The second comparator 140 is configured to compare the positive terminal output voltage Va and the negative terminal output voltage Vb according to the reference voltage Vr to produce a second comparison result CR2.

[0018] The control circuit 150 is configured to receive the first comparison result CR1 and the second comparison result CR2, and accordingly control the positive terminal capacitor array 110 and the negative terminal capacitor array 120 to switch the capacitor enable combination.

[0019] In each of the multiple switching stages, the control circuit 150 uses a set of digital codes to DC switch the positive terminal capacitor array 110 and the negative terminal capacitor array 120 according to the first comparison result CR1 generated by the first comparator 130. When the positive terminal output voltage Va and the negative terminal output voltage Vb are equal, the control circuit 150 outputs the corresponding set of digital codes as the digital output signal DOUT.

[0020] More specifically, the capacitors in the positive capacitor array 110 and the negative capacitor array 120 are initially disabled. After receiving the positive input voltage Vip and the negative input voltage Vin, the control circuit 150 continuously adjusts the digital code DC according to the first comparison result CR1 to switch the capacitor enable combinations of the positive capacitor array 110 and the negative capacitor array 120. In one embodiment, the digital code DC switches the capacitors included in the positive capacitor array 110 and the negative capacitor array 120 in a thermometer-coded form at each switching stage.

[0021] When there exists a set of digital codes DC that makes the positive terminal output voltage Va and the negative terminal output voltage Vb equal, this set of digital codes DC is the analog-to-digital conversion result of the positive terminal input voltage Vip and the negative terminal input voltage Vin, and is output as a digital output signal DOUT.

[0022] The control circuit 150 determines whether the difference between the positive terminal output voltage Va and the negative terminal output voltage Vb is within a preset range related to the reference voltage Vr based on the second comparison result CR generated by the second comparator 140, and operates in either the accelerated switching mode or the normal switching mode accordingly.

[0023] In one embodiment, the second comparator 140 includes a positive-terminal comparator 160 and a negative-terminal comparator 170. The positive-terminal comparator 160 is configured to compare the positive-terminal output voltage Vip with a reference voltage Vr to generate a positive-terminal comparison result CP, which is included in the second comparison result CR2. The negative-terminal comparator 170 is configured to compare the negative-terminal input voltage Vin with the reference voltage Vr to generate a negative-terminal comparison result CN, which is included in the second comparison result CR2.

[0024] The control circuit 150 is configured to set a preset range between positive and negative values ​​of the reference voltage Vr, and determines whether the difference between the positive terminal output voltage Vip and the negative terminal output voltage Vin is within the preset range based on a second comparison result. More specifically, when the difference is expressed as Vi, the condition that the difference is within the preset range can be expressed as -Vr≤Vi≤Vr. The condition that the difference is outside the preset range can be expressed as Vi<-Vr or Vi>Vr. In a numerical example, the reference voltage Vr can be, for example, but not limited to, 100 millivolts (mV).

[0025] It should be noted that the structure of the second comparator 140 and the setting of the preset range described above are merely examples. In other embodiments, the second comparator 140 can achieve the purpose of comparing the difference between the positive terminal output voltage Vip and the negative terminal output voltage Vin through other structures and preset range settings.

[0026] When the difference between the positive terminal output voltage Va and the negative terminal output voltage Vb is outside a preset range, the control circuit 150 operates in accelerated switching mode, causing the positive terminal capacitor array 110 and the negative terminal capacitor array 120 to switch at a first capacitor switching speed. Conversely, when the difference is within a preset range, the control circuit 150 operates in normal switching mode, causing the positive terminal capacitor array 110 and the negative terminal capacitor array 120 to switch at a second capacitor switching speed. The first capacitor switching speed is greater than the second capacitor switching speed.

[0027] In one embodiment, when the difference is outside a preset range, the control circuit 150 determines that the difference between the positive terminal output voltage Va and the negative terminal output voltage Vb is large, and causes the positive terminal capacitor array 110 and the negative terminal capacitor array 120 to operate at a faster capacitor switching speed, thereby accelerating the comparison process. Conversely, when the difference is within the preset range, the control circuit 150 determines that the difference between the positive terminal output voltage Va and the negative terminal output voltage Vb is small and close, and causes the positive terminal capacitor array 110 and the negative terminal capacitor array 120 to operate at a slower capacitor switching speed, thereby improving the accuracy of the comparison.

[0028] Please refer to Figure 2 . Figure 2 A more detailed circuit diagram of the positive terminal capacitor array 110 is shown in one embodiment of the present invention. The following will be accompanied by... Figure 2 Taking the positive terminal capacitor array 110 as an example, the structure of the comparator capacitor array and the operation of the accelerated comparator mechanism will be explained. The negative terminal capacitor array 120 can have the same structure and operation as the positive terminal capacitor array 110, and will not be described in detail again.

[0029] The positive terminal capacitor array 110 includes multiple capacitors, a capacitor switching circuit 200, and multiple acceleration switching circuits 210.

[0030] In this embodiment, the positive terminal capacitor array 110 includes capacitors C0 to C5, C... 6A C 6B C 7A C 7B C 8A C 8B C 9A And C 9B These capacitors include multiple groups of corresponding capacitors, and in this embodiment, they include C. 6A And C 6B C 7A And C 7B C 8A And C 8B C 9A And C 9B Two capacitors for each of the four groups.

[0031] The capacitor switching circuit 200 is electrically coupled to the aforementioned capacitor and configured to enable the corresponding capacitor by DC switching according to the digital code.

[0032] Each of the accelerated switching circuits 210 is electrically coupled to a corresponding set of capacitors and configured to simultaneously enable the corresponding set of capacitors according to the accelerated switching signal SS. In one embodiment, the accelerated switching circuit 210 is a switching element disposed between the corresponding set of capacitors to form a path to connect the corresponding set of capacitors under the control of the accelerated switching signal SS.

[0033] therefore, Figure 1 When the control circuit 150 is operating in the accelerated switching mode, in each switching stage, the digital code DC is used to enable one of the target capacitors through the capacitor switching circuit 200, and the accelerated switching signal SS is used to enable the corresponding group of capacitors corresponding to the target capacitor through the accelerated switching circuit 210.

[0034] Figure 1 When the control circuit 150 is operating in normal switching mode, it enables the target capacitor in the capacitor only by using digital code DC through the capacitor switching circuit 200 in each switching stage.

[0035] Taking one application scenario as an example, when the positive terminal capacitor array 110 and the negative terminal capacitor array 120 receive the positive terminal input voltage Vip and the negative terminal input voltage Vin respectively, the capacitors in the positive terminal capacitor array 110 and the negative terminal capacitor array 120 are initially suppressed. Since the difference between the positive terminal output voltage Va and the negative terminal output voltage Vb is large, the control circuit 150 adjusts the digital code DC according to the first comparison result CR1, and also operates in the accelerated switching mode according to the second comparison result CR2, which shows that the difference bit is outside the preset range.

[0036] Therefore, under the control of the digital code DC encoded by the thermometer, the control circuit 150 can use capacitor C in the first switching phase. 9A The target capacitor is enabled by capacitor switching circuit 200, and then simultaneously enabled by acceleration switching signal SS through acceleration switching circuit 210, along with capacitor C. 9A The relevant capacitor C 9B Similarly, if the second comparison result CR2 continues to show a difference value outside the preset range, the control circuit 150 continues to operate in the accelerated switching mode, and in the second switching stage, the corresponding capacitor C is simultaneously enabled using the above mechanism. 8A And C 8B And in the third switching phase, the corresponding capacitor C is simultaneously enabled using the above mechanism. 7A And C 7B .

[0037] When the second comparison result CR2 shows a difference within a preset range, the control circuit 150 will operate in normal switching mode, enabling one capacitor sequentially via the capacitor switching circuit 200 in each subsequent switching stage (e.g., from capacitor C in each switching stage). 6A C 6B Switch to capacitor C0 in sequence.

[0038] Please refer to Figure 3 . Figure 3 A more detailed circuit diagram of the positive terminal capacitor array 110 is shown in another embodiment of the present invention. The following will be accompanied by... Figure 3 Taking the positive terminal capacitor array 110 as an example, the structure of the comparator capacitor array and the operation of the accelerated comparator mechanism will be explained. The negative terminal capacitor array 120 can have the same structure and operation as the positive terminal capacitor array 110, and will not be described in detail again.

[0039] The positive terminal capacitor array 110 includes multiple capacitors, a capacitor switching circuit 200, and multiple delay circuits 300.

[0040] In this embodiment, the positive terminal capacitor array 110 includes capacitors C0 to C5, C... 6A C 6B C 7A C 7B C 8A C 8B C 9A And C 9B .

[0041] The capacitor switching circuit 200 is electrically coupled to the aforementioned capacitor and configured to enable the corresponding capacitor by DC switching according to the digital code.

[0042] Each delay circuit 300 is electrically coupled between two adjacent capacitors and includes multiple delay units DL. Each delay unit DL is in... Figure 3 The image is illustrated as a buffer. In one embodiment, the capacitor switching circuit 200 can control the operation of the delay circuit 300 and switch capacitors via, for example, but not limited to, flip-flops, associated signals (not shown), and logic circuitry. Therefore, the delay units in the delay circuit 300 determine the switching time between two adjacent capacitors. Each delay circuit 300 is configured to bypass at least a portion of the delay unit DL according to the acceleration switching signal SS.

[0043] With capacitor C 9A And C 9B Taking the delay circuit 300 as an example, the delay circuit 300 includes multiple delay units DL to determine the capacitance C. 9A And C 9B The switching time between them, i.e., the capacitance C 9AAnd C 9B The interval between two consecutive switching phases.

[0044] therefore, Figure 1 When the control circuit 150 is operating in the accelerated switching mode, in each switching stage, the digital code DC is used to enable one of the target capacitors in the capacitor switching circuit 200, and the accelerated switching signal SS is used to bypass at least one delay unit DL of the delay circuit 300 between the target capacitor and the next capacitor.

[0045] Figure 1 When the control circuit 150 is operating in normal switching mode, it only enables the target capacitor in the capacitor through the capacitor switching circuit 200 with digital code DC during each switching stage. Therefore, the delay unit DL is not bypassed by the delay circuit 300.

[0046] Taking one application scenario as an example, when the positive terminal capacitor array 110 and the negative terminal capacitor array 120 receive the positive terminal input voltage Vip and the negative terminal input voltage Vin respectively, the capacitors in the positive terminal capacitor array 110 and the negative terminal capacitor array 120 are initially suppressed. Since the difference between the positive terminal output voltage Va and the negative terminal output voltage Vb is large, the control circuit 150 adjusts the digital code DC according to the first comparison result CR1, and also operates in the accelerated switching mode according to the second comparison result CR2, which shows that the difference bit is outside the preset range.

[0047] Therefore, under the control of the digital code DC encoded by the thermometer, the control circuit 150 can use capacitor C in the first switching phase. 9A The target capacitor is enabled by the capacitor switching circuit 200, and then the enable capacitor C is bypassed by the acceleration switching signal SS. 9A With the next capacitor C 9B The delay unit DL of the delay circuit 300. Similarly, if the second comparison result CR2 continues to show a difference value outside the preset range, the control circuit 150 continues to operate in the accelerated switching mode, bypassing the enable capacitor C in the second switching phase using the aforementioned mechanism. 9B With the next capacitor C 8A The delay unit DL of the delay circuit 300 is used, and the corresponding capacitor C is simultaneously enabled in the third switching phase using the above mechanism. 8A And C 8B .

[0048] When the second comparison result CR2 shows a difference within a preset range, the control circuit 150 will operate in normal switching mode, enabling one capacitor sequentially via the capacitor switching circuit 200 in each subsequent switching stage (e.g., from capacitor C in each switching stage). 7A C 7BThe delay unit DL of the related delay circuit 300 is switched sequentially to capacitor C0 and is no longer bypassed.

[0049] In one embodiment, paired with Figure 2 The described acceleration switching mechanism and its combination Figure 3 The described accelerated switching mechanism can be implemented selectively or simultaneously. When implemented simultaneously, the control circuit 150 can simultaneously enable multiple corresponding capacitors in each switching phase in the accelerated switching mode, and bypass at least a portion of the delay units in the delay circuit 300 between these corresponding capacitors and the next capacitor. For example, the control circuit 150 can enable a corresponding capacitor C in one switching phase. 9A And C 9B And bypass capacitor C 9B And C 9A The delay unit DL of the delay circuit 300 is used to accelerate the switching.

[0050] It should be noted that the number of capacitors included in the above-described set of corresponding capacitors is merely an example. In other embodiments, the number of capacitors included in a set of corresponding capacitors may be two or more values ​​to achieve faster switching, or different sets of corresponding capacitors may include different numbers of capacitors, and different preset ranges may be set for the second comparator to achieve different switching speeds. Furthermore, the number of delay units included in the delay circuit is also merely an example. In other embodiments, the number of delay units may be two or more arbitrary values.

[0051] Please refer to Figure 4 . Figure 4 In one embodiment of the present invention, the positive terminal output voltage Va and the negative terminal output voltage Vb vary with... Figure 1 A schematic diagram showing how the operation of the analog-to-digital converter circuit 100 varies. Figure 4 In the diagram, the positive terminal output voltage Va is drawn as a solid line segment, and the negative terminal output voltage Vb is drawn as a dashed bar line.

[0052] like Figure 4 As shown, before time interval T1, Figure 1 The positive terminal capacitor array 110 and the negative terminal capacitor array 120 receive the positive terminal input voltage Vip and the negative terminal input voltage Vin through switches Sip and Sin, so that the positive terminal output voltage Va and the negative terminal output voltage Vb are equal to the positive terminal input voltage Vip and the negative terminal input voltage Vin.

[0053] In time interval T1, Figure 1Switches Sip and Sin are disconnected, causing the positive capacitor array 110 and the negative capacitor array 120 to sample and generate positive output voltage Va and negative output voltage Vb. The control circuit 150 then switches based on the comparison result of the positive output voltage Va and the negative output voltage Vb. Figure 4 The positive value +Vr and the negative value -Vr of the reference voltage Vr are also shown.

[0054] During time interval T2, the difference between the positive terminal output voltage Va and the negative terminal output voltage Vb is outside a preset range. Therefore, the control circuit 150 will operate in accelerated switching mode to control the switching of the positive terminal capacitor array 110 and the negative terminal capacitor array 120, causing the positive terminal output voltage Va and the negative terminal output voltage Vb to decrease at a first slope. Figure 4 In the middle, the first slope is represented by line segment SL1.

[0055] During time interval T3, the difference between the positive terminal output voltage Va and the negative terminal output voltage Vb is within a preset range. The control circuit 150 will operate in normal switching mode, controlling the switching of the positive terminal capacitor array 110 and the negative terminal capacitor array 120, causing the positive terminal output voltage Va and the negative terminal output voltage Vb to decrease with a second slope, where the first slope is greater than the second slope. Figure 4 In the middle, the second slope is represented by the line segment SL2.

[0056] After time interval T3, the difference between the positive terminal output voltage Va and the negative terminal output voltage Vb will be equal, thus making... Figure 1 The control circuit 150 generates a digital output signal DOUT.

[0057] Therefore, the analog-to-digital conversion circuit of the present invention can switch at different capacitor switching speeds according to the difference between the positive terminal output voltage and the negative terminal output voltage, which can speed up the operation when the difference is large and maintain accuracy when the difference is small.

[0058] Please refer to Figure 5 . Figure 5 The diagram shows a flowchart of an analog-to-digital conversion method 500 with an accelerated comparison mechanism according to an embodiment of the present invention.

[0059] In addition to the aforementioned apparatus, the present invention also discloses an analog-to-digital conversion method 500 with an accelerated comparison mechanism, applicable to, for example, but not limited to, [various applications]. Figure 1 In the analog-to-digital conversion circuit 100. One of the analog-to-digital conversion methods 500 is implemented, for example... Figure 5 As shown, it includes the following steps:

[0060] In step S510, the positive terminal capacitor array 110 receives the positive terminal input voltage Vip and outputs the positive terminal output voltage Va.

[0061] In step S520, the negative terminal capacitor array 120 receives the negative terminal input voltage Vip and outputs the negative terminal output voltage Vb.

[0062] In step S530, the first comparator 130 compares the positive terminal output voltage Va and the negative terminal output voltage Vb to generate a first comparison result CR1.

[0063] In step S540, the second comparator 140 compares the positive terminal output voltage Va and the negative terminal output voltage Vb to generate a second comparison result CR2.

[0064] In step S550, the control circuit 150 receives the first comparison result CR1 to determine whether the positive terminal output voltage Va and the negative terminal output voltage Vb are equal based on the first comparison result CR1.

[0065] In step S560, when the positive terminal output voltage Va and the negative terminal output voltage Vb are not equal, the control circuit 150 switches the capacitor enable combination of the positive terminal capacitor array 110 and the negative terminal capacitor array 120 with a set of digital codes according to the first comparison result CR1 in each of the multiple switching stages.

[0066] In step S570, the control circuit 150 receives the second comparison result CR2 to determine whether the difference between the positive terminal output voltage Va and the negative terminal output voltage Vb is within a preset range based on the second comparison result CR2.

[0067] In step S580, when the difference between the positive terminal output voltage Va and the negative terminal output voltage Vb is outside a preset range, the control circuit 150 operates in an accelerated switching mode, causing the positive terminal capacitor array 110 and the negative terminal capacitor array 120 to switch at a first capacitor switching speed.

[0068] In step S585, the control circuit 150 operates in normal switching mode when the difference between the positive terminal output voltage Va and the negative terminal output voltage Vb is within a preset range, and the positive terminal capacitor array 110 and the negative terminal capacitor array 120 switch at a second capacitor switching speed, wherein the first capacitor switching speed is greater than the second capacitor switching speed.

[0069] After steps S580 and S585, the process returns to step S530 to continue the comparison. When it is determined in step S550 that the positive terminal output voltage Va and the negative terminal output voltage Vb are equal, the process proceeds to step S590, and the control circuit 150 outputs the corresponding set of digital codes DC as the digital output signal DOUT.

[0070] It should be noted that the above-described implementation is merely an example. In other embodiments, those skilled in the art can make modifications without departing from the spirit of the invention.

[0071] In summary, the analog-to-digital conversion circuit and method with an accelerated comparison mechanism in this invention switches at different capacitor switching speeds based on the difference between the positive and negative output voltages. This can accelerate the operation when the difference is large and maintain accuracy when the difference is small.

[0072] Although the embodiments of this application are described above, these embodiments are not intended to limit this application. Those skilled in the art can make changes to the technical features of this application based on the express or implied content of this application. All such changes may fall within the scope of patent protection sought by this application. In other words, the scope of patent protection of this application shall be determined by the scope of the patent application as defined in this specification.

[0073] [Symbol Explanation]

[0074] 100: Analog-to-digital converter circuit

[0075] 110: Positive terminal capacitor array

[0076] 120: Negative-end capacitor array

[0077] 130: First comparator

[0078] 140: Second comparator

[0079] 150: Control Circuit

[0080] 160: Positive end comparator

[0081] 170: Negative-end comparator

[0082] 200: Capacitor switching circuit

[0083] 210: Accelerated switching circuit

[0084] 300: Delay circuit

[0085] 500: Analog-to-digital conversion method

[0086] S510~S590: Steps

[0087] C0~C5, C 6A C 6B C 7A C 7B C 8A C 8B C 9A C 9B :capacitance

[0088] CN: Negative end comparison result

[0089] CP: Results of positive end comparison

[0090] CR1: First comparison result

[0091] CR2: Second comparison result

[0092] DL: Delay Unit

[0093] DC: Digital Code

[0094] DOUT: Digital output signal

[0095] Sin, Sip: Switches

[0096] SL1, SL2: line segments

[0097] SS: Accelerated switching signal

[0098] T1~T3: Time interval

[0099] Va: Positive terminal output voltage

[0100] Vb: Output voltage at the negative terminal

[0101] Vin: Negative input voltage

[0102] Vip: Positive input voltage

[0103] Vr: Reference voltage.

Claims

1. An analog-to-digital converter circuit with an accelerated comparison mechanism, comprising: A positive-terminal capacitor array configured to receive a positive-terminal input voltage and output a positive-terminal output voltage; A negative-terminal capacitor array configured to receive a negative-terminal input voltage and output a negative-terminal output voltage; A first comparator is configured to compare the positive terminal output voltage and the negative terminal output voltage to produce a first comparison result; A second comparator is configured to compare the positive terminal output voltage and the negative terminal output voltage according to a reference voltage to generate a second comparison result; as well as A control circuit configured to receive the first comparison result and the second comparison result; In each of the multiple switching stages, the control circuit switches a capacitor enable combination of the positive terminal capacitor array and the negative terminal capacitor array with a set of digital codes according to the first comparison result, and outputs the corresponding set of digital codes as a digital output signal when the positive terminal output voltage and the negative terminal output voltage are equal. According to the second comparison result, the control circuit operates in an accelerated switching mode when the difference between the positive terminal output voltage and the negative terminal output voltage is outside a preset range related to the reference voltage, causing the positive terminal capacitor array and the negative terminal capacitor array to switch at a first capacitor switching speed, and operates in a normal switching mode when the difference is within the preset range, causing the positive terminal capacitor array and the negative terminal capacitor array to switch at a second capacitor switching speed, wherein the first capacitor switching speed is greater than the second capacitor switching speed.

2. The analog-to-digital converter circuit of claim 1, wherein the second comparator comprises: A positive terminal comparator is configured to compare the positive terminal output voltage with the reference voltage to produce the second comparison result, which includes a positive terminal comparison result. as well as A negative-terminal comparator is configured to compare the negative-terminal output voltage with the reference voltage to produce the second comparison result, which includes a negative-terminal comparison result. The control circuit is configured to set a range between a positive value and a negative value of the reference voltage as the preset range, and to determine whether the difference between the positive terminal output voltage and the negative terminal output voltage is within the preset range based on the second comparison result.

3. The analog-to-digital conversion circuit according to claim 2, wherein the reference voltage is 100 millivolts.

4. The analog-to-digital converter circuit according to claim 1, wherein each of the positive terminal capacitor arrays and the negative terminal capacitor array comprises: Multiple capacitors; A capacitor switching circuit is electrically coupled to the plurality of capacitors and configured to switch the corresponding plurality of capacitors according to the set of digital codes. as well as Multiple acceleration switching circuits, each electrically coupled to a corresponding set of capacitors among the multiple capacitors, are configured to simultaneously enable the corresponding set of capacitors according to an acceleration switching signal. When the control circuit operates in the accelerated switching mode, in each of the plurality of switching stages, it enables one of the target capacitors among the plurality of capacitors through the capacitor switching circuit with the set of digital codes, and simultaneously enables the set of corresponding capacitors corresponding to the target capacitor through the plurality of accelerated switching circuits with the accelerated switching signal. When the control circuit operates in the normal switching mode, in each of the plurality of switching stages, it enables the target capacitor among the plurality of capacitors only by means of the set of digital codes through the capacitor switching circuit.

5. The analog-to-digital converter circuit according to claim 1, wherein each of the positive terminal capacitor arrays and the negative terminal capacitor array comprises: Multiple capacitors; A capacitor switching circuit is electrically coupled to the plurality of capacitors and configured to switch the corresponding plurality of capacitors according to the set of digital codes. as well as Multiple delay circuits, each electrically coupled between two adjacent capacitors, each including multiple delay units to determine a switching time between the two adjacent capacitors, and each configured to bypass at least a portion of the multiple delay units according to an acceleration switching signal. When the control circuit operates in the accelerated switching mode, in each of the plurality of switching stages, it enables one of the target capacitors among the plurality of capacitors through the capacitor switching circuit with the set of digital codes, and bypasses the plurality of delay units of one of the plurality of delay circuits between the target capacitor and the next capacitor with the accelerated switching signal. When the control circuit operates in the normal switching mode, in each of the plurality of switching stages, it enables only one of the target capacitors among the plurality of capacitors through the capacitor switching circuit using the set of digital codes.

6. An analog-to-digital conversion method with an accelerated comparison mechanism, comprising: A positive-terminal capacitor array receives a positive-terminal input voltage and outputs a positive-terminal output voltage. A negative-terminal capacitor array receives a negative-terminal input voltage and outputs a negative-terminal output voltage. A first comparator compares the positive terminal output voltage and the negative terminal output voltage to produce a first comparison result; A second comparator compares the positive terminal output voltage and the negative terminal output voltage against a reference voltage to generate a second comparison result. A control circuit receives the first comparison result and switches a capacitor enable combination of the positive terminal capacitor array and the negative terminal capacitor array with a set of digital codes according to the first comparison result in each of the plurality of switching stages, and outputs the corresponding set of digital codes as a digital output signal when the positive terminal output voltage and the negative terminal output voltage are equal. as well as The control circuit receives the second comparison result and, based on the second comparison result, operates in an accelerated switching mode when the difference between the positive terminal output voltage and the negative terminal output voltage is outside a preset range related to the reference voltage, causing the positive terminal capacitor array and the negative terminal capacitor array to switch at a first capacitor switching speed. When the difference is within the preset range, the circuit operates in a normal switching mode, causing the positive terminal capacitor array and the negative terminal capacitor array to switch at a second capacitor switching speed, wherein the first capacitor switching speed is greater than the second capacitor switching speed.

7. The analog-to-digital conversion method according to claim 6 further includes: The second comparator includes a positive terminal comparator that compares the positive terminal output voltage with a reference voltage to generate the second comparison result, which includes a positive terminal comparison result. The second comparator includes a negative-terminal comparator that compares the negative-terminal output voltage with the reference voltage to generate the second comparison result, which includes a negative-terminal comparison result; and The control circuit sets a range between a positive value and a negative value of the reference voltage as the preset range, and determines whether the difference between the positive terminal output voltage and the negative terminal output voltage is within the preset range based on the second comparison result.

8. The analog-to-digital conversion method according to claim 7, wherein the reference voltage is 100 millivolts.

9. The analog-to-digital conversion method according to claim 6, wherein each of the positive terminal capacitor arrays and the negative terminal capacitor arrays includes a plurality of capacitors, a capacitor switching circuit, and a plurality of accelerated switching circuits, the capacitor switching circuit being electrically coupled to the plurality of capacitors and configured to enable the corresponding plurality of capacitors according to the set of digital codes, each of the plurality of accelerated switching circuits being electrically coupled to a corresponding set of capacitors in the plurality of capacitors and configured to simultaneously enable the corresponding set of capacitors according to an accelerated switching signal, the analog-to-digital conversion method further includes: When the control circuit is operating in the accelerated switching mode, in each of the plurality of switching stages, one of the target capacitors among the plurality of capacitors is enabled by the set of digital codes through the capacitor switching circuit, and the set of corresponding capacitors corresponding to the target capacitor is simultaneously enabled by the accelerated switching signal through the plurality of accelerated switching circuits. as well as When the control circuit is operating in the normal switching mode, in each of the plurality of switching stages, the target capacitor among the plurality of capacitors is enabled only by the set of digital codes through the capacitor switching circuit.

10. The analog-to-digital conversion method of claim 6, wherein each of the positive-terminal capacitor arrays and the negative-terminal capacitor arrays includes a plurality of capacitors, a capacitor switching circuit, and a plurality of delay circuits, the capacitor switching circuit being electrically coupled to the plurality of capacitors and configured to switch to enable the corresponding plurality of capacitors according to the set of digital codes, each of the plurality of delay circuits being electrically coupled between two adjacent plurality of capacitors, each including a plurality of delay units to determine a switching time between two adjacent plurality of capacitors, and each configured to bypass at least a portion of the plurality of delay units according to an accelerated switching signal, the analog-to-digital conversion method further comprising: When the control circuit is operating in the accelerated switching mode, in each of the plurality of switching stages, it enables one of the target capacitors in the plurality of capacitors through the capacitor switching circuit with the set of digital codes, and bypasses the plurality of delay units of one of the plurality of delay circuits between the target capacitor and the next capacitor with the accelerated switching signal. When the control circuit is operating in the normal switching mode, in each of the plurality of switching stages, it enables only one of the target capacitors among the plurality of capacitors by means of the set of digital codes through the capacitor switching circuit.

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