A stress regulation method based on a tunable MEMS Fabry-Perot cavity chip

Abstract

The present invention discloses a stress regulation method based on a tunable MEMS Fabry-Perot cavity chip. By regulating and coupling the key structures of the tunable MEMS Fabry-Perot chip, and then using a process method combining double-sided coating and single-sided coating for formal preparation, continuously monitoring the stress change of the back film, and finally using single-sided deposition of part of the back film for stress compensation. This method can completely solve the problem of easy stress mismatch of the tunable MEMS Fabry-Perot cavity chip, improve the manufacturing efficiency and manufacturing yield of the tunable MEMS Fabry-Perot cavity chip, and at the same time can meet the tunable range of different application scenarios, increasing its commercial value.

Description

Technical Field

[0001] The present invention relates to the technical field of stress regulation of MEMS Fabry - Perot cavity chips, and particularly to a stress regulation method based on a tunable MEMS Fabry - Perot cavity chip. Background Art

[0002] Optical filtering devices composed of tunable MEMS Fabry - Perot cavity chips have many advantages such as simple structure, high resolution, wide free spectral range, and strong customization ability, and have important application scenarios in the fields of spectral detection, spectral imaging, etc.

[0003] The main structure of a typical tunable MEMS Fabry - Perot cavity chip consists of two distributed Bragg reflectors (DBRs) and an intermediate cavity. During the process of electro - tuning, one of the DBR structures will generate displacement, which is called the moving mirror; the other DBR structure remains fixed and is called the fixed mirror. The tunable voltage range of the moving mirror is directly controlled by the stress of the corresponding DBR composite film layer, and the flatness of the fixed mirror is also related to the stress of its corresponding DBR composite film layer. In addition, during the entire preparation process of the tunable MEMS Fabry - Perot cavity chip, stress will also affect a series of processes such as wafer warping, patterning alignment, and sacrificial layer release. This results in extremely low yield of the existing tunable MEMS Fabry - Perot cavity chip manufacturing process, mismatched tunable ranges, and great difficulty in commercial promotion. Summary of the Invention

[0004] The purpose of the present invention is to provide a stress regulation method based on a tunable MEMS Fabry - Perot cavity chip to solve the above problems. The present invention aims to improve the yield during its preparation process, and at the same time, can meet the tunable ranges of different application scenarios, making it have greater commercial utilization value.

[0005] The present invention achieves the above - mentioned purpose through the following technical solutions:

[0006] A stress regulation method based on a tunable MEMS Fabry - Perot cavity chip, comprising the following steps:

[0007] Step 1: Use double - polished single - crystal Si as the substrate, deposit a SiO2 transition layer / lower DBR composite film layer on one side through a thermal oxidation process to form a coupling structure, and test the stress;

[0008] Step 2: Use double - polished single - crystal Si as the substrate, deposit an upper DBR composite film layer through a single - side process and perform annealing treatment, and test its stress;

[0009] Step 3: Use double - polished single - crystal Si as the substrate, deposit a TEOS sacrificial layer / upper DBR composite film layer coupling structure through a single - side process and perform annealing treatment, and test its stress;

[0010] Step 4: Use a thin film stress meter to measure the stress of the composite film layer and the coupling structure in Steps 2 and 3, and obtain the stress σ of the annealed upper DBR composite film layer u-DBR and the stress σ of the coupling structure of the annealed TEOS sacrificial layer / upper DBR composite film layer TEOS / DBR ; σ u-DBR is tensile stress, and the numerical range conforms to the tunable use range; and the stress of the coupling structure |σ TEOS / DBR | < 50 MPa; Meeting these two conditions is considered passed, and if these two conditions are not met, return to Steps 2 and 3 for further optimization until satisfied;

[0011] Step 5: Perform double-sided coating on a new double-polished single-crystalline Si wafer substrate according to the thin film parameters adjusted in Step 1. After the coating is completed, measure the thin film stress value with the back surface of the wafer as the reference plane, denoted as σ1;

[0012] Step 6: Based on Step 5, perform thin film deposition again according to the thin film parameters adjusted in Steps 2, 3, and 4. Among them, the TEOS thin film is deposited on the front side by PECVD, and the upper DBR composite film layer is deposited on both sides by LPCVD. After the deposition is completed, perform annealing treatment;

[0013] Step 7: Deposit an AL shielding film with a thickness of 800 to 2000 nm, an SiO2 antireflection film with a thickness of 100 to 1000 nm, and an Si3N4 antireflection film with a thickness of 100 to 1000 nm on the back surface of the wafer in Step 6 in sequence.

[0014] A further solution is that in Step 1, a double-polished single-crystalline Si wafer is used as the substrate, and an SiO2 thin film with a thickness of 200 to 400 nm is deposited on one side by a thermal oxidation process, and a poly / Si3N4 / poly / Si3N4 / poly five-layer film is deposited on the SiO2 thin film by an LPCVD process in sequence to form a lower DBR composite film layer; where the thickness of the poly film layer is 50 to 200 nm, and the thickness of the Si3N4 film layer is 100 nm to 300 nm.

[0015] A further solution is that in Step 1, the stress of the above coupling structure is measured by a thin film stress meter. When the stress value satisfies |σ SiO2 / DBR | < 50 MPa, it is considered passed through the coupling; if not, adjust the stress of the SiO2 thin film, poly thin film, or Si3N4 thin film according to the stress result until it is satisfied.

[0016] A further solution is that in step 2, a double-polished single-crystal Si wafer is used as the substrate, and six layers of poly / Si3N4 / poly / Si3N4 / poly / Si3N4 films are sequentially deposited on one side through the LPCVD process to form an upper DBR composite film layer, and annealing treatment is performed; the thickness of the poly film layer is 50 to 200 nm, and the thickness of the Si3N4 film layer is 0 to 300 nm.

[0017] A further solution is that in step 3, a double-polished single-crystal Si is used as the substrate, a TEOS sacrificial layer film of 1000 to 3000 nm is deposited on one side through the PECVD process, and an upper DBR composite film layer composed of six layers of poly / Si3N4 / poly / Si3N4 / poly / Si3N4 films is sequentially deposited on the TEOS sacrificial layer film by using the process parameters of step 2 to form a coupling structure, and finally annealing treatment under the same conditions is performed.

[0018] A further solution is that in step 6, the film stress is measured with the back surface of the wafer as the reference plane to obtain a new stress value σ2; the TEOS film on the front surface of the wafer is coupled with the upper DBR structure, while there is only the upper DBR structure with tensile stress on the back surface of the wafer, so σ2>0 at this time.

[0019] A further solution is that in step 7, the stress of these three film layers mainly compensates for the film stress on the back surface of the wafer in step 7, and its comprehensive stress must be compressive stress, and the numerical range depends on the size of σ2.

[0020] A further solution is that an AL electrode layer is also deposited on the front surface of the wafer.

[0021] A further solution is that in steps 5-7, the SiO2 transition layer is deposited on both sides by the thermal oxidation process, and the lower DBR composite film and the upper DBR composite film are both deposited on both sides by the LPCVD process to further offset the warping problem caused by stress. The TEOS sacrificial layer is deposited on the front surface by the PECVD process, and the antireflection film is composed of a SiO2 film and a Si3N4 film, both of which are deposited on the back surface by the PECVD process. During the whole preparation process, the stress is monitored by measuring the film stress on the back surface of the wafer.

[0022] A further solution is that in step 6, an annealing treatment is required after the front deposition of the TEOS sacrificial layer.

[0023] Since the TEOS sacrificial layer film is deposited on one side by the PECVD process, stress is bound to be generated after annealing, which will affect the flatness of the wafer. Subsequently, the stress can be compensated by depositing a back Al shielding film and an antireflection composite film, so that the absolute value of the overall stress of the back film is less than 50 MPa.

[0024] The beneficial effects of the present invention are as follows:

[0025] Regulate the stresses of two key coupling structures, namely the SiO2 transition layer / lower DBR composite film layer and the TEOS sacrificial layer / upper DBR composite film layer, so that the absolute values of their stresses are both less than 50 MPa. This improves the flatness of the wafer during the manufacturing process and reduces the process risks of the key film layers;

[0026] Regulate the stress of the upper DBR movable composite film layer structure in advance, meeting the requirements of the tunable range, which greatly improves the manufacturing efficiency and manufacturing yield of the tunable MEMS Fabry-Perot cavity chip;

[0027] Multiple composite film layers all adopt the double-sided deposition process, which further ensures the flatness of the wafer during the preparation of the tunable MEMS Fabry-Perot cavity chip and brings convenience to some high-precision patterning processes;

[0028] The backside AL shielding layer and the antireflection composite film can perform stress compensation in real time according to the stress value after annealing, thereby continuously balancing the stresses of the thin films on both sides of the wafer and ensuring that all process flows can be successfully completed;

[0029] Both the overall and local composite film layers adopt multiple stress regulation measures, completely solving the problem of easy stress mismatch in the tunable MEMS Fabry-Perot cavity chip. Brief Description of the Drawings

[0030] To more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for use in the embodiments or the description of the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0031] Figure 1 It is a schematic diagram of a stress regulation method for a tunable MEMS Fabry-Perot cavity chip according to the present invention;

[0032] Figure 2 It is a schematic cross-sectional view of the overall structure of a tunable MEMS Fabry-Perot cavity chip;

[0033] Figure 3 It is a schematic cross-sectional view of the stress regulation coupling structure of the transition layer SiO2 / lower DBR composite film;

[0034] Figure 4 It is a schematic cross-sectional view of the stress regulation structure of the single upper DBR composite film;

[0035] Figure 5 It is a schematic cross-sectional view of the stress regulation coupling structure of the sacrificial layer TEOS / upper DBR composite film;

[0036] Figure 6It is a schematic diagram of the stress regulation values of three key structures of a tunable MEMS Fabry-Perot cavity chip;

[0037] Figure 7 It is a schematic diagram of the change of the comprehensive stress of the thin film on the back side of the wafer of the tunable MEMS Fabry-Perot cavity chip during the manufacturing process. Detailed implementation manners

[0038] To make the objectives, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be described in detail below. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other implementation manners obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the scope protected by the present invention.

[0039] In any embodiment, as Figure 1-7 shown, the present invention provides a stress regulation method for a MEMS Fabry-Perot cavity chip with a tunable range conforming to the 1750 - 2150 nm band, including the following steps:

[0040] Step 1: Use a double-polished single-crystalline Si wafer as a substrate, deposit a SiO2 thin film with a thickness of 200 to 400 nm on one side through a thermal oxidation process, and sequentially deposit a five-layer film of poly / Si3N4 / poly / Si3N4 / poly on the SiO2 thin film through an LPCVD process to form a lower DBR composite film layer. The thickness of the poly film layer is 50 to 200 nm, and the thickness of the Si3N4 film layer is 100 nm to 300 nm;

[0041] Step 2: Measure the stress of the above coupling structure through a thin film stress meter. When the stress value satisfies |σ SiO2 / DBR | < 50 MPa, it is considered passed. If not, return to Step 1 to adjust the stress of the SiO2 thin film, poly thin film or Si3N4 thin film according to the stress result until it is satisfied;

[0042] Step 3: Take a new double-polished single-crystalline Si wafer as a substrate, and sequentially deposit a six-layer film of poly / Si3N4 / poly / Si3N4 / poly / Si3N4 on one side through an LPCVD process to form an upper DBR composite film layer, and perform an annealing treatment. The thickness of the poly film layer is 50 to 200 nm, and the thickness of the Si3N4 film layer is 0 to 300 nm;

[0043] Step 4: Take a new double-polished single-crystalline Si wafer as the substrate, deposit a TEOS sacrificial layer film with a thickness of 1000 to 3000 nm on one side through the PECVD process, and deposit an upper DBR composite film layer composed of six layers of poly / Si3N4 / poly / Si3N4 / poly / Si3N4 in sequence on the TEOS sacrificial layer film using the process parameters of Step 3 to form a coupling structure. Finally, perform an annealing treatment under the same conditions;

[0044] Step 5: Use a thin-film stress meter to measure the stress of the composite film layer and the coupling structure in Step 3 and Step 4, and obtain the stress σ of the annealed upper DBR composite film layer u-DBR and the coupling structure of the annealed TEOS sacrificial layer / upper DBR composite film layer

[0045] stress σ TEOS / DBR . It is required that σ u-DBR is tensile stress, and the numerical range meets the tunable use range; and the stress of the coupling structure |σ TEOS / DBR |<50 MPa. Meeting these two conditions means passing. If these two conditions are not met, return to Step 3 and Step 4 for further optimization until satisfied;

[0046] Step 6: Perform double-sided coating on a new double-polished single-crystalline Si wafer substrate according to the thin-film parameters adjusted in Step 1 and Step 2. After the coating is completed, measure the thin-film stress value with the back side of the wafer as the reference plane, and record it as σ1;

[0047] Step 7: Based on Step 6, deposit the thin film again according to the thin-film parameters adjusted in Step 3, Step 4, and Step 5. Among them, the TEOS thin film is deposited on the front side by PECVD, and the upper DBR composite film layer is deposited on both sides by LPCVD. After the deposition is completed, perform an annealing treatment. Measure the thin-film stress with the back side of the wafer as the reference plane to obtain a new stress value σ2. Since the TEOS thin film on the front side of the wafer is coupled with the upper DBR structure, and there is only the upper DBR structure with tensile stress on the back side of the wafer, so σ2>0 at this time;

[0048] Step 8: Deposit an AL shielding film with a thickness of 800 to 2000 nm, an SiO2 antireflection film with a thickness of 100 to 1000 nm, and an Si3N4 antireflection film with a thickness of 100 to 1000 nm on the back side of the wafer in Step 7 in sequence. The stress of these three film layers mainly compensates for the thin-film stress on the back side of the wafer in Step 7, and its comprehensive stress must be compressive stress, and the numerical range depends on the size of σ2;

[0049] Step 9: Finally, deposit an AL electrode layer on the front side of the wafer. Since the area reserved after patterning is extremely small, the stress can be ignored.

[0050] After the front deposition of the TEOS sacrificial layer, an annealing treatment will be carried out to break the stress balance. Subsequently, the Al shielding film and the SiO2 / Si3N4 antireflection composite film deposited on the back need to compensate for the unbalanced stress value, so that the absolute value of the overall film stress on the back is less than 50 MPa.

[0051] The prepared product is as Figure 2 shown, which is a schematic cross-sectional view of the overall structure of the tunable MEMS Fabry-Perot cavity chip. It is a double-sided structure, including a double-polished single-crystal Si substrate 1. A SiO2 thin film layer 2 is deposited on the single-crystal Si substrate 1 through a double-sided thermal oxidation process; and the SiO2 thermal oxidation thin film layer is distributed with a lower DBR composite film 3. Then, a TEOS thin film 4 is distributed on the lower DBR composite film 3 on the front. Then, the upper DBR composite film 5 is continuously deposited on both sides. Then, an Al shielding layer 7 and an antireflection film 6 are deposited on the upper DBR composite film 5 on the back. Finally, the designed AL electrode layer 8 is distributed on the upper DBR composite film 3 on the front. According to the thickness values of each film layer, stress regulation is carried out. Finally, the combined stress of the SiO2 thermal oxidation thin film layer / lower DBR composite film layer needs to be relatively low, with an absolute value less than 50 MPa. The schematic cross-sectional view of the stress regulation coupling structure is as Figure 3 shown; the stress of the upper DBR composite film layer after annealing needs to be tensile stress and meet the simulation value of the tunable range. The schematic cross-sectional view of the stress regulation structure is as Figure 4 shown; the combined stress of the TEOS thin film / upper DBR composite film layer after annealing needs to be relatively low, and the absolute value is also less than 50 MPa. The schematic cross-sectional view of the stress regulation coupling structure is as Figure 5 shown.

[0052] In this embodiment, the single-crystal Si substrate is double-sided polished with a thickness of 300 to 1000 um, the thickness of the SiO2 thin film transition layer is 200 to 400 nm, the thickness of the poly thin film in the lower DBR composite film is 50 to 200 nm, the thickness of the Si3N4 thin film is 100 to 300 nm, the thickness of the TEOS sacrificial layer thin film is 1000 to 3000 nm, the thickness of the poly thin film in the upper DBR composite film is 50 to 200 nm, the thickness of the Si3N4 thin film is 0 to 300 nm, the thickness of the Al shielding layer and the AL electrode layer is 800 to 2000 nm, the thickness of the SiO2 thin film in the antireflection film is 100 to 1000 nm, and the thickness of the Si3N4 thin film is 100 to 1000 nm.

[0053] The regulation process and stress values of the present invention are as follows:

[0054] First, on three double-polished single-crystalline Si wafers, two stress coupling structures of SiO2 / lower DBR composite film layer and TEOS / upper DBR composite film layer (annealed) are respectively deposited on the front side, and the upper DBR composite film layer (annealed) is deposited on the front side alone. Then, the stress of each film layer of these three key structures is regulated, and finally the stress values that meet the conditions are obtained as Figure 6 shown. Among them, the stress of the SiO2 / lower DBR coupling structure is -22.46 MPa, and the absolute value is less than 50 MPa; the stress of the upper DBR composite film layer after annealing alone is a tensile stress of 506 MPa, meeting the requirements of the tunable range; the stress of the TEOS / upper DBR coupling structure after annealing is -25.77 MPa, and the absolute value is less than 50 MPa.

[0055] Using the above-regulated stress parameters, it is formally prepared on a double-polished single-crystalline Si substrate, and the stress during the preparation process is monitored by measuring the stress of the back film layer. As Figure 7 shown, first, SiO2 thin films are deposited on both sides through a thermal oxidation process, and the stress value of the back film is measured to be -1.16 MPa; next, the lower DBR composite film layer is deposited on both sides by LPCVD process, and the stress value of the back film is measured to be -2.2 MPa; next, TEOS thin film is deposited on the front side by PECVD process, and the stress value of the back film is measured to be 9.01 MPa; next, the upper DBR composite film layer is deposited on both sides by LPCVD process and annealed, and the stress value of the back film is measured to be 265 MPa; next, AL film is deposited on the back by electron beam evaporation, and the stress value of the back film is measured to be 102.9 MPa; finally, SiO2 / Si3N4 antireflection composite film is deposited on the back by PECVD process, and at this time the stress of the back film is measured to be 40.22 MPa, and the absolute value is less than 50 MPa. In this way, the finally fabricated tunable MEMS Fabry-Perot cavity structure meets various requirements of the process and performance.

[0056] As described above, it is only the specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention can easily think of changes or substitutions, which should all be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claimed rights. In addition, it should be noted that in the above specific implementation manner, the various specific technical features described can be combined in any appropriate manner without contradiction. To avoid unnecessary repetition, the present invention will not separately describe various possible combination methods. In addition, any combination can be made between different embodiments of the present invention as long as it does not violate the idea of the present invention, and it should also be regarded as the content disclosed by the present invention.

Claims

1. A stress regulation method based on a tunable MEMS Fabry - Perot cavity chip, characterized in that, It includes the following steps: Step 1: Using double-polished single-crystalline Si as the substrate, deposit the SiO2 transition layer / lower DBR composite film layer on one side through a thermal oxidation process to form a coupling structure, and test the stress. In Step 1, deposit a 200 - 400 nm thick SiO2 thin film through a thermal oxidation process, and sequentially deposit five layers of poly / Si3N4 / poly / Si3N4 / poly on the SiO2 thin film through the LPCVD process to form the lower DBR composite film layer; Step 2: Using double-polished single-crystalline Si as the substrate, deposit the upper DBR composite film layer through a single-side process and perform an annealing treatment, and test its stress. In Step 2, sequentially deposit six layers of poly / Si3N4 / poly / Si3N4 / poly / Si3N4 on one side through the LPCVD process to form the upper DBR composite film layer; Step 3: Using double-polished single-crystalline Si as the substrate, deposit the TEOS sacrificial layer / upper DBR composite film layer coupling structure through a single-side process and perform an annealing treatment, and test its stress; In Step 3, deposit a 1000 - 3000 nm TEOS sacrificial layer thin film on one side through the PECVD process, and sequentially deposit the upper DBR composite film layer composed of six layers of poly / Si3N4 / poly / Si3N4 / poly / Si3N4 on the TEOS sacrificial layer thin film using the process parameters of Step 2 to form a coupling structure; Step 4: Use a thin-film stress meter to measure the stress of the composite film layer and the coupling structure in Steps 2 and 3, and obtain the stress σ of the upper DBR composite film layer after annealing u-DBR and the stress σ of the coupling structure of the TEOS sacrificial layer / upper DBR composite film layer after annealing TEOS / DBR ; σ u-DBR is tensile stress, and the numerical range meets the tunable use range; and the stress of the coupling structure |σ TEOS / DBR |< 50 MPa; Meeting these two conditions means passing, and not meeting these two conditions means returning to Steps 2 and 3 for further optimization until satisfied; Step 5: Perform double-sided coating on a new double-polished single-crystalline Si wafer substrate according to the adjusted film parameters in Step 1. After the coating is completed, measure the film stress value with the back surface of the wafer as the reference surface, denoted as σ1; Step 6: Based on Step 5, perform film deposition again according to the adjusted film parameters in Step 2, Step 3, and Step 4. Among them, the TEOS thin film is deposited on the front side through PECVD, and the upper DBR composite film layer is deposited on both sides through LPCVD. After the deposition is completed, perform an annealing treatment; Step 7: Sequentially deposit an AL shielding film with a thickness of 800 - 2000 nm, an SiO2 antireflection film with a thickness of 100 - 1000 nm, and an Si3N4 antireflection film with a thickness of 100 - 1000 nm on the back surface of the wafer in Step 6.

2. The stress regulation method based on a tunable MEMS Fabry - Perot cavity chip according to claim 1, characterized in that, In Step 1, the thickness of the poly film layer is 50 - 200 nm, and the thickness of the Si3N4 film layer is 100 nm - 300 nm.

3. The stress regulation method based on a tunable MEMS Fabry - Perot cavity chip according to claim 1, characterized in that, In the above step 1, the stress of the above coupling structure is measured by a thin film stress meter. When the stress value satisfies |σ SiO2 / DBR | < 50 MPa, it is considered to pass the coupling; if not, the stress of the SiO2 thin film, poly thin film or Si3N4 thin film is adjusted according to the stress result until it is satisfied.

4. The stress regulation method based on a tunable MEMS Fabry - Perot cavity chip according to claim 1, characterized in that, In Step 2, the thickness of the poly film layer is 50 - 200 nm, and the thickness of the Si3N4 film layer is 0 - 300 nm.

5. The stress regulation method based on a tunable MEMS Fabry - Perot cavity chip according to claim 1, characterized in that, In Step 6, measure the film stress with the back surface of the wafer as the reference surface to obtain a new stress value σ2; The TEOS thin film on the front side of the wafer is coupled with the upper DBR structure, while there is only the upper DBR structure with tensile stress on the back surface of the wafer. Therefore, σ2 > 0 at this time.

6. The stress regulation method based on a tunable MEMS Fabry - Perot cavity chip according to claim 1, characterized in that, In Step 7, the stress of these three film layers mainly compensates for the film stress on the back surface of the wafer in Step 7, and its combined stress must be compressive stress, and the numerical range depends on the size of σ2.

7. The stress regulation method based on a tunable MEMS Fabry - Perot cavity chip according to claim 1, characterized in that, It also includes depositing an AL electrode layer on the front side of the wafer.

8. The stress regulation method based on a tunable MEMS Fabry - Perot cavity chip according to claim 1, characterized in that, In the steps 5-7, the SiO2 transition layer is deposited on both sides by thermal oxidation process, the lower DBR composite film and the upper DBR composite film are both deposited on both sides by LPCVD process, the TEOS sacrificial layer is deposited on the front side by PECVD process, the antireflection film is composed of SiO2 thin film and Si3N4 thin film, and both are deposited on the back side by PECVD process. During the whole preparation process, the stress is monitored by measuring the stress of the thin film on the back side of the wafer.

9. The stress regulation method based on a tunable MEMS Fabry - Perot cavity chip according to claim 1, characterized in that, In the step 6, an annealing treatment is required after the front-side deposition of the TEOS sacrificial layer.

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