A time-to-digital converter, time measurement method and related apparatus

Abstract

This application provides a time-to-digital converter, a time measurement method, and related equipment, which have high time measurement accuracy. The time-to-digital converter includes: a coarse time counting unit, a fine time counting unit, a buffer unit, and a processing unit. The coarse time counting unit receives a first clock signal and a test input signal, and counts from a reference time until the test input signal is received, using one clock cycle t of the first clock signal as the counting clock, to obtain a coarse time result for the test input signal. The fine time counting unit includes a carry chain; wherein the timing length of the carry chain is greater than 2t, and the carry chain includes n adders cascaded together. The processing unit is coupled to the buffer unit and is used to: monitor the output results of the n adders based on the first clock signal; and determine the fine time result of the test input signal based on the two obtained output results of the n adders.

Description

Technical Field

[0001] This application relates to the field of electronic technology and discloses a time-to-digital converter, a time measurement method, and related equipment. Background Technology

[0002] Currently, lidar technology requires high measurement accuracy. For example, applying lidar technology in surveying scenarios can reduce target deviation. Alternatively, adding lidar to vehicles can enable accurate distance determination of obstacles. For lidar technology, accurately measuring the laser's time of flight is crucial for improving ranging accuracy. A time measurement accuracy at the picosecond level can enable lidar ranging accuracy to the centimeter level. Therefore, time measurement is extremely important for lidar technology. Improving time measurement accuracy is a problem that urgently needs to be solved. Summary of the Invention

[0003] This application provides a time-to-digital converter, a time measurement method, and related equipment, which have high time measurement accuracy.

[0004] In a first aspect, embodiments of this application provide a time-to-digital converter, including: a coarse time counting unit, a fine time counting unit, a buffer unit, and a processing unit;

[0005] The coarse time counting unit is used to receive a first clock signal and a test input signal, and to count from a reference time until the test input signal is received, according to one clock period t of the first clock signal as the counting clock, so as to obtain the coarse time result of the test input signal.

[0006] The fine-time counting unit includes a carry chain; wherein the timing length of the carry chain is greater than 2t, the carry chain includes n adders, where n is a positive integer greater than 1, the n adders are cascaded, wherein the carry input terminal of the first-stage adder is used to receive the input signal to be measured; the carry input terminal of the i-th stage adder is coupled to the carry output terminal of the (i-1)-th stage adder, where i takes any integer from 2 to n;

[0007] The buffer unit is coupled to the carry output terminal of each of the n adders, and is used to buffer the output results of the carry output terminals of the n adders;

[0008] The processing unit is coupled to the cache unit and is used for:

[0009] Based on the first clock signal, monitor the output results of the n adders;

[0010] Based on the output results of the n adders obtained twice, the fine time result of the input signal under test is determined, wherein the coarse time result and the fine time result are used to determine the time measurement result of the input signal under test.

[0011] In one possible implementation, this application provides a time-to-digital converter in which the processing unit is specifically used for:

[0012] At the first rising edge of the first clock signal, the output results of the n adders are obtained;

[0013] If the output of the n adders obtained at the first rising edge is different from the preset initial result, and the adder with the largest level among the adders that carry at the first rising edge is the first-level adder, then the output of the n adders is obtained at the second rising edge, wherein the second rising edge is the first rising edge after the first rising edge.

[0014] If the output of the n adders obtained at the first rising edge is different from the preset initial result, and the adder with the largest level among the adders that carry at the first rising edge is not the first-level adder, then the output of the n adders is obtained at the second rising edge and the third rising edge, wherein the third rising edge is the second rising edge after the first rising edge.

[0015] In one possible implementation, this application provides a time-to-digital converter in which the processing unit is further configured to:

[0016] If the adder with the largest level among the adders that carry at the first rising edge is not the first-level adder, the first adder with the largest level among the adders that carry at the first rising edge is determined based on the output result obtained at the first rising edge; or, if the adder with the largest level among the adders that carry at the first rising edge is the first-level adder, the first adder with the largest level among the adders that carry at the third rising edge is determined based on the output result obtained at the third rising edge.

[0017] Based on the output obtained at the second rising edge, determine the second adder with the largest number of stages among the adders that have carried at the second rising edge.

[0018] And based on the first adder and the second adder, the fine-time result of the input signal under test is determined.

[0019] In one possible implementation, this application provides a time-to-digital converter where each adder has a pre-configured start time; the start time of the first-stage adder is configured as a first value; the difference between the start time of the i-th-stage adder and the first value is the timing length of the first i-1 stages of adders; the processing unit is specifically used for:

[0020] If the difference between the start time of the second adder and the start time of the first adder is less than t, the difference between the start time of the first adder and t is taken as the first candidate fine time result;

[0021] If the difference between the start time of the second adder and the start time of the first adder is equal to or greater than t, the difference between the start time of the second adder and 2t is taken as the first candidate fine time result;

[0022] Based on the first candidate fine time result, the fine time result of the input signal to be measured is determined.

[0023] In one possible implementation, this application provides a time-to-digital converter where each adder has a pre-configured end time; the start time of the first-stage adder is configured as a first value, and the difference between the end time of the first-stage adder and the first value is the timing length of the first-stage adder; the difference between the end time of the i-th-stage adder and the first value is the timing length of the i-th-stage adder; the processing unit is further configured to:

[0024] If the difference between the end time of the second adder and the end time of the first adder is less than t, the difference between the end time of the second adder and 2t is taken as the second candidate fine time result;

[0025] If the difference between the end time of the second adder and the end time of the first adder is equal to or greater than t, the difference between the end time of the first adder and t is taken as the second candidate fine time result;

[0026] Based on the second candidate fine time result, the fine time result of the input signal to be measured is determined.

[0027] In one possible implementation, this application provides a time-to-digital converter in which the processing unit is specifically used for:

[0028] Based on the candidate set, the fine-time result of the input signal to be tested is determined, wherein the minimum value in the candidate set is the first candidate result, and the maximum value in the candidate set is the second candidate result;

[0029] If the adder with the largest number of stages among the adders that carry at the first rising edge is the first-stage adder, then any value in the candidate set is the fine-time result of the input signal to be measured.

[0030] If the adder with the largest number of stages among the adders that carry at the first rising edge is the first-stage adder, then the sum of any value in the candidate set and t is the fine-time result of the input signal to be measured.

[0031] Secondly, embodiments of this application provide a time measurement method that can be applied to time-to-digital converters as described in the first aspect and any possible implementation thereof. The method includes:

[0032] The input signal to be tested is counted according to one clock period t of the first clock signal to obtain a coarse time result of the input signal to be tested.

[0033] Based on the first clock signal, monitor the output results of the n adders;

[0034] Based on the output results of the n adders obtained twice, the fine-time result of the input signal to be tested is determined.

[0035] In one possible implementation, in a time measurement method provided in this application, monitoring the output results of the n adders includes:

[0036] At the first rising edge of the first clock signal, the output results of the n adders are obtained;

[0037] If the output of the n adders obtained at the first rising edge is different from the preset initial result, and the adder with the largest level among the adders that carry at the first rising edge is the first-level adder, then the output of the n adders is obtained at the second rising edge, wherein the second rising edge is the first rising edge after the first rising edge.

[0038] If the output of the n adders obtained at the first rising edge is different from the preset initial result, and the adder with the largest level among the adders that carry at the first rising edge is not the first-level adder, then the output of the n adders is obtained at the second rising edge and the third rising edge, wherein the third rising edge is the second rising edge after the first rising edge.

[0039] In one possible implementation, in a time measurement method provided in this application, if the output result of the adder obtained at the first rising edge is different from the preset initial result, the step of determining the fine time result of the input signal to be measured based on the output results of the n adders obtained twice includes:

[0040] If the adder with the largest level among the adders that carry at the first rising edge is not the first-level adder, the first adder with the largest level among the adders that carry at the first rising edge is determined based on the output result obtained at the first rising edge; or, if the adder with the largest level among the adders that carry at the first rising edge is the first-level adder, the first adder with the largest level among the adders that carry at the third rising edge is determined based on the output result obtained at the third rising edge.

[0041] Based on the output obtained at the second rising edge, determine the second adder with the largest number of stages among the adders that have carried at the second rising edge.

[0042] And based on the first adder and the second adder, the fine-time result of the input signal under test is determined.

[0043] In one possible implementation, in a time measurement method provided in this application embodiment, each adder has a pre-configured start time; the start time of the first-stage adder is configured as a first value; the difference between the start time of the i-th-stage adder and the first value is the timing length of the first i-1 stages of adder;

[0044] The step of determining the fine-time result of the input signal under test based on the first adder and the second adder includes:

[0045] If the difference between the start time of the second adder and the start time of the first adder is less than t, the difference between the start time of the first adder and t is taken as the first candidate fine time result;

[0046] If the difference between the start time of the second adder and the start time of the first adder is equal to or greater than t, the difference between the start time of the second adder and 2t is taken as the first candidate fine time result;

[0047] Based on the first candidate fine time result, the fine time result of the input signal to be measured is determined.

[0048] In one possible implementation, in a time measurement method provided in this application embodiment, each adder has a pre-configured end time; the start time of the first-stage adder is configured as a first value, and the difference between the end time of the first-stage adder and the first value is the timing length of the first-stage adder; the difference between the end time of the i-th-stage adder and the first value is the timing length of the i-th-stage adder.

[0049] The step of determining the fine-time result of the input signal under test based on the first adder and the second adder further includes:

[0050] If the difference between the end time of the second adder and the end time of the first adder is less than t, the difference between the end time of the second adder and 2t is taken as the second candidate fine time result;

[0051] If the difference between the end time of the second adder and the end time of the first adder is equal to or greater than t, the difference between the end time of the first adder and t is taken as the second candidate fine time result;

[0052] Based on the second candidate fine time result, the fine time result of the input signal to be measured is determined.

[0053] In one possible implementation, in a time measurement method provided in this application, determining the fine-time result of the input signal to be measured includes:

[0054] Based on the candidate set, the fine-time result of the input signal to be tested is determined, wherein the minimum value in the candidate set is the first candidate result, and the maximum value in the candidate set is the second candidate result;

[0055] If the adder with the largest number of stages among the adders that carry at the first rising edge is the first-stage adder, then any value in the candidate set is the fine-time result of the input signal to be measured.

[0056] If the adder with the largest number of stages among the adders that carry at the first rising edge is the first-stage adder, then the sum of any value in the candidate set and t is the fine-time result of the input signal to be measured.

[0057] Thirdly, embodiments of this application also provide an electronic device, including: a transmitting module, a receiving module, and a time-to-digital converter that can be applied as in the first aspect and any possible implementation thereof.

[0058] The transmitting module is used to transmit optical signals;

[0059] The receiving module is used to receive the input signal to be tested, which is the light signal reflected by the obstacle;

[0060] The time-to-digital converter is used to measure the time of flight of the optical signal.

[0061] Fourthly, a computer-readable storage medium storing computer instructions that, when executed on a processor, cause the processor to perform a time measurement method as provided in the second aspect and any possible implementation thereof.

[0062] Fifthly, embodiments of this application provide a computer program product comprising a computer program that, when executed by a processor, implements the steps of the time measurement method provided in the second aspect and any possible implementation thereof.

[0063] The beneficial effects of the embodiments of this application are as follows:

[0064] A time-to-digital converter, a time measurement method, and related equipment are disclosed, featuring high time measurement accuracy. The timing length of the carry chain in the fine-time counting unit is greater than twice the clock period t of the clock signal. The processing unit uses the output results of the two acquired carry chains to determine the fine-time result of the input signal under test. The technical solution provided in this application eliminates the need for multiple carry chains, reducing resource consumption. Furthermore, the time-to-digital converter provided in this application achieves high timing accuracy, avoiding the impact of excessively long delays. It eliminates the need for additional modulation and encoding / decoding of the input signal under test, resulting in high real-time performance.

[0065] Other features and advantages of this application will be set forth in the following description and will be apparent in part from the description or may be learned by practicing the application. The objectives and other advantages of this application may be realized and obtained by means of the structures particularly pointed out in the written description, claims, and drawings. Attached Figure Description

[0066] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0067] Figure 1 This is a schematic diagram illustrating an application scenario provided in the embodiments of this application;

[0068] Figure 2 This is a schematic diagram of the structure of a time-to-digital converter;

[0069] Figure 3 This is a schematic diagram of the structure of a time-to-digital converter provided in an embodiment of this application;

[0070] Figure 4a This is a schematic diagram of the structure of a time-to-digital converter provided in an embodiment of this application;

[0071] Figure 4b This is a schematic diagram of an adder provided in an embodiment of this application;

[0072] Figure 4c A schematic diagram illustrating the relationship between the carry chain and the clock cycle in a time-to-digital converter provided in this application embodiment;

[0073] Figure 5 A flowchart of a time measurement method provided in an embodiment of this application;

[0074] Figure 6 A flowchart of a time measurement method provided in an embodiment of this application;

[0075] Figure 7 A flowchart of a time measurement method provided in an embodiment of this application;

[0076] Figure 8 A flowchart of a time measurement method provided in an embodiment of this application;

[0077] Figure 9 A flowchart of a time measurement method provided in an embodiment of this application;

[0078] Figure 10 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0079] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings of the embodiments of this application. Obviously, the described embodiments are only some embodiments of the technical solutions of this application, and not all embodiments. Based on the embodiments recorded in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the technical solutions of this application.

[0080] In surveying, mapping, and automotive applications, high ranging accuracy is crucial for LiDAR. Low accuracy can lead to target deviations and vehicles failing to accurately determine obstacle distances. Using only a standard digital system clock for laser time-of-flight calculation results in significant errors. For example, a 200MHz system clock provides a time measurement accuracy of one clock cycle (4ns). However, the speed of light is 0.3 m / ns, and the measurement of laser time-of-flight results in an error of 0.6 m (0.5 × 0.3 m / ns × 4ns). Such accuracy is insufficient for applications like driver assistance and surveying.

[0081] To address the issue of low timing accuracy in ordinary digital systems, dedicated time-to-digital converter (TDC) chips or carry chains of field-programmable gate arrays (FPGAs) can be used to achieve high-precision time measurement. If lidar technology achieves centimeter-level ranging accuracy, the corresponding time measurement technology can achieve picosecond-level timing accuracy.

[0082] Currently, the method of interpolating clock cycles using delay chains constructed from carry-in addition is widely used. However, this method still suffers from measurement errors, as each delay unit is inconsistent, which is determined by the chip manufacturing process. Furthermore, redundant traces and crossing clock regions can further increase the delay.

[0083] Figure 1 This paper illustrates an application scenario of a time-to-digital converter (TD-RCD). In lidar technology, a lidar system may include functional components such as a transmitting module, a receiving module, and a TDC. The transmitting module emits a light signal, which is reflected by an obstacle and received by the receiving module. The TDC measures the time of flight (tof_a) of the light signal, which is the duration between the moment the transmitting module emits the light signal (a1) and the moment the receiving module receives the reflected light signal (a2), where tof_a = a2 - a1. The distance between the lidar and the obstacle can be determined using the time of flight (tof_a) and the speed of light. Therefore, accurate measurement of tof_a can improve the ranging accuracy of the lidar.

[0084] Currently, the relevant technology uses a time-to-digital converter to measure the flight time of optical signals. Figure 2 The illustration shows a time-to-digital converter in the related art, which may include a coarse time counting module and a fine time counting module. The coarse time counting module can use one clock cycle b of a preset clock signal as the counting clock, and the counting result can be used to determine the coarse time result. The fine time counting module uses a carry chain, and the timing length of the carry chain is equal to one clock cycle b.

[0085] Both the coarse and fine time counting modules are housed within the chip. The optical signal is converted into an electrical signal via a photoelectric conversion circuit and input to the chip's pins. An input buffer (IBUF) typically exists between the chip's pins and the fine time counting module. The relatively long traces between these modules result in greater delays, leading to an ultra-wide bin. To improve time measurement resolution in ultra-wide bin conditions, this application provides a time-to-digital converter, a time measurement method, and related equipment, which can achieve higher time measurement resolution, i.e., higher time measurement accuracy.

[0086] Figure 3 An exemplary schematic diagram of a time-to-digital converter (TDD) is shown. The TDD can receive a test input signal. In some scenarios, the light signal emitted by the transmitting module is reflected by an obstacle, i.e., a reflected light signal. The signal output by the photoelectric conversion circuit after the reflected light signal is reflected can be the aforementioned test input signal. The time of the light signal emitted by the transmitting module can be recorded as a reference time. The TDD can be used to measure the duration between the time the test input signal is received and the reference time, thereby enabling time measurement of the test input signal and facilitating the measurement of the time of flight of the light signal.

[0087] In one possible design, the time-to-digital converter can receive a first clock signal for time measurement. In another possible design, the time-to-digital converter may include a clock signal generation module that generates a first clock signal St for time measurement. It should be understood that the first clock signal in this art is a periodic signal. In the embodiments of this application, one clock period of the first clock signal St is denoted as t, and the specific value can be configured according to the actual application scenario.

[0088] The time-to-digital converter provided in this application embodiment may include a coarse time counting unit, a fine time counting unit, a buffer unit, and a processing unit. The coarse time counting unit can be used to measure coarse time results. The fine time counting unit can be used to measure fine time results t1. The sum of the coarse time results and the fine time results t2 can be used as the time measurement result tof_total of the input signal under test, that is, tof_total = t1 + t2.

[0089] The processing unit can be coupled (or connected) to the coarse time counting unit, fine time counting unit, and buffer unit respectively, so as to control each unit or exchange data with each unit.

[0090] The coarse-time counting unit can receive a first clock signal and has the capability to count according to one clock cycle t of the first clock signal. In other words, the coarse-time counting unit can increment the count by 1 every time the first clock signal passes one clock cycle.

[0091] The coarse time counting unit can start counting from a reference time and stop counting when the input signal under test is received. In some scenarios, the reference time can be pre-configured. In other scenarios, the reference time can be the time when the aforementioned transmitting module transmits the optical signal. The coarse time counting unit starts counting from the reference time and continues until the input signal under test is received. The counting result provided by the coarse time counting unit can be used to determine the coarse time result. For example, the counting result provided by the coarse time counting unit is c1, and the value of the coarse time result t1 is c1×t.

[0092] Optionally, the transmitting module may also receive the same first clock signal. The transmitting module may transmit the optical signal at the rising edge of the first clock signal. The coarse time counting unit may increment the count by 1 at the rising edge of the first clock signal. Alternatively, the transmitting module may transmit the optical signal at the falling edge of the first clock signal. The coarse time counting unit may increment the count by 1 at the falling edge of the first clock signal. Alternatively, the coarse time counting unit may employ any existing coarse time result determination method, which is not limited in this application. It is understood that the coarse time counting unit may include a corresponding circuit structure to implement the function of the coarse time unit described above, which is not specifically limited in this application.

[0093] In this embodiment, the fine-time counting unit may include a carry chain. The timing length of the carry chain is greater than 2t. That is, the timing length of the carry chain can be greater than twice the aforementioned time period. Figure 4a The diagram below illustrates the specific structure of a fine-time counting unit. The fine-time counting unit may include a carry chain. This carry chain may include n adders, cascaded together. Each adder may be a full adder. A full adder may include a carry input (Cin), a fixed input port A, a fixed input port B, an sum output (sum), and a carry output (Cout). The relationship between the input ports and output ports of the full adder is shown in the following truth table:

[0094] A B Cin sum Cout 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 1 1 0 0 1 0 0 1 1 0 1 0 1 0 1 0 1 1 0 1 1 1 1 1 1

[0095] In the embodiments of this application, such as Figure 4bAs shown, the fixed input port A of each adder in the carry chain is connected to a first voltage level. The fixed input port B of each adder is connected to a second voltage level. The first and second voltage levels can be low and high, respectively. Alternatively, the first and second voltage levels can be high and low, respectively. For ease of explanation, "0" represents a low voltage level, and "1" represents a high voltage level. It should be understood that in this application, the fixed input ports A and B of each adder in the carry chain are connected to two different fixed voltage levels.

[0096] The carry-in terminal of the first-stage adder is used to receive the input signal to be tested. The carry-in terminal of the i-th-stage adder is coupled to the carry-out terminal of the (i-1)-th-stage adder. The i-th value is any integer from 2 to n.

[0097] For example, the carry input of the second-stage adder is coupled to the carry output of the first-stage adder. The carry input of the nth-stage adder is coupled to the carry output of the (n-1)th-stage adder. For each stage adder, since the fixed input ports A and B of each stage adder are 0 and 1 respectively, the output signal of the carry output is related to the input signal of the carry input. For example, if the input signal of the carry input of the i-th-stage adder is 0, then the output signal of the carry output is 0, meaning that no carry has occurred in the i-th-stage adder. Conversely, if the input signal of the carry input of the i-th-stage adder is 1, then the output signal of the carry output is 1, meaning that a carry has occurred in the i-th-stage adder.

[0098] The function of each adder stage described above can be implemented by combining multiple existing half-adders and logic gates, such as... Figure 4b As shown. It should be noted that the embodiments of this application do not limit the specific structure of the adder. Any circuit in the art that can realize the function of each stage of the adder described above can be used as an adder.

[0099] The buffer unit in the time-to-digital converter can be coupled to the carry-out output of each adder. The buffer unit can buffer the outputs of n adders. Optionally, the buffer unit can include n D flip-flops, with each D flip-flop corresponding to one of the n adders. Each D flip-flop can latch the level output of the carry-out output of its corresponding adder. Optionally, each D flip-flop can use the edge of a first clock signal as its latching signal. Each D flip-flop latches the level of the carry-out output of its corresponding adder at each rising edge of the first clock signal and holds it until the next rising edge refreshes it. This achieves the buffer unit latching the state of the carry chain.

[0100] When the level of the adder's carry output terminal is the third level, it indicates that the adder's carry output result is 0. When the level of the adder's carry output terminal is the fourth level, it indicates that the adder's carry output result is 1. Optionally, in some examples, a carry output result of 1 indicates that the adder has carried, and a carry output result of 0 indicates that the adder has not carried. In other examples, a carry output result of 1 indicates that the adder has not carried, and a carry output result of 0 indicates that the adder has carried. This application does not impose specific limitations on this. For the sake of illustration, the following description uses an adder carry output result of 1 indicating a carry and an adder carry output result of 0 indicating no carry as examples.

[0101] The processing unit in the time-to-digital converter can obtain the output results of the carry outputs of n adders from the buffer unit. These n adder carry output results also represent the carry output status of each stage of the adder. Based on the output results of the n adder carry outputs, the processing unit can determine the status of the adder that experienced a carry. In this embodiment, the output results of the adder carry outputs are simply referred to as the adder output results.

[0102] For example, the number of adders that generated a carry, and the number of adders that did not generate a carry. Another example is the number of stages of adders contained within the adders that generated a carry. Yet another example is the adder with the largest stage among the adders that generated a carry. Assuming n is 4, if the processing unit obtains an output of 0000 from the four adders, it indicates that none of the adders generated a carry. If the processing unit obtains an output of 1000 from the four adders, it indicates that the first-stage adder generated a carry. If the processing unit obtains an output of 1110 from the four adders, it indicates that the first-stage adder, the second-stage adder, and the third-stage adder generated carrys, with the third-stage adder having the largest stage among the adders that generated carrys.

[0103] In the time-to-digital converter provided in this application, the timing length of each adder is predetermined or pre-measured. The timing length of the adder is also the carry time of the adder. In this art, the carry time of the adder in the carry chain can be understood as the delay time (bin) of the delay unit in the delay chain formed by the carry chain. In some examples, the timing length of each adder can be the same. In other examples, the timing length of each adder can be different.

[0104] In the time-to-digital converter provided in this application, the sum of the timing lengths of each adder is also the timing length of the carry chain. The timing length of the carry chain in the fine time counting unit is greater than 2t, which means the sum of the timing lengths of each adder is greater than 2t. Figure 4c The figure shows the relationship between the timing length of each adder in the carry chain and the time period t of the first clock signal.

[0105] Figure 5 An exemplary embodiment of the time measurement method provided in this application is shown, which can be executed by the aforementioned processing unit. The method may include the following steps:

[0106] Step S501: Based on the first clock signal, monitor the output results of n adders.

[0107] Step S502: Determine the fine-time result of the input signal to be tested based on the output results of the n adders obtained twice.

[0108] The processing unit can detect the output results of n adders based on the first clock signal. For example, the processing unit can obtain the output results of the n adders cached in the buffer unit at the rising edge of the first clock signal to obtain the output status of each adder at the current rising edge. After the carry link receives the input signal to be tested, the processing unit can determine the fine-time result of the input signal to be tested by using the output status of the n adders obtained at two rising edges.

[0109] The processing unit can acquire the output results of n adders at the first rising edge of each clock signal. Based on the acquired output results of the n adders, the processing unit can determine the carry-generating behavior of any of the n adders. In some examples, the processing unit can compare the output results of the n adders with a preset initial result. If the output results of the n adders are the same as the initial result, it indicates that none of the n adders generated a carry at that rising edge. If the output results of the n adders are different from the initial result, it indicates that at least one of the n adders generated a carry at that rising edge.

[0110] Figure 6 An exemplary embodiment of the time measurement method provided in this application is shown, which can be executed by a processing unit, and the method may include the following steps:

[0111] Step S601: At the first rising edge of the first clock signal, obtain the output results of n adders.

[0112] Step S602: Compare the output result of the adder obtained at the first rising edge with the preset initial result. If yes, proceed to step S603; otherwise, proceed to step S604.

[0113] Step S603: Obtain the output results of n adders at the first rising edge after the first rising edge.

[0114] Assuming the first rising edge time is tx, and the next rising edge time after the first rising edge time is tx+t, the processing unit can obtain the output results of n adders at the next rising edge time after the first rising edge time, tx+t. The processing unit can take the next rising edge after the first rising edge time as the new first rising edge time and execute the operation in step S602.

[0115] Step S604: At the second rising edge, obtain the output results of n adders and determine the second adder with the largest number of stages among the adders that have carried at the second rising edge.

[0116] In this embodiment, the second rising edge time is the first rising edge time after the first rising edge time, that is, the next rising edge time after the first rising edge time. The processing unit can determine the carry situation of the n adders at the second rising edge time based on the output result obtained at the second rising edge time. The processing unit can determine the adder with the largest number of stages among the adders that have carried, denoted as the second adder.

[0117] Step S605: Among the adders that carry occurs at the first rising edge, is the adder with the largest level the first-level adder? If yes, proceed to step S606; otherwise, proceed to step S607.

[0118] Step S606: At the third rising edge, obtain the output results of n adders and determine the first adder with the largest number of levels among the adders that have carried at the third rising edge.

[0119] In this embodiment, if the processing unit determines that the output result of the adder obtained at the first rising edge is different from the preset initial result, the processing unit can determine the case of the adder that carried at the first rising edge based on the output result of the adder obtained at the first rising edge. The processing unit can then determine the timing for obtaining the output results of n adders based on the case of the adder that carried at the first rising edge.

[0120] If the adder that carries at the first rising edge is the first-stage adder, the processing unit can use the output results of n adders at the second and third rising edges to determine the fine-time result, without using the data when only the first-stage adder carries, thus avoiding the delay problem caused by the aforementioned ultra-wide bin case.

[0121] The second rising edge occurs at the first rising edge after the first rising edge, which is the next rising edge after the first rising edge. In other words, assuming the first rising edge is tx and the first rising edge after the first rising edge is tx+t, the processing unit obtains the output of n adders at this second rising edge.

[0122] The third rising edge occurs at the second rising edge after the first rising edge. In other words, assuming the first rising edge is tx, the second rising edge after the first rising edge is tx+2×t, and the processing unit obtains the output of n adders at this second rising edge.

[0123] The processing unit can determine the carry situation of the n adders at the third rising edge based on the output obtained at the third rising edge. The processing unit can identify the adder with the largest number of stages among the adders that have carried, and denote it as the first adder.

[0124] Step S607: Based on the output result obtained at the first rising edge, determine the first adder with the largest number of stages among the adders that have carried at the first rising edge.

[0125] If, among the adders that carry occurs at the first rising edge, the adder with the largest stage is not the first-stage adder, the processing unit can determine the fine-time result using the outputs of the n adders at the first and second rising edges. The processing unit can determine the carry situation of the n adders at the first rising edge based on the output obtained at the first rising edge. The processing unit can identify the adder with the largest stage among those that carry, and designate it as the first adder.

[0126] Step S608: Determine the fine-time result of the input signal to be measured based on the first adder and the second adder.

[0127] Optionally, in the time-to-digital converter provided in this application embodiment, each of the n adders has a pre-configured start time. The start time of the k-th stage adder can be denoted as T_k1, where k can be any integer from 1 to n. The start time of the first stage adder is configured with a first value, which can optionally be 0. The difference between the start time T_i1 of the i-th stage adder and the first value is the timing length of the first i-1 stages adder.

[0128] Optionally, in the time-to-digital converter provided in this application embodiment, each of the n adders has a pre-configured end time. The end time of the k-th stage adder can be denoted as T_k2, where k can be any integer from 1 to n. The start time of the first stage adder is configured with a first value, which can optionally be 0. The difference between the end time of the first stage adder and the first value is the timing length of the first stage adder. The difference between the end time T_i2 of the i-th stage adder and the first value is the timing length of the i-th stage adder.

[0129] Optionally, in the digital converter provided in this application embodiment, each of the n adders has a pre-configured start time and end time. The difference between the end time and the start time of the k-th stage adder is the timing length of the k-th stage adder. The start time of the first stage adder is configured with a first value, which can optionally be 0. The difference between the start time T_i1 of the i-th stage adder and the first value is the timing length of the first i-1 stages adder. The difference between the end time and the first value of the first stage adder is the timing length of the first stage adder. The difference between the end time T_i2 of the i-th stage adder and the first value is the timing length of the first i stages adder.

[0130] When the processing unit executes the operation in step S608, it adopts any one of the following methods. For ease of explanation, the first adder is denoted as the s-th stage adder, and the second adder is denoted as the q-th stage adder. Then, the start time of the first adder is T_s1, and the end time of the first adder is T_s2. The start time of the second adder is T_q1, and the end time of the second adder is T_q2.

[0131] In one possible implementation, Figure 7 An exemplary embodiment illustrates a time measurement method, which can be executed by a processing unit and may include the following steps:

[0132] Step S701: Obtain the start time T_s1 of the first adder and the start time T_q1 of the second adder.

[0133] Step S702: Determine whether the difference between the start time T_q1 of the second adder and the start time T_s1 of the first adder is less than t. If yes, proceed to step S703; otherwise, proceed to step S704.

[0134] Step S703: The difference between the start time T_s1 and t of the first adder is taken as the first candidate fine time result.

[0135] Step S704: The difference between the start time T_q1 and 2t of the second adder is taken as the first candidate fine time result.

[0136] Step S705: Based on the first candidate fine time result, determine the fine time result of the input signal to be measured.

[0137] The processing unit can determine the fine time result t2 of the input signal under test based on the first candidate fine time result. The fine time result t2 of the input signal under test is a value greater than or equal to the first candidate fine time result. The processing unit can use the sum of the previously determined coarse time result t1 and the determined fine time result t2 as the time measurement result of the input signal under test.

[0138] In some examples, if the largest adder among the adders that carry at the first rising edge is the first-stage adder, the processing unit can determine the second adder using the output results of the n adders at the second rising edge, and the first adder using the output results of the n adders at the third rising edge. Optionally, in this case, the processing unit can determine the first candidate fine-time result as the fine-time result of the input signal to be measured. For example, if the first candidate fine-time result is the difference T_s1-t between the start time T_s1 and t of the first adder, the processing unit determines the fine-time result t2 of the input signal to be measured as T_s1-t. The processing unit determines the time measurement result of the input signal to be measured as t1+T_s1-t. As another example, if the first candidate fine-time result is the difference T_q1-2t between the start time T_q1 and 2t of the second adder, the processing unit determines the fine-time result t2 of the input signal to be measured as T_q1-2t. The time measurement result of the input signal to be measured determined by the processing unit is t1+T_q1-2t.

[0139] Alternatively, in this scenario, the processing unit can determine the fine-time result of the input signal under test based on the first candidate time result, wherein the fine-time result of the input signal under test is greater than or equal to the first candidate time result. For example, if the first candidate fine-time result is the difference T_s1-t between the start time T_s1 and t of the first adder, the fine-time result t2 of the input signal under test determined by the processing unit can be greater than or equal to T_s1-t. As another example, if the first candidate fine-time result is the difference T_q1-2t between the start time T_q1 and 2t of the second adder, the fine-time result t2 of the input signal under test determined by the processing unit can be greater than or equal to...

[0140] In other examples, if the largest adder among the adders that carry at the first rising edge is not the first-stage adder, the processing unit can determine the second adder using the output results of the n adders at the second rising edge. And the first adder can be determined using the output results of the n adders at the first rising edge. Optionally, in this case, the processing unit can determine the fine-time result of the input signal under test as the sum of the first candidate fine-time result and one clock period t. For example, if the first candidate fine-time result is the difference T_s1-t between the start time T_s1 of the first adder and t, the processing unit determines the fine-time result t2 of the input signal under test as T_s1. The processing unit determines the time measurement result of the input signal under test as t1+T_s1. As another example, if the first candidate fine-time result is the difference T_q1-2t between the start time T_q1 of the second adder and 2t, the processing unit determines the fine-time result t2 of the input signal under test as T_q1-t. The time measurement result of the input signal to be measured determined by the processing unit is t1+T_q1-t.

[0141] Alternatively, in this scenario, the processing unit can determine the fine-time result of the input signal under test based on the sum s1 of the first candidate fine-time result and one clock cycle t, wherein the fine-time result of the input signal under test is greater than or equal to s1. For example, if the first candidate fine-time result is the difference T_s1-t between the start time T_s1 of the first adder and t, the fine-time result t2 of the input signal under test determined by the processing unit can be greater than or equal to T_s1. As another example, if the first candidate fine-time result is the difference T_q1-2t between the start time T_q1 of the second adder and 2t, the fine-time result t2 of the input signal under test determined by the processing unit can be greater than or equal to T_q1-t.

[0142] In one possible implementation, Figure 8 An exemplary embodiment illustrates a time measurement method, which can be executed by a processing unit and may include the following steps:

[0143] Step S801: Obtain the end time T_s2 of the first adder and the end time T_q2 of the second adder.

[0144] Step S802: Determine whether the difference between the end time T_q2 of the second adder and the end time T_s2 of the first adder is less than t. If yes, proceed to step S803; otherwise, proceed to step S804.

[0145] Step S803: The difference between the end time T_q2 and 2t of the second adder is taken as the second candidate fine time result.

[0146] Step S804: The difference between the end time T_s2 of the first adder and t is taken as the second candidate fine time result.

[0147] Step S805: Based on the second candidate fine time result, determine the fine time result of the input signal to be measured.

[0148] The processing unit can determine the fine time result t2 of the input signal under test based on the second candidate fine time result. The fine time result t2 of the input signal under test is a value that is less than or equal to the second candidate fine time result. The processing unit can use the sum of the previously determined coarse time result t1 and the determined fine time result t2 as the time measurement result of the input signal under test.

[0149] In some examples, if the largest adder among the adders that carry at the first rising edge is the first-stage adder, the processing unit can determine the second adder using the output results of the n adders at the second rising edge, and the first adder using the output results of the n adders at the third rising edge. Optionally, in this case, the processing unit can determine the second candidate fine-time result as the fine-time result of the input signal to be measured. For example, if the second candidate fine-time result is the difference T_s2-t between the end time T_s2 of the first adder and t, the processing unit determines the fine-time result t2 of the input signal to be measured as T_s2-t. The processing unit determines the time measurement result of the input signal to be measured as t1+T_q2-t. As another example, if the second candidate fine-time result is the difference T_q2-2t between the end time T_q2 of the second adder and 2t, the processing unit determines the fine-time result t2 of the input signal to be measured as T_q2-2t. The time measurement result of the input signal to be measured determined by the processing unit is t1+T_q2-2t.

[0150] Alternatively, in this scenario, the processing unit can determine the fine-time result of the input signal under test based on the second candidate fine-time result, wherein the fine-time result of the input signal under test is less than or equal to the second candidate fine-time result. For example, if the second candidate fine-time result is the difference T_s2-t between the end time T_s2 of the first adder and t, the fine-time result t2 of the input signal under test determined by the processing unit can be less than or equal to T_s2-t. As another example, if the second candidate fine-time result is the difference T_q2-2t between the end time T_q2 of the second adder and 2t, the fine-time result t2 of the input signal under test determined by the processing unit can be less than or equal to T_q2-2t.

[0151] In other examples, if the largest adder among the adders that carry at the first rising edge is not the first-stage adder, the processing unit can determine the second adder using the outputs of the n adders at the second rising edge. It can also determine the first adder using the outputs of the n adders at the first rising edge. Optionally, in this case, the processing unit can determine the fine-time result of the input signal under test as the sum of the second candidate fine-time result and one clock period t. For example, if the second candidate fine-time result is the difference T_s2-t between the end time T_s2 of the first adder and t, the processing unit determines the fine-time result t2 of the input signal under test as T_s2. The processing unit determines the time measurement result of the input signal under test as t1+T_q2. As another example, if the second candidate fine-time result is the difference T_q2-2t between the end time T_q2 of the second adder and 2t, the processing unit determines the fine-time result t2 of the input signal under test as T_q2-t. The time measurement result of the input signal to be measured determined by the processing unit is t1+T_q2-t.

[0152] Alternatively, in this scenario, the processing unit can determine the fine-time result of the input signal under test based on the second candidate fine-time result, wherein the fine-time result of the input signal under test is less than or equal to the second candidate fine-time result. For example, if the second candidate fine-time result is the difference T_s2-t between the end time T_s2 of the first adder and t, the fine-time result t2 of the input signal under test determined by the processing unit can be less than or equal to T_q2. As another example, if the second candidate fine-time result is the difference T_q2-2t between the end time T_q2 of the second adder and 2t, the fine-time result t2 of the input signal under test determined by the processing unit can be less than or equal to T_q2-t.

[0153] In one possible implementation, Figure 9 An exemplary embodiment illustrates a time measurement method, which can be executed by a processing unit and may include the following steps:

[0154] Step S901: Obtain the start time T_s1 of the first adder, the start time T_q1 of the second adder, the end time T_s2 of the first adder, and the end time T_q2 of the second adder.

[0155] Step S902: Determine whether the difference between the start time T_q1 of the second adder and the start time T_s1 of the first adder is less than t. If yes, proceed to step S903; otherwise, proceed to step S904.

[0156] Step S903: The difference between the start time T_s1 and t of the first adder is taken as the first candidate fine time result.

[0157] Step S904: The difference between the start time T_q1 and 2t of the second adder is taken as the first candidate fine time result.

[0158] Step S905: Determine whether the difference between the end time T_q2 of the second adder and the end time T_s2 of the first adder is less than t. If yes, proceed to step S906; otherwise, proceed to step S907.

[0159] Step S906: The difference between the end time T_q2 and 2t of the second adder is taken as the second candidate fine time result.

[0160] Step S907: The difference between the end time T_s2 of the first adder and t is taken as the second candidate fine time result.

[0161] Step S908: Based on the first candidate fine time result and the second candidate fine time result, determine the candidate set, wherein the minimum value in the candidate set is the first candidate result, and the maximum value in the candidate set is the second candidate result.

[0162] In this embodiment, the processing unit determines a first candidate fine-time result and a second candidate fine-time result, which can be used to determine a candidate set of fine-time results for the input signal under test, i.e., a value range. The values ​​in the candidate set are all greater than or equal to the first candidate result, and the values ​​in the candidate set are all less than or equal to the second candidate result.

[0163] Step S909: Determine whether the adder with the largest level among the adders that carry at the first rising edge is the first-level adder. If yes, proceed to step S910; otherwise, proceed to step S911.

[0164] Step S910: Determine one value from the candidate set as the fine-time result of the input signal to be measured.

[0165] The processing unit can use any value from the candidate set as the fine-time result of the input signal to be measured.

[0166] Step S911: The sum of a value in the candidate set and the time period t is determined as the fine-time result of the input signal to be measured.

[0167] The processing unit can sum any value in the candidate set with the time period t, and use the sum as the fine time result of the input signal to be measured.

[0168] Based on the same technical concept, this application also provides an electronic device. Figure 10 The diagram shows a schematic of an electronic device. The electronic device may include a transmitting module, a receiving module, and a time-to-digital converter provided in any of the foregoing embodiments.

[0169] The transmitting module is used to transmit optical signals;

[0170] The receiving module is used to receive the input signal to be tested, which is a light signal reflected by an obstacle.

[0171] A time-to-digital converter used to measure the time of flight of optical signals.

[0172] On the other hand, this application provides a computer-readable storage medium storing computer instructions that, when executed on a processor, cause the processor to perform the time measurement method provided in any of the foregoing embodiments.

[0173] On the other hand, embodiments of this application provide a computer program product, comprising a computer program that, when executed by a processor, implements the steps of the above-described time measurement method.

[0174] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0175] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0176] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0177] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0178] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A time-to-digital converter, characterized in that, include: Coarse time counting unit, fine time counting unit, buffer unit, and processing unit; The coarse time counting unit is used to receive a first clock signal and a test input signal, and to count from a reference time until the test input signal is received, according to one clock period t of the first clock signal as the counting clock, so as to obtain the coarse time result of the test input signal. The fine-time counting unit includes a carry chain; wherein the timing length of the carry chain is greater than 2t, the carry chain includes n adders, where n is a positive integer greater than 1, the n adders are cascaded, wherein the carry input terminal of the first-stage adder is used to receive the input signal to be measured; the carry input terminal of the i-th stage adder is coupled to the carry output terminal of the (i-1)-th stage adder, where i takes any integer from 2 to n; The buffer unit is coupled to the carry output terminal of each of the n adders, and is used to buffer the output results of the carry output terminals of the n adders; The processing unit is coupled to the cache unit and is used for: Based on the first clock signal, monitor the output results of the n adders; Based on the output results of the n adders obtained twice, the fine time result of the input signal under test is determined, wherein the coarse time result and the fine time result are used to determine the time measurement result of the input signal under test; Specifically, when the processing unit monitors the output results of the n adders based on the first clock signal, it is used for: At the first rising edge of the first clock signal, the output results of the n adders are obtained; If the output of the n adders obtained at the first rising edge is different from the preset initial result, and the adder with the largest level among the adders that carry at the first rising edge is not the first-level adder, then the output of the n adders is obtained at the second rising edge, wherein the second rising edge is the first rising edge after the first rising edge. If the output of the n adders obtained at the first rising edge is different from the preset initial result, and the adder with the largest level among the adders that carry at the first rising edge is the first-level adder, then the output of the n adders is obtained at the second rising edge and the third rising edge, where the third rising edge is the second rising edge after the first rising edge.

2. The time-to-digital converter as described in claim 1, characterized in that, The processing unit is also used for: If the adder with the largest number of stages among the adders that carry at the first rising edge is not the first-stage adder, the first adder with the largest number of stages among the adders that carry at the first rising edge is determined based on the output result obtained at the first rising edge. Alternatively, if the adder with the largest number of stages among the adders that carry at the first rising edge is the first-stage adder, the first adder with the largest number of stages among the adders that carry at the third rising edge is determined based on the output result obtained at the third rising edge. Based on the output obtained at the second rising edge, determine the second adder with the largest number of stages among the adders that have carried at the second rising edge. And based on the first adder and the second adder, the fine-time result of the input signal under test is determined.

3. The time-to-digital converter as described in claim 2, characterized in that, Each adder has a pre-configured start time; the start time of the first-stage adder is configured as a first value; the difference between the start time of the i-th-stage adder and the first value is the timing length of the first i-1 stages of adders; the processing unit is specifically used for: If the difference between the start time of the second adder and the start time of the first adder is less than t, the difference between the start time of the first adder and t is taken as the first candidate fine time result; If the difference between the start time of the second adder and the start time of the first adder is equal to or greater than t, the difference between the start time of the second adder and 2t is taken as the first candidate fine time result; Based on the first candidate fine time result, the fine time result of the input signal to be measured is determined.

4. The time-to-digital converter as described in claim 2 or 3, characterized in that, Each adder has a pre-configured end time; the start time of the first-stage adder is configured to a first value, and the difference between the end time of the first-stage adder and the first value is the timing length of the first-stage adder; the difference between the end time of the i-th-stage adder and the first value is the timing length of the i-th-stage adder. The processing unit is further configured to: If the difference between the end time of the second adder and the end time of the first adder is less than t, the difference between the end time of the second adder and 2t is taken as the second candidate fine time result; If the difference between the end time of the second adder and the end time of the first adder is equal to or greater than t, the difference between the end time of the second adder and t is taken as the second candidate fine time result; Based on the second candidate fine time result, the fine time result of the input signal to be measured is determined.

5. The time-to-digital converter as described in claim 4, characterized in that, The processing unit is specifically used for: Based on the candidate set, the fine-time result of the input signal to be tested is determined, wherein the minimum value in the candidate set is the first candidate fine-time result, and the maximum value in the candidate set is the second candidate fine-time result; If the adder with the largest number of stages among the adders that carry at the first rising edge is the first-stage adder, then any value in the candidate set is the fine-time result of the input signal to be measured. If the adder with the largest number of stages among the adders that carry at the first rising edge is the first-stage adder, then the sum of any value in the candidate set and t is the fine-time result of the input signal to be measured.

6. A time measurement method, characterized in that, Applied to any one of the time-to-digital converters as described in claims 1-5, the method comprises: The input signal to be tested is counted according to one clock period t of the first clock signal to obtain a coarse time result of the input signal to be tested. Based on the first clock signal, monitor the output results of the n adders; Based on the output results of the n adders obtained twice, the fine-time result of the input signal to be tested is determined; The monitoring of the output results of the n adders includes: At the first rising edge of the first clock signal, the output results of the n adders are obtained; If the output of the n adders obtained at the first rising edge is different from the preset initial result, and the adder with the largest level among the adders that carry at the first rising edge is not the first-level adder, then the output of the n adders is obtained at the second rising edge, wherein the second rising edge is the first rising edge after the first rising edge. If the output of the n adders obtained at the first rising edge is different from the preset initial result, and the adder with the largest level among the adders that carry at the first rising edge is the first-level adder, then the output of the n adders is obtained at the second rising edge and the third rising edge, where the third rising edge is the second rising edge after the first rising edge.

7. The method as described in claim 6, characterized in that, If the output results of the n adders obtained at the first rising edge are different from the preset initial results, the step of determining the fine-time result of the input signal under test based on the output results of the n adders obtained in the two steps includes: If the adder with the largest level among the adders that carry at the first rising edge is not the first-level adder, the first adder with the largest level among the adders that carry at the first rising edge is determined based on the output result obtained at the first rising edge; or, if the adder with the largest level among the adders that carry at the first rising edge is the first-level adder, the first adder with the largest level among the adders that carry at the third rising edge is determined based on the output result obtained at the third rising edge. Based on the output obtained at the second rising edge, determine the second adder with the largest number of stages among the adders that have carried at the second rising edge. And based on the first adder and the second adder, the fine-time result of the input signal under test is determined.

8. The method as described in claim 7, characterized in that, Each adder has a pre-configured start time; the start time of the first-stage adder is configured as a first value; the difference between the start time of the i-th-stage adder and the first value is the timing length of the first i-1 stages of adders; The step of determining the fine-time result of the input signal under test based on the first adder and the second adder includes: If the difference between the start time of the second adder and the start time of the first adder is less than t, the difference between the start time of the first adder and t is taken as the first candidate fine time result; If the difference between the start time of the second adder and the start time of the first adder is equal to or greater than t, the difference between the start time of the second adder and 2t is taken as the first candidate fine time result; Based on the first candidate fine time result, the fine time result of the input signal to be measured is determined.

9. The method as described in claim 7 or 8, characterized in that, Each adder has a pre-configured end time; the start time of the first-stage adder is configured to a first value, and the difference between the end time of the first-stage adder and the first value is the timing length of the first-stage adder; the difference between the end time of the i-th-stage adder and the first value is the timing length of the i-th-stage adder. The step of determining the fine-time result of the input signal under test based on the first adder and the second adder further includes: If the difference between the end time of the second adder and the end time of the first adder is less than t, the difference between the end time of the second adder and 2t is taken as the second candidate fine time result; If the difference between the end time of the second adder and the end time of the first adder is equal to or greater than t, the difference between the end time of the first adder and t is taken as the second candidate fine time result; Based on the second candidate fine time result, the fine time result of the input signal to be measured is determined.

10. The method as described in claim 9, characterized in that, The determination of the fine-time result of the input signal to be measured includes: Based on the candidate set, the fine-time result of the input signal to be tested is determined, wherein the minimum value in the candidate set is the first candidate fine-time result, and the maximum value in the candidate set is the second candidate fine-time result; If the adder with the largest number of stages among the adders that carry at the first rising edge is the first-stage adder, then any value in the candidate set is the fine-time result of the input signal to be measured. If the adder with the largest number of stages among the adders that carry at the first rising edge is the first-stage adder, then the sum of any value in the candidate set and t is the fine-time result of the input signal to be measured.

11. An electronic device, characterized in that, include: The transmitting module, the receiving module, and the time-to-digital converter as described in any one of claims 1-5; The transmitting module is used to transmit optical signals; The receiving module is used to receive the input signal to be tested, which is the light signal reflected by the obstacle; The time-to-digital converter is used to measure the time of flight of the optical signal.

12. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that, when executed on a processor, cause the processor to perform the method as described in any one of claims 6-10.

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