Cross-clock-domain time information correction method and distributed system thereof
By using a cross-clock domain time information correction method and adjusting the counters of master and child nodes, high-precision time information conversion is achieved in large-scale distributed systems, which simplifies system design and reduces costs. It is suitable for time calibration in asynchronous clock domains.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HUAZHONG NORMAL UNIV
- Filing Date
- 2023-12-27
- Publication Date
- 2026-06-23
AI Technical Summary
In large-scale distributed systems, existing technologies for time measurement in synchronous clock domains are costly and difficult to deploy, while time measurement in asynchronous clock domains has low accuracy and makes it difficult to achieve high-precision time information conversion.
By using a cross-clock domain time information correction method, the child node sends the clock and data to the master node. The master node configures a counter to sample and correct the data. The correction value of the clock counter is used to adjust the data, thereby realizing the conversion of timestamps in different clock domains, simplifying system design and improving time measurement accuracy.
It achieves high-precision time information conversion under different clock domains, reduces equipment costs and system complexity, improves the accuracy and stability of time measurement, and is suitable for time calibration under asynchronous clock domains.
Smart Images
Figure CN117792554B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of distributed technology, specifically relating to a cross-clock domain time information correction method and its distributed system. Background Technology
[0002] Time information generally refers to the specific moment an event occurs or the relationship between the moments of different events, such as time differences. For large distributed systems, it is sometimes necessary to accurately measure the precise occurrence time of events at different nodes. To achieve this, in addition to designing circuits for time measurement at each child node, the relationship between the clock references of each node also needs to be considered. Currently, typical distributed system time measurement techniques are usually based on synchronous clocks, with the master node distributing the clock reference to each child node. When the clocks of the entire system are from the same source and stable, the time information measured by each node can be converted to a unified clock domain. This synchronization has its advantages, but for large systems, whether based on independent clock distribution links or using clock distribution methods embedded in the data, complex system design is required for accurate clock distribution. This includes achieving high-precision clock distribution and adjustment, and designing clock recovery circuits at each child node to obtain the system clock from the master node. All existing methods are often expensive and difficult to deploy, while asynchronous clock time measurement schemes have relatively low accuracy. Summary of the Invention
[0003] The purpose of this invention is to address the shortcomings of the aforementioned background technology by providing a cross-clock domain time information correction method and its distributed system, which has a simple structure, saves equipment costs, is relatively easy to deploy, and has relatively high time measurement accuracy.
[0004] The technical solution adopted in this invention is: a method for correcting time information across clock domains, comprising the following steps:
[0005] The child node sends a digital signal carrying its own clock and data information to the master node, and then the master node recovers the child node's clock and data;
[0006] The master node is configured with a child node clock counter and a master node clock counter. The master node samples the other clock using either the child node clock or the master node clock. When it finds that the lag time between the two clocks reaches a single cycle of the faster clock, it adjusts the child node clock counter to keep the two clock counters consistent.
[0007] The timestamp of the child node's data in the master node's clock domain is obtained by converting the child node's clock counter and the master node's clock.
[0008] The above technical solution also includes the following steps: the master node counts the number of cycles P of the child node clock during the process from the two clock counters becoming consistent to the lag time between the two clocks reaching the single cycle of the faster clock, and generates a correction value for the child node clock counter based on the number of cycles P; in each cycle of the child node clock, the child node clock counter increases the correction value as the counting result of the child node clock counter under the premise of normal counting.
[0009] In the above technical solution, when the counters of the two clocks are the same, the correction value of the child node clock counter is 0;
[0010] When the clock frequency of the child node is greater than that of the master node, in each clock cycle of the child node, the correction value of the child node clock counter is increased by -1 / P compared to the previous clock cycle, until the counters of the two clocks are adjusted to be consistent, and this cycle continues.
[0011] When the clock frequency of the child node is lower than that of the master node, the correction value of the child node clock counter is increased by +1 / P in each clock cycle of the child node until the counters of the two clocks are adjusted to be consistent, and this cycle continues.
[0012] In the above technical solution, for the sampling result of any clock to another clock, when the lag time between the two clocks reaches a single cycle of the faster clock, a window that disables correction is added after the first transition edge of the sampling result.
[0013] In the above technical solution, an enable signal is generated when the lag time between the two clocks is found to reach a single cycle of the faster clock. This enable signal is used to adjust the counter of the child node clock.
[0014] In the above technical solution, when the frequency of the child node clock is greater than that of the master node clock, the master node clock is sampled using the child node clock: when the child node clock is on the rising edge, the master node clock is sampled, and the sampling result is generated based on the level state of the master node clock; when the sampling result is on the falling edge, the current cycle calculation of the child node clock counter remains unchanged.
[0015] In the above technical solution, when the child node clock frequency is less than the master node clock, the master node clock is used to sample the child node clock signal: when the master node clock is rising, the child node clock is sampled, and the sampling result is generated according to the level state of the child node clock; when the sampling result is falling, the current period count result of the child node clock counter is increased by one.
[0016] In the above technical solution, after the master node receives the digital signal from the child node, it first decodes it and recovers the clock and data, and then performs clock domain correction.
[0017] In the above technical solution, the width of the window is set according to the jitter of the two clocks and the difference in their frequencies.
[0018] The present invention also provides a distributed system for cross-clock domain time information correction, including a master node and several child nodes; the master node uses the system clock, and the child nodes use their own independent local clocks; the system executes the cross-clock domain time information correction method, so that the master node corrects the digital signals from each child node from the clock domain of the child nodes to the clock domain of the master node.
[0019] The beneficial effects of this invention are as follows: The cross-clock domain time information correction method proposed in this invention simplifies the clock link design of the entire system, especially for each sub-node. Each sub-node can directly use its local independent clock reference, and the clocks of each sub-node do not need to be synchronized with the clock of the master node, effectively saving the computational cost and construction cost of the sub-node system. Based on the time information and data stream transmitted from the sub-nodes, the master node uses the sub-node clock recovered from the data stream and the local system clock, combined with the correction method proposed in this invention, to convert the time information of sub-node events from the sub-node clock domain to the master node's system clock domain, ensuring that the sub-node data received by the master node has high time measurement accuracy.
[0020] Furthermore, by correcting the calibration result of the child node clock counter, the present invention further improves the calibration accuracy of the child node clock, ensuring that the child node data received by the master node has high time measurement accuracy.
[0021] Furthermore, the correction method proposed in this invention can dynamically reduce the instability of the period P caused by jitter, thereby further improving the accuracy of time measurement.
[0022] Furthermore, this invention adds a window to disable calibration after the first edge transition of the sampling result, effectively avoiding the problem of counter correction errors caused by clock jitter and improving the stability of calibration operations.
[0023] Furthermore, by setting an enable signal, the present invention can dynamically adjust the time of the child node clock counter each time, ensuring the accuracy of the calibration operation and improving the time measurement accuracy.
[0024] Furthermore, the sampling method adopted in this invention can maintain the consistency of counter values under different clock domains according to different scenarios, and the implementation method is relatively simple and consumes low resources.
[0025] Furthermore, before performing clock domain correction, the present invention performs transcoding to ensure the correctness of data transmission and the high quality of data transmission in the electrical link, thereby further reducing the risk of data errors.
[0026] Furthermore, by setting the window width based on information from two clocks, this invention can prevent system-wide failure due to excessive clock jitter. This improves time calibration accuracy and reduces the probability of erroneous operations. Attached Figure Description
[0027] Figure 1 This is a schematic diagram of the method flow of the present invention;
[0028] Figure 2 This is a schematic diagram of the system distribution in a specific embodiment;
[0029] Figure 3 A schematic diagram is generated based on the sampling results of a specific embodiment;
[0030] Figure 4 This is a schematic diagram of the counter calibration principle in a specific embodiment;
[0031] Figure 5 This is a schematic diagram of the enable signal in a specific embodiment. Detailed Implementation
[0032] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments to facilitate a clear understanding of the present invention, but these descriptions do not constitute a limitation on the present invention.
[0033] like Figure 1 As shown, the present invention provides a method for correcting time information across clock domains, comprising the following steps:
[0034] The child node sends a digital signal carrying its own clock and data information to the master node, which then recovers it.
[0035] The master node is configured with a child node clock counter and a master node clock counter. The master node samples the other clock using either the child node clock or the master node clock. When it finds that the lag time between the two clocks reaches a single cycle of the faster clock, it adjusts the child node clock counter to keep the two clock counters consistent.
[0036] The timestamp of the child node's data in the master node's clock domain is obtained by converting the child node's clock counter and the master node's clock.
[0037] The present invention also provides a distributed system for cross-clock domain time information correction, including a master node and several child nodes; the master node uses the system clock, and the child nodes use their own independent local clocks; the system executes the cross-clock domain time information correction method, so that the master node corrects the digital signals from each child node from the clock domain of the child nodes to the clock domain of the master node.
[0038] The method proposed in this invention is still applicable when there is a significant difference between the frequencies of the master node system clock and the child node local clock.
[0039] The principles of the present invention will be further explained below with reference to specific embodiments.
[0040] like Figure 2 As shown, this specific embodiment includes several child nodes, with the master node being an FPGA. Each child node interacts with the master node in the same way, and the master node performs a cross-clock domain time information correction method for each child node. Therefore, the invention is explained through the time information correction process of the master node for a specific child node.
[0041] Child nodes use their own independent local clocks f node It serves as a reference for time measurement and is applied to various local modules, such as the Time-to-Digital Converter (TDC). node It also serves as a reference clock for the uplink data link. The child node sends a clock signal (f) to the master node via a unidirectional fiber. node Digital signals containing data information. Both the child and master nodes use SFP+ modules to convert between optical and electrical signals.
[0042] The master node uses the system clock f sys Based on this, its transceiver recovers the data and clock f transmitted from the child node in the child node's clock domain. node Then, the Calibration module is used to utilize the recovered child node clock f. node With the local system clock f sys Correct the time information of the child nodes to the local f sys Under the system clock domain.
[0043] The master node is configured with a child node clock counter (CNT). fcal_int and master node clock counter CNT sys Running on the local system clock f sys The counter CNT sys The count value increments by one for each master node clock cycle. It runs on the recovery clock, which is also the child node clock f. node The child node clock counter CNT fcal_int Under normal circumstances, the clock cycle of each child node increases by one.
[0044] In this specific embodiment, the child node clock f node The frequency is slightly higher than the system clock f sys Therefore, the correction process in this specific embodiment is as follows:
[0045] Using child node clock f node For the system clock fsys Sampling is performed when the child node clock f node When a rising edge occurs, the master node clock f is... sys Perform sampling and generate sampling result DFF. out .like Figure 3 As shown, if the sampling time, i.e., when the child node clock has a rising edge, the system clock f sys If it is high, the sampling result DFF out A high level indicates a high level, and vice versa.
[0046] like Figure 4 As shown, when the sampling result DFF out When a falling edge appears, it indicates that the lag time between the two clocks has reached the duration of a single cycle of the child node clock. At this time, the child node counter CNT will be controlled. fcal_int The count value remains unchanged in the next cycle.
[0047] Specifically, the child node counter CNT fcal_int and system clock counter CNT sys The initial count value remains consistent, both being J. The child node counter CNT is updated just before the falling edge of the sampling result DFFout occurs. fcal_int The count value is K-1, and the system clock counter CNT is... sys The count value is K-2, and the difference between the count values of the two counters reaches 1 and their trailing edges are aligned. Therefore, in the next clock cycle, the system clock counter CNT... sys Normal counting, the count value becomes K-1, child node counter CNT fcal_int The count value remains consistent with the previous clock cycle, that is, it is still K-1.
[0048] This specific embodiment is based on clock sampling, and the sampling result DFF is used to... out The period difference and frequency difference between two asynchronous clocks can be measured, i.e., the sampling result is DFF. out The frequency; and by adjusting the value of the counter, the counter values of the two clock domains are kept less than 1.
[0049] In response to the above-mentioned correction method for child node counters, this specific embodiment further proposes a method for correcting the correction results:
[0050] The master node counts the number of cycles P of the child node clock during the process from the two clock counters becoming consistent until the lag time between the two clocks reaches a single cycle of the faster clock. Based on this number of cycles P, a correction value CNT for the child node clock counter is generated. fcal_frac In each cycle of the child node clock, the child node clock counter is incremented by a correction value as the correction result of the child node clock counter, provided that the counting is normal (i.e., CNT).fcal_int +CNT fcal_frac ).
[0051] When the counters of the two clocks are in sync, the correction value of the child node clock is 0; in each clock cycle of the child node, the correction value of the child node clock increases by -1 / P compared to the previous clock cycle, until the counters of the two clocks are adjusted to be in sync, and this cycle continues.
[0052] like Figure 4 As shown, for the child node clock f node The counter information J+2 below is corrected to f. sys In the clock domain, the value of its counter is J+2-2 / P.
[0053] This specific embodiment further corrects the decimal part of the time information of the child node clock. Ideally, the corrected accuracy will be close to the difference between the periods of the two clocks.
[0054] By multiplying the corrected and modified child node clock counter by the master node clock frequency, the relative time of the child node's digital signal from 0 in the master node clock domain is obtained. Then, the relative time is superimposed on the system time in the master node clock domain to obtain the final timestamp, thereby realizing the time information correction of the digital signal from the child node clock domain to the master node clock domain.
[0055] Since both clock edges actually have jitter, the actual sampling result DFF out Will as Figure 5 As shown, fluctuations exist near each ideal edge, i.e., brief, repeated transitions between low level 0 and high level 1. Therefore, in this specific embodiment, when performing correction, a window to disable correction is added after the first transition of each ideal edge, and correction is only applied to the sampled result DFF. out A Calibrate pulse is generated at the falling edge position, which triggers the child node clock counter CNT. fcal_int Perform a calibration to keep it in sync with the master node clock counter.
[0056] The window width can be configured online, depending on the clock jitter and the frequency difference between the two clocks. The standard for this width setting primarily depends on the sampling result DFF. out For the period, it is generally recommended to take 1 / 4 of the period as the window size.
[0057] In existing technologies, clock synchronization is required between the master node and multiple child node devices, which places more stringent demands on the design of the solution, is less flexible, and involves a large number of interconnecting cables between devices. This invention effectively solves the problem of time information recovery across clock domains, provides more design possibilities, and can be applied to systems that cannot perform time synchronization, simplifying the overall system structure.
[0058] Compared with the prior art, this specific embodiment effectively reduces the complexity of system design. For example, in traditional large-scale systems, clock distribution is often used to complete the clock synchronization of the entire system. Each subsystem requires at least two cables for sending digital signals from the slave node to the master node and for the master node to send clock signals from the slave node.
[0059] The method proposed in this invention can calibrate the clock signal of the child node to the master system when using an asynchronous clock, reducing the connection to each subsystem to a single cable, used only for transmitting digital signals from the child node to the master node. This results in significant improvements in equipment cost, system design complexity, and design speed.
[0060] It is worth noting that some large systems often require hundreds or even thousands of subsystems, and the cables are long and the cost is high. Applying this invention to large systems can save hundreds of millions or even tens of millions of dollars in costs.
[0061] The contents not described in detail in this specification are existing technologies known to those skilled in the art.
Claims
1. A method for correcting time information across clock domains, characterized in that: Includes the following steps: The child node sends a digital signal carrying its own clock and data information to the master node, and then the master node recovers the child node's clock and data; The master node is configured with a child node clock counter and a master node clock counter; The master node samples the other clock using either the child node clock or the master node clock. When it finds that the lag between the two clocks reaches a single cycle of the faster clock, it adjusts the child node clock counter to keep the two clock counters consistent. The timestamp of the child node's data in the master node's clock domain is obtained by converting the child node's clock counter and the master node's clock. The master node counts the number of cycles P of the child node clock during the process from the counters of the two clocks becoming consistent until the lag time between the two clocks reaches the single cycle of the faster clock, and generates a correction value for the child node clock counter based on the number of cycles P. In each cycle of the child node clock, the child node clock counter is incremented by a correction value as the counting result of the child node clock counter, on the premise of normal counting. When the counters of the two clocks are identical, the correction value of the child node clock counter is 0; When the clock frequency of the child node is greater than that of the master node, in each clock cycle of the child node, the correction value of the child node clock counter is increased by -1 / P compared to the previous clock cycle, until the counters of the two clocks are adjusted to be consistent, and this cycle continues. When the clock frequency of the child node is lower than that of the master node, the correction value of the child node clock counter is increased by +1 / P in each clock cycle of the child node until the counters of the two clocks are adjusted to be consistent, and this cycle continues.
2. The method according to claim 1, characterized in that: For any clock sampling result of another clock, when the lag time between the two clocks reaches a single cycle of the faster clock, a window that disables correction is added after the first transition edge of the sampling result.
3. The method according to claim 1, characterized in that: An enable signal is generated when the lag between the two clocks is found to reach a single cycle of the faster clock. This enable signal is used to adjust the counter of the child node clock.
4. The method according to claim 1, characterized in that: When the child node clock frequency is greater than the master node clock, the master node clock is sampled using the child node clock; when the child node clock is on the rising edge, the master node clock is sampled, and the sampling result is generated based on the level state of the master node clock. When a falling edge appears in the sampling result, the calculation of the child node clock counter for that cycle remains unchanged.
5. The method according to claim 1, characterized in that: When the child node clock frequency is lower than the master node clock, the master node clock is used to sample the child node clock signal; when the master node clock is at the rising edge, the child node clock is sampled, and the sampling result is generated according to the level state of the child node clock. When a falling edge appears in the sampling result, the current cycle count of the child node clock counter is incremented by one.
6. The method according to claim 1, characterized in that: After receiving the digital signal from the child node, the master node first decodes it, restores the clock and data, and then performs clock domain correction.
7. The method according to claim 2, characterized in that: The width of the window is set according to the jitter of the two clocks and the difference in their frequencies.
8. A distributed system for cross-clock domain time information correction, characterized in that: It includes a master node and several child nodes; the master node uses the system clock, and the child nodes use their own independent local clocks; the system executes the cross-clock domain time information correction method according to any one of claims 1-7, so that the master node corrects the digital signals from each child node from the clock domain of the child node to the clock domain of the master node.