Distributed control system clock signal detection switching method and system

Abstract

The application relates to a distributed control system clock signal detection switching method and system. A distributed control system using synchronous clock communication has the problems that secondary computers cannot independently select a working state and a fault state is not predicted. In the system, a primary computer is connected to a primary clock signal branching module, the primary clock signal branching module is branched to be connected to secondary computers and a clock signal switching module; the secondary computers and an internal clock signal generating module are connected to the clock signal switching module, and the clock signal switching module is connected to a secondary clock signal branching module; and the secondary clock signal branching module is branched to be connected to the secondary computers and tertiary computers. The method adopts external clock automatic detection and internal and external clock switching strategies, has higher control and starting flexibility, can select to start part of the secondary computers, lowers part of the control functions of the primary computers, realizes diversified control, saves operation time, and improves operation efficiency.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer control, in particular to a clock signal detection switching method and system for a distributed control system. BACKGROUND

[0002] A distributed control system (DCS) is generally divided into three layers: a process control layer (level 3), a production monitoring layer (level 2), and a centralized management layer (level 1). The process control layer at the bottom layer generally realizes data acquisition and control locally by dispersed field control stations, data acquisition stations, etc., and transmits the data to the production monitoring layer computer through a data communication network. The production monitoring layer centrally manages the data from the process control layer, such as various optimization calculations, statistical reports, fault diagnosis, display alarms, etc. With the development of computer technology, the DCS can be connected to higher-performance computer devices through a network to realize higher-level centralized management functions, such as scheduling, warehouse management, energy management, etc. The process control layer uses microprocessors to control each loop, and small and medium-sized industrial control computers or high-performance microprocessors are used to implement the control of the upper level. Information is exchanged between loops and between levels through high-speed data channels. In some cases, high-speed real-time communication between upper and lower computers requires a synchronous clock to ensure fast data transmission and reception. However, in some special cases, the production monitoring layer computer (level 2 computer) should have the ability to generate a clock signal and start with the internal clock, and can start and run independently. If there are more levels of systems, the computers at each level in between may have the need to start and work independently.

[0003] If the production monitoring layer computer (level 2 computer) does not have the ability to generate an internal clock and start with the internal clock, but only has the ability to start with an external clock, then each time the work is started, the centralized management layer computer (level 1 computer) needs to be turned on. However, in some cases, only the level 2 computer needs to be started to complete the related work, and the level 1 computer does not need to be turned on. In some specific cases, it is necessary to turn on the level 2 computer first, such as in the military field, where the level 2 computer is turned on first to save operation time and improve operation efficiency. SUMMARY

[0004] The purpose of the present application is to provide a clock signal detection switching method and system for a distributed control system, to solve the problem that the production monitoring layer computer (level 2 computer) cannot start and work independently in the current distributed control system using synchronous clock communication.

[0005] To achieve the above purpose, the technical solution adopted by the present application is as follows:

[0006] A distributed control system clock signal detection and switching system includes a primary computer, a secondary computer, and a tertiary computer. The system also includes a primary clock signal splitting module, a clock signal switching module, an internal clock signal generation module, and a secondary clock signal splitting module.

[0007] The primary computer is connected to the primary clock signal splitter module, and the primary clock signal splitter module is connected to the secondary computer and the clock signal switching module respectively.

[0008] The secondary computer and the internal clock signal generation module are both connected to the clock signal switching module, and the clock signal switching module is connected to the secondary clock signal splitter module;

[0009] The secondary clock signal splitter module connects to the secondary computer and the tertiary computer respectively.

[0010] Furthermore, the system also includes a clock signal conditioning module and a detection signal driving module, which are disposed between the primary clock signal splitter module and the secondary computer.

[0011] The primary clock signal splitter module is connected to the clock signal conditioning module, and then connected to the secondary computer through the detection signal driving module.

[0012] Furthermore, the system also includes a switching control signal driving module, which is disposed between the secondary computer and the clock signal switching module;

[0013] The secondary computer is connected to the switching control signal driving module, and then to the clock signal switching module.

[0014] On the other hand, a clock signal detection and switching method for a distributed control system is provided, the method comprising:

[0015] The Level 1 computer generates an external clock signal and maintains the signal output while the Level 1 computer is operating.

[0016] An internal clock signal generation module is set up in the secondary computer. The internal clock signal generation module generates an internal clock signal and maintains the signal output when the secondary computer is working.

[0017] In full-state mode, the secondary computer starts up using the internal clock signal and continuously detects the external clock signal; when the external clock signal is detected, it receives the external clock signal and uses the external clock to work while stopping the detection of the external clock signal. If there are three consecutive communication errors, the detection of the external clock signal is resumed; when the external clock signal is not detected, it receives the internal clock signal and uses the internal clock to work while maintaining the detection of the external clock signal.

[0018] In self-test mode, the secondary computer does not detect external clock signals; instead, it receives internal clock signals and uses the internal clock to operate.

[0019] Furthermore, the internal clock signal generation module is a clock generation circuit that is consistent with the external clock circuit of the primary computer, or a clock signal generation circuit that uses technical specifications consistent with the external clock signal of the primary computer.

[0020] Furthermore, the secondary computer continuously monitors external clock signals, including:

[0021] The external clock signal generated by the primary computer is sent to the clock signal conditioning module, and then sent to the secondary computer through the detection signal driving module.

[0022] Furthermore, when the secondary computer does not detect an external clock signal, it receives the internal clock signal and operates using the internal clock, including:

[0023] A primary clock signal splitter module is set up in the primary computer, and a clock signal switching module is set up in the secondary computer;

[0024] The external clock signal generated by the primary computer is sent to the primary clock signal splitter module. After being split by the primary clock signal splitter module, one output is sent to the clock signal conditioning module, and the other output is sent to the clock signal switching module.

[0025] The default state of the clock signal switching module is to receive the external clock signal generated by the primary computer and send it to the secondary and tertiary computers;

[0026] When the secondary computer does not detect an external clock signal, it sends a switching control signal to the clock signal switching module. The clock signal switching module then switches to receiving the internal clock signal generated by the internal clock signal generation module and uses the internal clock to operate.

[0027] Furthermore, when the secondary computer does not detect an external clock signal, it sends a switching control signal to the clock signal switching module, including:

[0028] A switching control signal drive module is set up in the secondary computer. The switching control signal issued by the secondary computer is amplified by the switching control signal drive module and then sent to the clock signal switching module.

[0029] Furthermore, the method also includes:

[0030] During the switchover, the secondary computer stops detecting the external clock signal, and all communication between the secondary and tertiary computers is temporarily interrupted, resuming after one communication cycle.

[0031] Furthermore, the method also includes:

[0032] A secondary clock signal splitting module is set up in the secondary computer. The clock signal switching module splits the received external clock signal or internal clock signal, sending one path to the secondary computer and the other path to the tertiary computer.

[0033] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0034] This method enables clock signal detection and switching, system state maintenance, and fault state prediction in distributed control systems. Compared to currently used distributed control systems, the secondary computer, using automatic external clock detection and internal / external clock switching, offers greater control and startup flexibility than distributed control systems without an internal clock. It allows for the selective startup of some secondary computers and their controlled subordinate computers, and the delegation of some control functions from the primary computer to the secondary computer. Under conditions of partial or full system startup, the secondary computer can replace the primary computer to perform some control functions. Users can select a more suitable startup scale, achieving more diverse control capabilities, saving operation time, and improving operational efficiency. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other embodiments can be obtained from these drawings without creative effort.

[0036] Figure 1 This is a principle block diagram of the method of the present invention;

[0037] Figure 2 This is a schematic diagram of the hardware circuit connection of the clock buffer;

[0038] Figure 3 This is a clock signal conditioning circuit diagram;

[0039] Figure 4 This is the frequency response diagram of an RC circuit;

[0040] Figure 5 This is the original time-domain signal diagram of the differential clock;

[0041] Figure 6 This is the spectrum of the Fast Fourier Transform of a 100MHz differential clock signal with a time of 0.02 seconds;

[0042] Figure 7 This is a time-domain signal diagram of a limited differential clock signal;

[0043] Figure 8This is the spectrum of the Fast Fourier Transform of a 0.02-second amplitude-limited differential clock signal;

[0044] Figure 9 This is a diagram of the output signal of the Multisim simulation conditioning module;

[0045] Figure 10 This is the circuit diagram of the detection signal drive module;

[0046] Figure 11 This is a diagram of the output signals of the Multisim simulation detection signal drive module;

[0047] Figure 12 This is the circuit diagram of the control signal drive module;

[0048] Figure 13 This is a circuit diagram of a clock signal switching module using a DC contactor;

[0049] Figure 14 This is a circuit diagram of a clock signal switching module using solid-state relays;

[0050] Figure 15 This is a circuit diagram of a clock signal switching module that uses a magnetic latching relay;

[0051] Figure 16 This is the circuit diagram for a single-pin magnetic latching relay. Detailed Implementation

[0052] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of the invention.

[0053] It should be noted that similar reference numerals and letters indicate similar items; therefore, once an item is defined in one embodiment, it does not need to be further defined and explained in subsequent embodiments. Furthermore, the terms "comprising" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0054] It should also be noted that although the order of steps is mentioned in the method description, in some cases, steps may be performed in a different order than that described here, and this should not be interpreted as a restriction on the order of steps.

[0055] Common distributed control systems include a primary computer, a secondary computer, and a tertiary computer. After the primary computer starts up, it sends an external clock signal to the secondary and tertiary computers to achieve synchronization. This method leads to excessive system dependence on the primary computer, as the secondary computer lacks independent startup capability, making it unsuitable and unstable in certain situations. This invention provides a clock signal detection and switching system for distributed control systems, which upgrades the existing primary, secondary, and tertiary computer system architecture and effectively overcomes the aforementioned problems.

[0056] like Figure 1 The system further includes a primary clock signal splitting module, a clock signal switching module, an internal clock signal generation module, and a secondary clock signal splitting module. The primary computer is connected to the primary clock signal splitting module, which in turn connects to the secondary computer and the clock signal switching module. Both the secondary computer and the internal clock signal generation module are connected to the clock signal switching module, which in turn connects to the secondary clock signal splitting module. The secondary clock signal splitting module connects to the secondary computer and the tertiary computer.

[0057] The system also includes a clock signal conditioning module and a detection signal driving module, which are located between the primary clock signal splitter module and the secondary computer. The primary clock signal splitter module is connected to the clock signal conditioning module, and then connected to the secondary computer through the detection signal driving module.

[0058] The system also includes a switching control signal drive module, which is located between the secondary computer and the clock signal switching module; the secondary computer is connected to the switching control signal drive module, and then to the clock signal switching module.

[0059] Based on the above system structure, the present invention provides a clock signal detection and switching method for a distributed control system, the method comprising:

[0060] S1: The primary computer generates an external clock signal and maintains the signal output while the primary computer is operating.

[0061] S2: An internal clock signal generation module is set in the secondary computer. The internal clock signal generation module generates an internal clock signal and maintains the signal output when the secondary computer is working.

[0062] The internal clock signal generation module is a clock generation circuit that is consistent with the external clock circuit of the primary computer, or uses a clock signal generation circuit with specifications consistent with the external clock signal of the primary computer. The internal clock signal generation module ensures that the secondary computer still has a clock signal available when there is no external clock signal input; that is, an internal clock signal. When the secondary computer starts up, it synchronously supplies power to the internal clock signal generation module, which generates the internal clock signal and maintains the signal output while the secondary computer is operating.

[0063] S3: The system operates in two modes:

[0064] (1) In full-state mode, the secondary computer starts up with the internal clock signal and continuously detects the external clock signal; when the external clock signal is detected, it receives the external clock signal and uses the external clock to work and stops detecting the external clock signal. If communication fails for 3 consecutive cycles, it resumes detecting the external clock signal and takes corresponding actions based on the detection results; when the external clock signal is not detected, it receives the internal clock signal and uses the internal clock to work while maintaining the detection of the external clock signal.

[0065] S311: The process by which the secondary computer continuously detects the external clock signal is as follows:

[0066] The external clock signal generated by the primary computer is sent to the clock signal conditioning module, and then sent to the secondary computer through the detection signal driving module.

[0067] When an external clock signal is detected, the external clock signal is received and used to operate, and the detection of the external clock signal is stopped. If communication fails for 3 consecutive clock cycles, the detection of the external clock signal is resumed.

[0068] If the detection capability of the secondary computer does not match the clock signal frequency, or if the secondary computer lacks the ability to detect clock signals, a signal processing circuit needs to be designed to convert the clock signal into a DC signal before sending it to the processor for detection. This method adopts the latter approach, designing a rectification and conditioning circuit—a clock signal conditioning module. After rectification and conditioning, the external clock signal is ensured to be perfectly matched with the secondary computer's input requirements in terms of frequency, effective voltage, noise figure, and load capacity. Through hardware means, the square wave signal is conditioned into a conditioned signal containing a large-amplitude DC component. If the secondary computer has the ability to directly detect clock signals or has an internal module for processing and detecting clock signals, this step can be omitted, and the external clock signal can be detected directly.

[0069] Considering the limited power of the clock signal itself, which attenuates after passing through the clock signal conditioning module, the driving capability of the conditioned signal is insufficient. Furthermore, the conditioned signal still contains a significant amount of AC components; sending it directly to the secondary computer without processing can easily introduce noise into the secondary computer. Therefore, an optocoupler module—a detection signal driving module—is used to isolate noise and further improve the driving capability of the detection signal.

[0070] After being conditioned and driven, the external clock signal is sent to the detection pin of the secondary computer. The secondary computer software and supporting hardware judge the detection signal. If the secondary computer determines that there is no external clock signal, it outputs control state 1 (pseudo-full state mode) through the output control pin. If the secondary computer determines that there is an external clock signal, it outputs control state 2 (true full state mode). This step is mainly implemented by software, and the specific code should be matched with the input signal, processor specifications, and supporting hardware circuitry. The specific process is as follows: The secondary computer starts up and runs the main program. The detection software module continuously sends interrupt requests to the secondary computer until the secondary computer responds to the interrupt, retrieves the detection instructions, and executes them. According to the instruction code requirements, the secondary computer uses the specified detection input pins to sample the external clock signal or the processed conditioning drive signal and records the sampling results. The secondary computer reads the sampling results. If the sampling result is greater than the specified value, it is considered that there is an external clock signal input. At this time, the processor controls the output pin to output a low-level control signal, i.e., output control state 2 (true full state mode). If the sampling result is less than the specified value, it is considered that there is no external clock signal input. At this time, the processor controls the output pin to output a high-level control signal, i.e., output control state 1 (pseudo full state mode).

[0071] S312: The process by which the Level 2 computer receives the internal clock signal and uses the internal clock when it does not detect an external clock signal is as follows:

[0072] S3121: A primary clock signal splitter module is set up in the primary computer, and a clock signal switching module is set up in the secondary computer.

[0073] S3122: The external clock signal generated by the primary computer is sent to the primary clock signal splitter module. After being split by the primary clock signal splitter module, one output is sent to the clock signal conditioning module and enters the detection process (used for both operation and detection). The other output is sent to the clock signal switching module.

[0074] The input external clock signal is split. Different splitting methods can be used depending on the clock signal frequency, the splitting method used by the upstream computer, and the clock signal's driving capability. If the clock signal frequency is low, or if the preceding stage already uses a clock buffer with sufficient driving capability, a direct parallel splitting method is used. If the direct splitting method in the preceding stage results in insufficient clock signal driving capability and an irregular waveform, even if the clock signal frequency is low enough, a clock buffer should be used here to improve the clock signal driving capability and correct the waveform. If the clock signal frequency is high, or if the conditioning circuit has a significant impact on the clock signal after parallel splitting, a clock signal buffer is used for clock signal splitting. This example uses a clock signal buffer to split the clock signal.

[0075] S3123: The default state of the clock signal switching module is to receive the external clock signal generated by the primary computer and send it to the secondary and tertiary computers.

[0076] In the default state, i.e., when the power is off or when there is no need to switch to the internal clock, the clock signal switching module maintains a reliable connection with the external clock signal. Under this condition, the optocoupler does not work and the light-emitting diode does not emit light.

[0077] S3124: When the secondary computer does not detect an external clock signal, it sends a switching control signal to the clock signal switching module. The clock signal switching module switches to receiving the internal clock signal generated by the internal clock signal generation module according to the switching control signal and uses the internal clock to work.

[0078] When the secondary computer does not detect an external clock signal, the process of sending a switching control signal to the clock signal switching module is as follows:

[0079] A switching control signal drive module is set up in the secondary computer. The switching control signal issued by the secondary computer is amplified by the switching control signal drive module and then sent to the clock signal switching module.

[0080] During the switchover, the secondary computer stops detecting the external clock signal, and all communication between the secondary and tertiary computers is temporarily interrupted, resuming after one communication cycle.

[0081] If this method is used in applications requiring high timeliness and communication accuracy, a drive amplification circuit—a switching control signal drive module—is needed to drive and amplify the switching control signal output from the secondary computer, ensuring that the switching control signal is effectively and reliably sent to the clock signal switching module. This method still uses an optocoupler module to drive and amplify the output switching control signal, improving the stability and load-carrying capacity of the switching control signal, and thus enhancing system reliability.

[0082] The clock signal switching module executes switching instructions based on the input switching control signal. When the input is a low-level control signal, the switching circuit—the clock signal switching module—maintains the connection between the secondary computer's clock signal pin and the external clock signal circuit. When the input is a high-level control signal, the switching circuit operates, disconnecting from the external clock circuit and connecting to the internal clock signal circuit, thus achieving the switching between the internal and external clock signals. Specifically, the secondary computer sends the switching control signal to the positive pin of the optocoupler input, while the negative pin of the optocoupler input is grounded. If there is no external clock signal and the system is in control state 1 (pseudo-full-state mode), the secondary computer sends a high-level signal, activating the LED and turning on the phototransistor. If there is an external clock signal, the processor sends a low-level signal, the LED does not activate, and the phototransistor does not conduct.

[0083] (1) The positive terminal of the output of the optocoupler is connected to the driving power supply, and the negative terminal is grounded through a conditioning and voltage regulation circuit composed of a parallel resistor and a Schottky diode. The phototransistor controls the level of the output signal according to the brightness of the diode to realize the driving of the control signal.

[0084] (2) In self-test mode, the secondary computer does not detect the external clock signal, and the secondary computer receives the internal clock signal and uses the internal clock to work.

[0085] S4: A secondary clock signal splitting module is set up in the secondary computer. The clock signal switching module splits the received external clock signal or internal clock signal, sending one path to the secondary computer and the other path to the tertiary computer.

[0086] When this method is started, the appropriate mode can be selected according to the requirements. In civilian applications, one mode is usually sufficient to meet the actual needs, while military applications often require the design of two or more modes. The default startup mode is full-state mode using an external clock. When the internal clock is needed in full-state mode, the system switches to the internal clock. Alternatively, a self-test mode can be selected directly, which defaults to using the internal clock.

[0087] In full-state mode, either an internal clock or an external clock can be used. A status bit needs to be added during communication. When using the internal clock, the external clock signal is disabled, i.e., "pseudo-full-state mode"; when using the external clock, it is enabled, i.e., "pseudo-full-state mode". When an external clock is available, it is used first. The computer boots up using the internal clock and defaults to full-state mode, but can be manually intervened to enter self-test mode. Within logical constraints, adjustments can be made as needed.

[0088] When the secondary computer operates in "pseudo-full-state mode," it detects the external clock signal during specific communication cycles to ensure that the external clock signal is detected as soon as possible. If the external clock signal is not detected, the internal clock is used. If the secondary computer selects self-test mode under manual intervention, the system does not detect the external clock signal at all, and the secondary computer uses the internal clock.

[0089] When the secondary computer detects an external clock signal while operating in "pseudo-full-state mode", it immediately switches to external clock signal operation, interrupts the detection of external clock, and maintains the operation of external clock.

[0090] Based on the control strategy of this method, when the secondary computer operates in full-state mode and the external clock is valid, if the primary computer experiences a communication failure or system failure that prevents the external clock signal from being sent or causes an interruption in the clock signal transmission line, the secondary computer will experience a communication error and be unable to transmit data to the upper and lower levels. In this case, it will immediately send a switching control signal to switch to the internal clock and monitor the communication status. If the communication is normal, it will indicate an external clock failure; if it is abnormal, it will indicate a communication failure. Furthermore, the secondary computer can start independently without relying on the primary computer's startup, automatically entering full-state mode, reading and executing the external clock signal detection command. If the external clock signal is input normally and the system detection is valid (i.e., "true full-state mode"), the status bit in the communication data will be set to "1" (assuming the external clock signal is valid as "1"), and status data and control commands will be transmitted normally to the upper and lower level computers. If the external clock signal is not input (i.e., "pseudo-full-state mode"), the status bit in the communication data will be set to "0," and status data and control commands will only be transmitted to the lower level computer.

[0091] This method enables the conditioning, driving, and detection of external clock signals, and outputs the corresponding mode control state based on the detection results, activating the corresponding clock signal circuit. This allows level 2 and level 3 computers to prioritize the use of external clock signals when they are available, and select internal clock signals when they are unavailable. Furthermore, in full-state operation mode, once an external clock signal is input, the internal signal switching circuit is immediately controlled to activate the external clock signal circuit, enabling the system to operate in external clock mode. This provides greater control flexibility and startup flexibility.

[0092] Example:

[0093] The above method and system will be further described in detail below through specific embodiments:

[0094] Taking a differential clock with a clock frequency of 100MHz as an example, the clock signal conditioning module conditions the input external clock signal from a high-frequency square wave signal into a DC signal containing ripple signal, and then sends the conditioning signal to the detection signal driving module. The detection signal driving module eliminates the ripple component, retains the DC component, and improves the signal driving capability. The detection signal driving module sends the driving signal to the processor detection pin, and then the processor detection control software samples and judges the signal.

[0095] If the processor's sampling result is high, it determines that there is an external clock signal input, and the control switching terminal outputs "0" (low level). If the processor's sampling result is low, it determines that there is no external clock signal input, and the control switching terminal outputs "1" (high level). The processor's switching control pin sends the control signal to the control signal drive module. When the switching control pin outputs "0", i.e., sends a low level, the control signal drive module outputs approximately 0V low level. When the switching control pin outputs "1", i.e., sends a high level, the control signal drive module also outputs a matching high level. The control signal drive module sends the control drive signal to the clock signal switching module. When the output of the control signal drive module is low, the clock signal switching module does not work, i.e., it keeps the switch contact unchanged, making the switch contact with the external clock signal contact. At this time, the processor uses the external clock signal to work. When the output of the control signal drive module is high, the clock signal switching module works, i.e., it switches the switch contact, making the switch contact contact with the internal clock signal contact. At this time, the processor uses the internal clock signal to work.

[0096] See Figure 2 This example uses the Si53156 clock signal buffer as the clock signal splitter module. Detailed technical specifications of the Si53156 clock signal buffer can be found in its technical datasheet. This example assumes there are three downstream computers using differential clock signals; therefore, a buffer with a 1-to-6 differential clock signal splitter is required. It receives the differential external clock signal from the upstream computer and outputs six differential clock signals. Each of the three downstream computers uses two signals: one for operation and one for detection. The names, types, and technical descriptions of the various pins of the Si53156 clock signal buffer are given below.

[0097] Table 1. Pin Definitions of Si53156 Clock Signal Buffer

[0098]

[0099]

[0100] See Figure 3In this example, the clock signal conditioning module consists of a Schottky diode with good high-frequency characteristics, a general-purpose resistor with a resistance of 4.99Ω, and a general-purpose capacitor with a capacitance of 2.7nF. Taking a differential signal as an example, from an electrical engineering and electronic perspective, because the diode has unidirectional conduction characteristics within a specific voltage range, the square wave signal, after passing through the diode, only retains the portion greater than 0.75V. When fed into the network composed of the resistor and capacitor, due to the voltage across the capacitor... Therefore, when the voltage amplitude of the input signal changes, the capacitor, as an energy storage element, can play a role in voltage stabilization. After the first few pulses fully charge the capacitor plates, the voltage of the capacitor tends to stabilize, especially under the condition of no load, the voltage signal across the capacitor contains a low AC component voltage amplitude.

[0101] The resistor here serves as a current limiter. Adjusting the resistor value adjusts the current, the capacitor charging time, and the system output time. Note that the resistor should not be too large or too small. If it's too large, the loop current is too small, resulting in a long charging time and a prolonged response time; if it's too small, it won't provide protection. Under the operating conditions of this example, a standard resistor of 1Ω-5Ω is recommended; in this example, 4.99Ω is used.

[0102] The diode acts as a limiter, retaining only the positive half-cycle greater than the diode's voltage drop after passing through it. Without the diode, the capacitor would function as a closed circuit under AC signal conditions, resulting in a low-amplitude AC signal output from its terminals. We chose a high-frequency Schottky diode due to its superior high-frequency characteristics, enabling it to operate normally even with high clock signal frequencies. Simulation in Multisim confirmed that the ZPD8.2 diode meets the requirements and effectively limits the voltage. The key parameters of the ZPD8.2 diode are given below.

[0103] Table 2 Key parameters of ZPD8.2 diode

[0104] Name Description Value Unit Remark CJO Zero-bias junction capacitance 0.999e-12 F VJ Junction potential 0.75 V IS Saturation current 2.5245e-16 A RS Parasitic resistance 0.5164 Ω TT Switching time 5e-9 sec BV Reverse breakdown voltage 8.329 V

[0105] The capacitor acts as a rectifier here, using its voltage regulation function to rectify the near-high-frequency half-square wave signal into a DC signal containing AC signals. When the signal frequency is high, the size of the capacitor must be strictly controlled. If the capacitor is too large, it will take a long time to charge to saturation, requiring more cycles to stabilize the output signal and increasing the system's response time. However, if the capacitor is too small, its charge storage capacity is limited, resulting in weak load-carrying capacity. Simulation results under a 100MHz clock condition suggest using a standard 1nF-5nF capacitor to ensure sufficient response time and load-carrying capacity.

[0106] From a signal and system perspective, the RC circuit connected to the diode is actually a simple RC low-pass filter. Let v c(t) represents the output across the capacitor, v s (t) represents the system input. Based on the capacitor voltage-current relationship, we have:

[0107]

[0108] Assuming the system is initially relaxed, then when the input voltage is v s (t)=e jω The output will definitely be v. c (t)=H(jω)e jω Where H(jω) is the frequency response of the system, substituting it into the above equation, we get: In this example, we take C = 2.7 × 10 - 9 Given F,R = 4.99Ω, the system's amplitude-frequency response is shown in [reference needed]. Figure 4 .

[0109] When ω = 0, |H(jω)| = 1; when ω is sufficiently large, |H(jω)| << 1, indicating that the system is a non-ideal low-pass filter. The original clock signal is shown below. Figure 5 This is a square wave signal containing both positive and negative half-cycles. See the half-wave clock signal for details. Figure 6 For a square wave signal containing a positive half-cycle, the Fast Fourier Transform (FFT) result for a duration of 0.02 s is shown in [reference needed]. Figure 8 As can be seen, the frequency domain of the 0.02s half-wave square wave clock signal includes a DC component with ω=0 and amplitude of 1. Therefore, after passing through the RC circuit, the larger amplitude DC component will be retained, while the lower frequency sinusoidal AC component will be passed through, attenuating the higher frequency sinusoidal AC component. Thus, the Schottky diode plays a crucial role here; without diode limiting, the system would inevitably fail to output. Furthermore, using a 0.02s continuous clock signal here already represents 2×10 of the clock cycle. 6 For high-frequency signals, the duration is long enough. The transformed spectrum is now discrete, further indicating that the duration is sufficient. Therefore, the analysis results have a certain degree of accuracy and reference value. See also... Figure 9 The Multisim simulation output shows that at C = 2.7 × 10⁻⁶ -9 With F,R = 4.99Ω, the stable output time of the differential clock signal network with an input of 100MHz is about 70ns (1 large grid on the horizontal axis in the figure is 100ns), the output voltage is about 1.2V (1 large grid on the vertical axis in the figure is 2V), and the output signal contains obvious ripple.

[0110] See Figure 10The detection signal driving module, in this example, consists of a 1.02Ω current-limiting protection resistor, an optocoupler, a 10kΩ voltage divider resistor, and a +5V power supply. The current-limiting resistor should be of appropriate size; simulation analysis suggests using a common resistor between 1Ω and 100Ω. In this example, R = 1.02Ω. The optocoupler has few requirements; in this example, a PS2081-4 is used. The voltage divider resistor clamps the output voltage and must be sufficiently large; simulation analysis shows its size is typically between 5kΩ and 20kΩ. See also... Figure 11 This is used to simulate the voltage output of the detection signal drive module in Multisim. At this point, the system has completed the conversion from clock signal to detection drive signal.

[0111] See Figure 12 The control signal driving module has the same composition and working principle as the detection signal driving module.

[0112] The drive control signal is sent to the clock signal switching module, which then executes the switching command according to the control signal status. Three types of clock signal switching modules are given below.

[0113] See Figure 13 This method uses a dual-input, single-output 6-wire DC contactor as the actuator. The module consists of a protective resistor and an integrated DC contactor. When the processor detects an external clock signal, the processor control pin sends a low level. When the contactor control signal input is 0V, the contactor winding does not work, and the contact switch remains in contact with the external clock input terminal. At this time, the output signal is the external clock signal. When the processor detects no external clock signal, the processor control pin sends a high level, the contactor control signal input is the rated operating voltage, the contactor winding is energized, and the contactor switch switches the contact contacts, maintaining contact with the internal clock signal input terminal. At this time, the output signal is the internal clock signal.

[0114] See Figure 14 This method uses solid-state relays as actuators. The module consists of a protective resistor, two normally open solid-state relays, and two normally closed solid-state relays. The normally closed relays are connected to the external clock signal, and the normally open relays are connected to the internal clock signal. The control terminal is connected to the input signal. Its control method is basically the same as the contactor mode. When the processor detects an external clock signal, the processor control pin sends a low level, the module control signal input is 0V, all four solid-state relays are not working, the normally closed relays remain closed, and the normally open relays remain open. At this time, the module sends out the external clock signal. When the processor detects an external clock signal, the processor control pin sends a high level, the module control signal input is the rated operating voltage of the relays, all four solid-state relays work, the normally closed relays switch to open circuit, and the normally open relays switch to closed circuit. At this time, the module sends out the internal clock signal.

[0115] See Figure 15 This method uses magnetic latching relays as the actuators. The module consists of a protective resistor and four magnetic latching relays. Since the operation of magnetic latching relays differs slightly from that of relays and contactors, this method requires pulse signal control and two independent control lines: one to activate the internal clock and the other to activate the external clock. When the processor starts, it first sends an external clock pulse control signal, at which point the module connects to the external clock signal transmission line. If an external clock signal is present in the transmission line, the processor stops processing and does not send any pulse control signal; the clock signal switching module remains connected to the external clock signal, and the system uses the external clock signal. If the processor detects no external clock signal, it sends a switching pulse control signal through the internal clock control pin. At this point, the relay connected to the external clock signal disconnects, and the relay connected to the internal clock signal connects, the module outputs the internal clock signal, and the system operates using the internal clock signal. Thus, the system completes the detection of the clock signal and the switching between the internal and external clocks.

[0116] If the system wants to implement external clock signal detection and switching through upgrades, but lacks sufficient detection and control pins, a separate processor can be used to accomplish this task. This method, like other methods, cannot arbitrarily switch under continuous external clock signal conditions; it can only guarantee that the external clock signal is used first when available, and the internal clock is used when no external clock is available, sending out an "internal clock status." It switches to the internal clock when an external clock signal is input, and sends a fault signal when neither is available. The detection and switching process is basically the same as with the processor-based approach; simply send the detection drive signal to the separate processor, and the switching control signal is provided by the separate processor. The specific principle block diagram is not listed here; refer to the principle block diagram using the same processor. This method allows for system upgrades by adding external devices without modifying the original system, demonstrating a certain degree of feasibility.

[0117] The main program design for clock signal detection and switching is given below.

[0118] After each processor starts up, the calling program sends an interrupt request to the processor. Upon response, the processor samples the detection input pin twice and reads the sampling result. If the result is high, the control output pin is set low, the external clock is enabled, the context is restored, and the interrupt ends. If there is no high level, the control output pin is set high, the external clock is disabled, the context is restored, and the interrupt ends. In "pseudo-full-state mode," an interrupt request can be sent to the processor at 50 communication cycles (adjustable as needed). If the interrupt is not responded to, another interrupt request is sent at 10 communication cycles (adjustable as needed) until a response is received. After the processor responds, it samples the detection input pin twice and reads the sampling result. If the result is high, the control output pin is set low, the external clock is enabled, the context is restored, and the interrupt ends. If there is no high level, the control output pin is set high, the external clock remains disabled, the context is restored, and the interrupt ends. The detection steps are then repeated until an external clock signal is detected. If no external clock signal is needed, no detection is performed.

[0119] If communication fails for three consecutive clock cycles while the external clock is active, an interrupt request is immediately issued. After the processor responds, it samples the detection input pin twice and reads the sampling results. If the result is high, the communication system is considered abnormal, a communication abnormality message is sent, the context is restored, and the interrupt ends. If there is no high level, the control output pin is set to high, and the communication status is checked. If the communication is normal, an external clock invalidity status message is sent, the context is restored, and the interrupt ends. If the communication is abnormal, a communication fault message is sent, the context is restored, and the interrupt ends.

[0120] If communication fails for three consecutive clock cycles while the external clock is invalid, an interrupt request is immediately issued. After the processor responds, it samples the detection input pin twice and reads the sampling results. If the result is high, the control output pin is set low to enable the external clock and the communication status is checked. If the communication is normal, an internal clock fault indication is sent, the context is restored, and the interrupt ends. If the communication is abnormal, a communication fault indication is sent, the context is restored, and the interrupt ends. If there is no high level, a communication fault or internal clock fault indication is sent, the context is restored, and the interrupt ends.

[0121] The control process using magnetic latching relays is basically the same as the above process and will not be listed separately. The interrupt end status is described below: Interrupt end 1 means the external clock is valid and communication is normal; Interrupt end 1 means the external clock is invalid and communication is normal; Interrupt end 3 means communication failure; Interrupt end 4 means the external clock is invalid and communication is faulty or the internal clock signal is faulty; Interrupt end 5 means the external clock is valid, communication is normal, and the internal clock is faulty.

[0122] The above examples illustrate the present invention only to aid in understanding it and are not intended to limit the scope of the invention. Those skilled in the art can make various simple deductions, modifications, or substitutions based on the principles of this invention.

Claims

1. A clock signal detection and switching method for a distributed control system, characterized in that: The switching method is implemented based on a switching system, which includes a primary computer, a secondary computer, and a tertiary computer. The system also includes a primary clock signal splitting module, a clock signal switching module, an internal clock signal generation module, and a secondary clock signal splitting module. The primary computer is connected to the primary clock signal splitter module, and the primary clock signal splitter module is connected to the secondary computer and the clock signal switching module respectively. The secondary computer and the internal clock signal generation module are both connected to the clock signal switching module, and the clock signal switching module is connected to the secondary clock signal splitter module; The secondary clock signal splitter module connects to the secondary computer and the tertiary computer respectively; The switching method includes: The Level 1 computer generates an external clock signal and maintains the signal output while the Level 1 computer is operating. An internal clock signal generation module is set up in the secondary computer. The internal clock signal generation module generates an internal clock signal and maintains the signal output when the secondary computer is working. In full-state mode, the secondary computer starts up using the internal clock signal and continuously detects the external clock signal; when the external clock signal is detected, it receives the external clock signal and uses the external clock to work while stopping the detection of the external clock signal. If there are three consecutive communication errors, the detection of the external clock signal is resumed; when the external clock signal is not detected, it receives the internal clock signal and uses the internal clock to work while maintaining the detection of the external clock signal. In self-test mode, the secondary computer does not detect external clock signals; instead, it receives internal clock signals and uses the internal clock to operate. The method further includes: A secondary clock signal splitting module is set up in the secondary computer. The clock signal switching module splits the received external clock signal or internal clock signal, sending one path to the secondary computer and the other path to the tertiary computer. During the switchover, the secondary computer stops detecting the external clock signal, and all communication between the secondary and tertiary computers is temporarily interrupted, resuming after one communication cycle.

2. The method according to claim 1, characterized in that: The switching system further includes a clock signal conditioning module and a detection signal driving module, which are located between the first-level clock signal splitter module and the second-level computer. The primary clock signal splitter module is connected to the clock signal conditioning module, and then connected to the secondary computer through the detection signal driving module.

3. The method according to claim 2, characterized in that: The switching system further includes a switching control signal driving module, which is disposed between the secondary computer and the clock signal switching module. The secondary computer is connected to the switching control signal driving module, and then to the clock signal switching module.

4. The method according to claim 3, characterized in that: The internal clock signal generation module is a clock generation circuit that is consistent with the external clock circuit of the primary computer, or a clock signal generation circuit that uses technical specifications consistent with the external clock signal of the primary computer.

5. The method according to claim 4, characterized in that: The secondary computer continuously monitors external clock signals, including: The external clock signal generated by the primary computer is sent to the clock signal conditioning module, and then sent to the secondary computer through the detection signal driving module.

6. The method according to claim 5, characterized in that: When the Level 2 computer does not detect an external clock signal, it receives the internal clock signal and operates using the internal clock, including: A primary clock signal splitter module is set up in the primary computer, and a clock signal switching module is set up in the secondary computer; The external clock signal generated by the primary computer is sent to the primary clock signal splitter module. After being split by the primary clock signal splitter module, one output is sent to the clock signal conditioning module, and the other output is sent to the clock signal switching module. The default state of the clock signal switching module is to receive the external clock signal generated by the primary computer and send it to the secondary and tertiary computers; When the secondary computer does not detect an external clock signal, it sends a switching control signal to the clock signal switching module. The clock signal switching module then switches to receiving the internal clock signal generated by the internal clock signal generation module and uses the internal clock to operate.

7. The method according to claim 6, characterized in that: When the secondary computer does not detect an external clock signal, it sends a switching control signal to the clock signal switching module, including: A switching control signal drive module is set up in the secondary computer. The switching control signal issued by the secondary computer is amplified by the switching control signal drive module and then sent to the clock signal switching module.

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