A low-voltage undervoltage lockout circuit and method with zero temperature coefficient

Abstract

A zero-temperature-coefficient low-voltage undervoltage lockout circuit is characterized by comprising a voltage divider unit, a comparator unit, a feedback unit, and an output unit. The voltage divider unit generates a voltage divider of the input voltage. The comparator unit, connected to both the voltage divider unit and the output unit, generates a reference voltage based on the voltage divider and outputs the reference voltage to the output unit. The feedback unit feeds back the positive temperature coefficient current generated by the comparator unit to the voltage divider unit to counteract the negative temperature coefficient of the transistor voltage in the comparator unit. The output unit determines an output undervoltage lockout signal based on the zero-temperature-coefficient reference voltage. This invention is simple, requires few components, and significantly reduces the input voltage amplitude requirements of the undervoltage lockout circuit, allowing the undervoltage lockout signal to flip at a relatively small reference voltage, thus achieving undervoltage protection.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and more specifically, to a low-voltage undervoltage lockout circuit and method with zero temperature coefficient. Background Technology

[0002] UVLO (Under Voltage Lock Out) circuits protect circuits when the supply voltage falls below the turn-on threshold voltage of the chip or integrated circuit. Undervoltage lockout ensures that the chip is not damaged due to logic errors in subsequent circuits caused by insufficient supply voltage during soft-start or other situations, and is therefore widely used in various integrated circuits.

[0003] In existing technologies, to achieve undervoltage protection for low-voltage signals, transistors and MOSFETs with low threshold voltages are required to implement some functions in the circuit. However, the process cost of using low-threshold MOSFETs is high, and when such components are unavailable, it is difficult to generate a low-voltage UVLO threshold voltage with zero temperature coefficient.

[0004] To address this problem, there is an urgent need for a low-voltage undervoltage lockout circuit and method with zero temperature coefficient. Summary of the Invention

[0005] To address the shortcomings of existing technologies, the present invention aims to provide a low-voltage undervoltage lockout circuit with zero temperature coefficient. By acquiring the positive temperature coefficient current of the PMOS transistor in the comparator unit, the voltage of the transistor in the comparator unit with a negative temperature coefficient is compensated, thereby enabling the comparator unit to accurately generate the threshold voltage of the undervoltage lockout signal.

[0006] The present invention adopts the following technical solution.

[0007] A first aspect of the present invention relates to a zero-temperature-coefficient low-voltage undervoltage lockout circuit, wherein the circuit includes a voltage divider unit, a comparator unit, a feedback unit, and an output unit; the voltage divider unit is used to generate a voltage divider of the input voltage; the comparator unit is connected to the voltage divider unit and the output unit respectively, and is used to generate a reference voltage based on the voltage divider and output the reference voltage to the output unit; the feedback unit is used to feed back the positive temperature coefficient current generated by the comparator unit to the voltage divider unit to cancel the negative temperature coefficient of the transistor voltage in the comparator unit; the output unit determines an output undervoltage lockout signal based on the zero-temperature-coefficient reference voltage.

[0008] Preferably, the comparison unit includes a first PMOS transistor Mp1, a second PMOS transistor Mp2, a first transistor Q1, a second transistor Q2, and a bias resistor R3; wherein, the source of the first PMOS transistor Mp1 is connected to the input voltage Vin, and its gate and drain are both connected to the collector of the first transistor Q1; the source of the second PMOS transistor Mp2 is connected to the input voltage Vin, its gate is connected to the gate and drain of the first PMOS transistor, and its drain is connected to the collector of the second transistor Q2 and the input terminal of the output unit; the bases of the first transistor Q1 and the second transistor Q2 are respectively connected to the output terminal of the voltage divider unit; the emitter of the first transistor Q1 is grounded simultaneously with the emitter of the second transistor Q2 after passing through the bias resistor R3.

[0009] Preferably, the gate and drain of the first PMOS transistor Mp1 and the gate of the second PMOS transistor Mp2 in the comparison unit are all connected to the input terminal of the feedback unit.

[0010] Preferably, the feedback unit includes a fourth PMOS transistor Mp4, a first NMOS transistor Mn1, and a second NMOS transistor Mn2; wherein, the gate of the first PMOS transistor serves as the input terminal of the feedback unit, the source is connected to the input voltage Vin, and the drain is connected to the gate of the first NMOS transistor Mn1, the gate of the second NMOS transistor Mn2, and the drain of the second NMOS transistor Mn2, respectively; the sources of the first NMOS transistor Mn1 and the second NMOS transistor Mn2 are both grounded; the drain of the first NMOS transistor Mn1 serves as the output terminal of the feedback unit and is connected to the output terminal of the voltage divider unit.

[0011] Preferably, the voltage divider unit includes a first resistor R1 and a second resistor R2 connected in series, with one end of the first resistor R1 connected to the input voltage Vin and the other end of the second resistor R2 grounded; the connection point of the first resistor R1 and the second resistor R2 serves as the output of the voltage divider unit, and is connected to the output terminal of the feedback unit and the input terminal of the comparison unit, respectively.

[0012] Preferably, the output unit includes a third PMOS transistor Mp3 and a current source I0; wherein, the gate of the third PMOS transistor Mp3 is connected to the output terminal of the comparator unit, the source is connected to the input voltage Vin, the drain is connected to one end of the current source, and serves as the output terminal of the circuit to output an undervoltage lockout signal; the other end of the current source is grounded.

[0013] Preferably, the positive temperature current output by the feedback unit cancels the negative temperature voltage generated by the transistor in the comparator unit, so that the comparator unit outputs a stable reference voltage.

[0014] Preferably, the threshold voltage V between the base and emitter of the second transistor Q2 in the comparison unit is... be ≤0.7V.

[0015] Preferably, when the circuit temperature changes by a unit, the first transistor Q1 and the second transistor Q2 in the feedback unit satisfy the following condition: Where, ΔV be2 ΔV represents the decrease in threshold voltage of transistor Q2 per unit temperature. T denoted as the thermal voltage change of the first transistor Q1 and the second transistor Q2 per unit temperature, R1, R2 and R3 are the resistance values ​​of the first resistor R1, the second resistor R2 and the bias resistor R3, respectively, n is the ratio of the current density of the first transistor Q1 to the current density of the second transistor Q2, and a is the scaling factor of the current mirror in the feedback unit.

[0016] A second aspect of the present invention relates to a zero-temperature coefficient low-voltage undervoltage lockout method, which is implemented using a zero-temperature coefficient low-voltage undervoltage lockout circuit as described in the first aspect of the present invention.

[0017] The beneficial effects of this invention are that, compared with the prior art, the zero-temperature coefficient low-voltage undervoltage lockout circuit of this invention can compensate for the voltage of the transistor in the negative-temperature coefficient comparator unit by acquiring the positive temperature coefficient current of the PMOS transistor in the comparator unit, thereby enabling the comparator unit to accurately generate the threshold voltage of the undervoltage lockout signal. This invention is simple in method and requires fewer components, significantly reducing the requirements of the undervoltage lockout circuit on the input voltage amplitude, allowing the undervoltage lockout signal to flip at a relatively small reference voltage, thus achieving undervoltage protection. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of a low-voltage undervoltage lockout circuit in the prior art of this invention;

[0019] Figure 2 This is a schematic diagram of a low-voltage undervoltage lockout circuit with zero temperature coefficient according to the present invention.

[0020] Figure 3 The undervoltage protection threshold voltage V in a low-voltage undervoltage lockout circuit with zero temperature coefficient according to the present invention is... TH A schematic diagram showing how it changes with temperature;

[0021] Figure 4 In another embodiment of a low-voltage undervoltage lockout circuit with zero temperature coefficient according to the present invention, the undervoltage protection threshold voltage V is... TH A schematic diagram showing how it changes with temperature. Detailed Implementation

[0022] The present application will be further described below with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solutions of the present invention, and should not be construed as limiting the scope of protection of the present application.

[0023] Figure 1This is a schematic diagram of a low-voltage undervoltage lockout circuit in the prior art of this invention. Figure 1 As shown, an undervoltage lockout circuit may include a voltage divider unit, a comparator unit, and an output unit. Specifically, the voltage divider unit consists of... Figure 1 Resistors R1 and R2 are connected in series and output a voltage divider of the input voltage to the comparator unit. When the comparator unit receives the input voltage divider, it controls the current in the two branches based on this voltage divider. Specifically, the comparator unit in this invention can be implemented using a comparator, that is, using identical mirror MOS transistors Mp1 and Mp2, ensuring the ratio of the mirror currents of the two branches is 1:1. Simultaneously, transistors are appropriately selected so that the ratio of the transistor current densities of the two branches in the comparator unit is n:1. Therefore, the difference V between the base and emitter voltages of the first transistor... be1 The difference V between the base and emitter voltages of the second transistor be2 The difference between them is V be2 -V be1 =V T ·lnn. Wherein, V T For thermal voltage, V T Let ln / R3 be the current in the first branch. It can be seen that in this circuit, the voltage drop across resistor R4 is approximately...

[0024] For the output unit, if it is desired that the PMOS transistor Mp3 switches between on and off, the on-threshold voltage of the transistor must be set to... That's all. For the above formula, V... be2 V T The values ​​of parameters such as and n remain fixed after the circuit design is completed and the components are selected. Therefore, for this circuit, the range of the input voltage is limited after the circuit design is finalized. Restrictions.

[0025] Generally speaking, in order to ensure that the stable output value of the input voltage in the circuit, after the power supply voltage starts up and stabilizes, is sufficient to cause the PMOS transistor Mp3 in the output unit to flip from the cutoff state to the on state, the input voltage V should be guaranteed. in The maximum value, referred to in this invention as the undervoltage protection threshold voltage V. TH Even after being divided by resistors R1 and R2, it can still be greater than In other words, it should at least meet the following requirements.

[0026] In the process of selecting circuit components, in order to maintain V THFor the UVLO to be stable, at the zero-temperature threshold voltage point, after adjusting the Vb voltage to zero temperature coefficient using a resistor ratio, the transistor base voltage Vb should be approximately 1.2V. To ensure normal circuit operation, the transistor collector voltage Vc should be greater than or equal to its base voltage Vb. Assuming Vc and Vb are approximately equal, then Vb plus the PMOS threshold voltage should equal the Vin voltage. Therefore, to ensure the normal operation of each transistor and MOS transistor, the minimum threshold voltage of the UVLO should be greater than 1.2V plus the PMOS threshold voltage.

[0027] Additionally, when the transistor's V is satisfied be2 After determining the value, due to the voltage division of R1 and R2, the undervoltage protection threshold voltage V TH It will also naturally increase, even if the voltage divider is set as small as possible, the undervoltage protection threshold voltage V TH Higher than The voltage should also be sufficient to turn on PMOS transistors Mp1 and Mp2 in the comparator cell. Generally, PMOS transistors Mp1 and Mp2 can be implemented using low voltage technology (LVT), but this results in a gate-source threshold voltage difference of approximately 0.4V between Mp1 and Mp2.

[0028] In summary, Figure 1 In this circuit structure, based on existing component implementation technology, the minimum undervoltage protection threshold voltage V TH It is also around 1.6V. For a stable input voltage of around 1.2V, existing technologies cannot implement undervoltage lockout logic, or cannot guarantee the zero temperature coefficient characteristic of the undervoltage lockout threshold during implementation.

[0029] Figure 2 This is a schematic diagram of a low-voltage undervoltage lockout circuit with zero temperature coefficient according to the present invention. Figure 2 As shown, a zero-temperature-coefficient low-voltage undervoltage lockout circuit includes a voltage divider unit, a comparator unit, a feedback unit, and an output unit. The voltage divider unit generates a voltage divider of the input voltage. The comparator unit is connected to the voltage divider unit and the output unit respectively, and generates a reference voltage based on the voltage divider and outputs the bandgap reference voltage to the output unit. The feedback unit feeds back the positive temperature coefficient current generated by the comparator unit to the voltage divider unit to cancel the negative temperature coefficient of the transistor voltage in the comparator unit. The output unit determines the output undervoltage lockout signal based on the zero-temperature-coefficient reference voltage.

[0030] Understandably, this invention adds a feedback unit compared to existing technologies. This feedback unit can collect the mirror currents of PMOS transistors Mp1 and Mp2 and feed this current back to the base of the transistor. Since this current is fed back to the base of the transistor, it can work together with the voltage divided by the voltage divider unit to control the base of the transistor, allowing the transistor to enter a stable operating state. Typically, as the temperature rises, the voltage difference between the base and emitter of the transistor decreases, i.e., V... be2 It has a negative temperature coefficient, while due to the mirror image of PMOS transistor Mp3, the source-drain current of Mp3 has a positive temperature coefficient according to the bias resistor R3 in the first branch. If the two temperature coefficients can be reasonably canceled, the UVLO threshold voltage generated by the circuit can be made to remain unchanged with temperature.

[0031] Preferably, the comparison unit includes a first PMOS transistor Mp1, a second PMOS transistor Mp2, a first transistor Q1, a second transistor Q2, and a bias resistor R3; wherein, the source of the first PMOS transistor Mp1 is connected to the input voltage Vin, and its gate and drain are both connected to the collector of the first transistor Q1; the source of the second PMOS transistor Mp2 is connected to the input voltage Vin, its gate is connected to the gate and drain of the first PMOS transistor, and its drain is connected to the collector of the second transistor Q2 and the input terminal of the output unit; the bases of the first transistor Q1 and the second transistor Q2 are respectively connected to the output terminal of the voltage divider unit; the emitter of the first transistor Q1 is grounded simultaneously with the emitter of the second transistor Q2 after passing through the bias resistor R3.

[0032] In this comparison unit, because the current densities of Q1 and Q2 are different, and the ratio of the current density of Q1 to the current density of Q2 is n:1, under the action of current mirrors Mp1 and Mp2, their saturation currents are different and have a 1:n ratio. Due to the difference in saturation current, the base-emitter voltage difference of Q1 and Q2 in their stable operating state is also different. As mentioned above, the current flowing through R3 is V. T ·lnn / R3. At this time, the current in the first path containing R3 is fed back to the bases of Q1 and Q2 through the feedback unit, which can cancel the negative temperature coefficient of Vbe2. Preferably, the gate and drain of the first PMOS transistor Mp1 and the gate of the second PMOS transistor Mp2 in the comparison unit are all connected to the input terminal of the feedback unit.

[0033] In addition, to achieve mirroring and feedback for the positive temperature coefficient current, a feedback unit is added in this invention. The input of this feedback unit is the gate voltage of the two PMOS transistors in the comparator unit.

[0034] Preferably, the feedback unit includes a fourth PMOS transistor Mp4, a first NMOS transistor Mn1, and a second NMOS transistor Mn2; wherein, the gate of the first PMOS transistor serves as the input terminal of the feedback unit, the source is connected to the input voltage Vin, and the drain is connected to the gate of the first NMOS transistor Mn1, the gate of the second NMOS transistor Mn2, and the drain of the second NMOS transistor Mn2, respectively; the sources of the first NMOS transistor Mn1 and the second NMOS transistor Mn2 are both grounded; the drain of the first NMOS transistor Mn1 serves as the output terminal of the feedback unit and is connected to the output terminal of the voltage divider unit.

[0035] It is understood that in this invention, the feedback unit consists of two mirrored NMOS transistors and one PMOS transistor. The PMOS transistor Mp3 can mirror the proportional currents of Mp1 and Mp2, and then input this current from Mn2 to Mn1 to affect the base of the transistor.

[0036] By using a 1:1 mirror, the magnitude of the positive temperature coefficient current output by the feedback unit is exactly equal to the magnitude of the current in the branch containing R3. In this invention, the temperature coefficient is actually canceled out by fine-tuning the size of the resistor R3, the resistor R1, and the ratio of the current mirror after the threshold voltage has been calculated.

[0037] Preferably, the voltage divider unit includes a first resistor R1 and a second resistor R2 connected in series, with one end of the first resistor R1 connected to the input voltage Vin and the other end of the second resistor R2 grounded; the connection point of the first resistor R1 and the second resistor R2 serves as the output of the voltage divider unit, and is connected to the output terminal of the feedback unit and the input terminal of the comparison unit, respectively.

[0038] It is understood that the output terminal of the voltage divider unit in this invention serves as the input terminal of the transistor base to control the comparator unit.

[0039] Preferably, the output unit includes a third PMOS transistor Mp3 and a current source I0; wherein, the gate of the third PMOS transistor Mp3 is connected to the output terminal of the comparator unit, the source is connected to the input voltage Vin, the drain is connected to one end of the current source, and serves as the output terminal of the circuit to output an undervoltage lockout signal; the other end of the current source is grounded.

[0040] In this invention, the third PMOS transistor Mp3 is turned off or on according to the magnitude of its gate voltage. When Mp3 is turned off, the UVLO signal is a low level signal, and when Mp3 is turned on, the UVLO signal is a high level signal. At this time, the circuit can switch between normal operation and undervoltage lockout according to the state of the UVLO signal.

[0041] Preferably, the positive temperature current output by the feedback unit cancels the negative temperature voltage generated by the transistor in the comparator unit, so that the comparator unit outputs a stable reference voltage.

[0042] It is understood that if the positive temperature current output by the feedback unit in this invention just cancels the negative temperature voltage of the transistor, the comparison unit can generate a reference voltage. This voltage is a zero temperature coefficient voltage and does not change with the circuit operating temperature, thereby ensuring the accuracy of the undervoltage lockout logic.

[0043] Preferably, the threshold voltage V between the base and emitter of the second transistor Q2 in the comparator unit be ≤0.7V.

[0044] When selecting a transistor, the threshold voltage V of the transistor needs to be considered. be To ensure that the operating voltage of the circuit is sufficiently low, in this invention, V can be selected. be Transistors with a voltage of ≤0.7V.

[0045] In one embodiment of the present invention, when the threshold voltage of the transistor is around 0.5V, a PMOS transistor with a lower threshold turn-on voltage is used, so that the threshold turn-on voltages of Mp1 and Mp2 are around 0.4V. Since resistor R4 is no longer provided, the undervoltage protection threshold voltage V... TH Theoretically, the minimum voltage can be around 0.9V. In addition, even if ordinary PMOS transistors are used to reduce costs, with the thresholds of Mp1 and Mp2 around 0.7V, Vin can still provide undervoltage protection logic switching at around 1.2V.

[0046] It should be noted that in this invention, because a positive temperature coefficient current is added, and this current is actually generated due to the input voltage Vin acting on R1, causing the current flowing through R1 to increase, the positive temperature coefficient current can be assumed to be equal to the current flowing through R3, that is, this current is equal to V. T • lnn / R3. Assuming the current mirror ratio is 1, due to the effect of this current, the voltage across R1 increases relative to the original voltage across R1 and R2. This means that with the base voltages of Q1 and Q2 remaining constant, the input voltage Vin needs to increase by V. T ·lnn·R1 / R3.

[0047] In addition, to reduce the threshold voltage amplitude, since the voltage divider resistor R4 is no longer added to the circuit, the voltage across transistor Q2 is reduced. be2 This is equal to the magnitude of the input voltage after voltage division. Therefore, in this circuit of the present invention, assuming the scaling factor of the current mirror is 'a', the threshold voltage should actually be equal to...

[0048] In the method of this invention, the threshold voltage can first be set according to requirements, that is, the proportional relationship between R1 and R2 can be determined based on the input voltage Vin. Subsequently, in order to ensure the positive temperature coefficient current a·V T ·lnn / R3 can just offset the negative temperature coefficient voltage V be2 Changes can be seen in V TH_UVLO Simplify when the value of is constant. Therefore, in the actual circuit implementation process, it is possible to make The value of remains constant as the temperature changes, that is... With the values ​​of R1 and R2 determined, the value of R3 can be selected based on a certain proportion of R1, along with the current mirror scaling factor a, to obtain a complete temperature coefficient cancellation and a zero temperature coefficient undervoltage lockout reference voltage.

[0049] Figure 3 In one embodiment of a low-voltage undervoltage lockout circuit with zero temperature coefficient according to the present invention, the undervoltage protection threshold voltage V is... TH A schematic diagram showing how it changes with temperature. (Example) Figure 3 As shown, for example in Figure 2 In the circuit, the values ​​of resistors R1, R2 and R3 are set to 2.9MΩ, 11.6MΩ and 100KΩ respectively, and the current mirror scaling factor a = 1. Therefore, the threshold voltage with undervoltage protection is stable at about 1.53V in the temperature range of -55℃ to 135℃.

[0050] in addition, Figure 4 In another embodiment of a low-voltage undervoltage lockout circuit with zero temperature coefficient according to the present invention, the undervoltage protection threshold voltage V is... TH A schematic diagram showing how it changes with temperature. (Example) Figure 4 As shown, the resistance of R1 is selected to be 2.34MΩ, the resistance of R2 is 20 times that of R1, and R3 is approximately 100KΩ. The current mirror ratio remains 1, and the undervoltage protection threshold voltage is approximately 1.24V. Furthermore, as... Figure 4 As shown, the resistance remains stable below 1.24V over a temperature range of -55°C to 135°C.

[0051] A second aspect of the present invention relates to a zero-temperature coefficient low-voltage undervoltage lockout method, which is implemented using a zero-temperature coefficient low-voltage undervoltage lockout circuit as described in the first aspect of the present invention.

[0052] The beneficial effect of the present invention is that, compared with the prior art, the zero temperature coefficient low-voltage undervoltage lockout circuit of the present invention can compensate for the voltage of the transistor in the negative temperature coefficient comparator unit by acquiring the positive temperature coefficient current of the PMOS transistor in the comparator unit, thereby enabling the comparator unit to accurately generate the threshold voltage of the undervoltage lockout signal.

[0053] The applicant of this invention has provided a detailed description of the embodiments of the invention in conjunction with the accompanying drawings. However, those skilled in the art should understand that the above embodiments are merely preferred embodiments of the invention. The detailed description is only intended to help readers better understand the spirit of the invention and is not intended to limit the scope of protection of the invention. On the contrary, any improvements or modifications made based on the inventive spirit of the invention should fall within the scope of protection of the invention.

Claims

1. A zero-temperature-coefficient low-voltage under-voltage lockout circuit, characterized in that: the circuit comprises a voltage dividing unit, a comparison unit, a feedback unit and an output unit; wherein the voltage dividing unit is configured to generate a divided voltage of an input voltage; the comparison unit is connected with the voltage dividing unit and the output unit respectively, and is configured to generate a reference voltage based on the divided voltage and output the reference voltage to the output unit; the comparison unit comprises a first PMOS transistor Mp1, a second PMOS transistor Mp2, a first transistor Q1, a second transistor Q2 and a bias resistor R3; wherein the source of the first PMOS transistor Mp1 is connected with the input voltage Vin, and the gate and the drain of the first PMOS transistor Mp1 are connected with the collector of the first transistor Q1; the source of the second PMOS transistor Mp2 is connected with the input voltage Vin, the gate of the second PMOS transistor Mp2 is connected with the gate and the drain of the first PMOS transistor Mp1, and the drain of the second PMOS transistor Mp2 is connected with the collector of the second transistor Q2 and the input terminal of the output unit; the base of the first transistor Q1 and the base of the second transistor Q2 are connected with the output terminal of the voltage dividing unit respectively; the emitter of the first transistor Q1 is connected with the emitter of the second transistor Q2 through the bias resistor R3 and grounded simultaneously; the feedback unit is configured to feed back a positive temperature coefficient current generated by the comparison unit to the voltage dividing unit to offset the negative temperature coefficient of the transistor voltage in the comparison unit; and the output unit is configured to determine an output under-voltage lockout signal based on the reference voltage with zero temperature coefficient. 2.The zero-temperature-coefficient low-voltage under-voltage lockout circuit according to claim 1, characterized in that: the gate and the drain of the first PMOS transistor Mp1 and the gate of the second PMOS transistor Mp2 in the comparison unit are connected with the input terminal of the feedback unit. 3.The zero-temperature-coefficient low-voltage under-voltage lockout circuit according to claim 2, characterized in that: the feedback unit comprises a fourth PMOS transistor Mp4, a first NMOS transistor Mn1 and a second NMOS transistor Mn2; wherein the gate of the fourth PMOS transistor Mp4 is used as the input terminal of the feedback unit, the source of the fourth PMOS transistor Mp4 is connected with the input voltage Vin, and the drain of the fourth PMOS transistor Mp4 is connected with the gate and the drain of the first NMOS transistor Mn1 and the gate and the drain of the second NMOS transistor Mn2 respectively; the source of the first NMOS transistor Mn1 and the source of the second NMOS transistor Mn2 are grounded; and the drain of the first NMOS transistor Mn1 is used as the output terminal of the feedback unit and connected with the output terminal of the voltage dividing unit. 4.The zero-temperature-coefficient low-voltage under-voltage lockout circuit according to claim 3, characterized in that: the voltage dividing unit comprises a first resistor R1 and a second resistor R2 connected in series, one end of the first resistor R1 is connected with the input voltage Vin, and the other end of the second resistor R2 is grounded; and the connection point of the first resistor R1 and the second resistor R2 is used as the output of the voltage dividing unit and connected with the output terminal of the feedback unit and the input terminal of the comparison unit respectively. 5.The zero-temperature-coefficient low-voltage under-voltage lockout circuit according to claim 4, characterized in that: ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ The output unit comprises a third PMOS transistor Mp3 and a current source I0; wherein, a gate of the third PMOS transistor Mp3 is connected with an output end of the comparison unit, a source is connected with an input voltage Vin, a drain is connected with one end of the current source I0, and outputs an under-voltage lockout signal as an output end of the circuit; the other end of the current source I0 is grounded.

6. The zero-temperature-coefficient low-voltage under-voltage lockout circuit according to claim 5, wherein: a positive temperature current output by the feedback unit offsets a negative temperature voltage generated by the transistor in the comparison unit, so that the comparison unit outputs a stable reference voltage.

7. The zero-temperature-coefficient low-voltage under-voltage lockout circuit according to claim 6, wherein: the threshold voltage Vth between the base and the emitter of the second triode Q2 in the comparison unit be ≤ 0.7 V.

8. The zero-temperature-coefficient low-voltage under-voltage lockout circuit according to claim 7, wherein: When the unit change of the circuit temperature occurs, the first transistor Q1 and the second transistor Q2 in the feedback unit satisfy where ΔV be2 is the threshold voltage reduction of the second triode Q2 per unit temperature, ΔV T ΔV T ΔV T ΔV T ΔV T ΔV T ΔV T ΔV T ΔV <000000 R1, R2 and R3 are respectively a first resistance R1, a second resistance R2 and a bias resistance R3, n is a current density ratio of the first transistor Q1 and the second transistor Q2, a is a proportional coefficient of the current mirror in the feedback unit.

9. A zero-temperature-coefficient low-voltage under-voltage lockout method, comprising: the method is implemented by using the zero-temperature-coefficient low-voltage under-voltage lockout circuit according to any one of claims 1-8.

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