Trimming circuit and trimming method

Abstract

The application provides a trimming circuit and a trimming method. The trimming circuit comprises an enable control module, a clock generation module, a clock division module, a fuse control module, a reference voltage generation module and a comparison module. The enable control module is used for generating and outputting a clock enable signal according to a trimming enable signal and an enable-off signal. The clock generation module is used for generating and outputting a clock signal according to the clock enable signal. The clock division module is used for dividing the clock signal to generate and output (n+1) trimming control bits. The fuse control module is used for controlling a fuse array according to the (n+1) trimming control bits to generate and output (n+2) trimming bits. The reference voltage generation module is used for generating and outputting a reference voltage corresponding to the (n+2) trimming bits. The comparison module is used for comparing the reference voltage and a target voltage, and generating and outputting the enable-off signal when the reference voltage reaches the target voltage. The trimming circuit and the trimming method provided by the application solve the problem that the trimming code cannot be accurately obtained by the calculation method or the table lookup method.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of electronic circuit, in particular to a trimming circuit and a trimming method. BACKGROUND

[0002] In the field of integrated circuit, due to the influence of process distribution, the parameters of the produced chips have a certain distribution. In the application with high parameter accuracy requirement, trimming method is needed to reduce the influence of parameter distribution and improve the consistency of parameter accuracy to meet the application requirement. Figure 1 and Figure 2 As shown in the figures, the parameter value distribution is wide before trimming, and the parameter value concentration is greatly improved after trimming.

[0003] The known trimming methods mainly include electrical trimming, laser trimming, eFuse (electronic fuse) or EEROM (electrically erasable programmable read-only memory) code trimming. In the code trimming, the trimming code is generally obtained by calculation or table lookup method, and then the fuse is trimmed by the obtained trimming code.

[0004] The principle of the calculation method is to measure the measurement voltage that needs to be trimmed, calculate the trimming step number according to the following formula, and then look up the trimming code corresponding to the step number to perform trimming operation. The trimming step number NUM obtained by calculation is rounded off, and the trimming code corresponding to the trimming step number is obtained by table lookup, and then the fuse is trimmed by the trimming code.

[0005]

[0006] Wherein, NUM is the trimming step number, VREF(CP) is the measurement voltage, VREF0 is the reference voltage, V STEP is the minimum step size.

[0007] Although the calculation method for obtaining the trimming code is simple and easy to implement, this method has high consistency requirement for the minimum step size V STEP , that is, the condition for the formula to be established is that the value of the minimum step size V STEP remains consistent as much as possible during each trimming, so as to obtain accurate trimming step number, which is difficult to achieve in integrated circuit manufacturing process.

[0008] The table lookup method arranges the trimming range corresponding to each trimming code into a table through large data statistics. The measurement value falling within the trimming range corresponding to the specified trimming code is selected for trimming. Compared with the calculation method, the process distribution problem is solved to a certain extent, and the table lookup method directly eliminates the calculation process, so the program execution efficiency is high.

[0009] Although the table lookup method reduces the minimum step size V STEPthe distribution of the minimum step V STEP The process distribution is always present; and when the trimming deviation is large, on the one hand, the corresponding chip is small, and the trimming range lacks statistical basis; on the other hand, due to the influence of cumulative error, in this case, the lowest precision of trimming is directly covered by error, and in high-precision application scenarios, that is, when the parameter precision is higher, the lookup table method will have limitations; in addition, the condition for the lookup table method to be established is that the reference voltage VREF0 must be fixed each time the trimming is performed, and when the reference voltage VREF0 changes, a trimming table needs to be re-made, and the flexibility is greatly limited, which has great limitations in LDO (low dropout linear regulator) multi-voltage trimming or lithium battery protection system applications with multiple protection voltages. SUMMARY

[0010] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a trimming circuit and a trimming method for solving the problem that the trimming code cannot be accurately obtained by the calculation method or the lookup table method.

[0011] To achieve the above-mentioned purpose and other related purposes, the present application provides a trimming circuit, which comprises an enable control module, a clock generation module, a clock frequency division module, a fuse control module, a reference voltage generation module and a comparison module,

[0012] The enable control module is used to generate and output a clock enable signal according to a trimming enable signal and an enable off signal;

[0013] The clock generation module is connected to the output end of the enable control module, and is used to generate and output a clock signal according to the clock enable signal;

[0014] The clock frequency division module is connected to the output end of the clock generation module, and is used to frequency-division the clock signal to generate and output (n+1) -bit trimming control bits;

[0015] The fuse control module is connected to the output end of the clock frequency division module, and is used to control a fuse array according to the (n+1) -bit trimming control bits to generate and output (n+2) -bit trimming bits;

[0016] The reference voltage generation module is connected to the output end of the fuse control module, and is used to generate and output a reference voltage corresponding to the (n+2) -bit trimming bits;

[0017] The comparison module is connected to the output end of the reference voltage generation module, and is used to compare the reference voltage and a target voltage, and generate and output the enable off signal when the reference voltage reaches the target voltage;

[0018] Wherein, n is a positive integer greater than or equal to 1.

[0019] Optionally, the clock frequency division module comprises (n+1) D flip-flops; wherein the reset terminals of the (n+1) D flip-flops are connected to the trimming enable signal, the clock terminal of the first D flip-flop is connected to the clock signal, the clock terminals of the last n D flip-flops are connected to the output non-inverted terminals of the previous D flip-flops, the data input terminals of the (n+1) D flip-flops are connected to the output inverted terminals of the respective D flip-flops, and the output non-inverted terminals of the (n+1) D flip-flops are used as the output terminals of the clock frequency division module.

[0020] Optionally, the output inverted terminals of the (n+1) D flip-flops are used as the output terminals of the clock frequency division module.

[0021] Optionally, the fuse control module comprises (n+1) AND gates and (n+1) fuse arrays, each of the fuse arrays comprises one fuse and one switch, and the fuse and the switch are connected in series; wherein the first input terminals of the (n+1) AND gates are connected to the (n+1) trimming control bits respectively, the second input terminals of the (n+1) AND gates are connected to the trimming enable signal, and the output terminals of the (n+1) AND gates are connected to the control terminals of the (n+1) switches respectively; the (n+1) fuse arrays are connected in series to form (n+2) nodes, and the (n+2) nodes are used as the output terminals of the fuse control module.

[0022] Optionally, the reference voltage generation module comprises a first voltage dividing resistor, a second voltage dividing resistor and (n+1) trimming resistors; wherein the first voltage dividing resistor, the (n+1) trimming resistors and the second voltage dividing resistor are connected in series between a reference voltage and a reference ground voltage to form (n+2) connection nodes, the (n+2) connection nodes are connected to the (n+2) trimming bits respectively, and the connection node between the first voltage dividing resistor and the first trimming resistor is used as the output terminal of the reference voltage generation module.

[0023] Optionally, the comparison module is implemented by a comparator; wherein the first input terminal of the comparator is connected to the target voltage, the second input terminal of the comparator is connected to the reference voltage, and the output terminal of the comparator is used as the output terminal of the comparison module.

[0024] Optionally, the trimming circuit further comprises a target voltage generation module configured to generate and output the target voltage.

[0025] The application further provides a trimming method, which comprises:

[0026] 1) generating a clock enable signal when the trimming enable signal is valid, and stopping outputting the clock enable signal when the enable-off signal is valid;

[0027] 2) generating a clock signal based on the clock enable signal, frequency dividing the clock signal and generating (n+1) bit trimming control bits;

[0028] 3) fuse control based on (n+1) bit trimming control bits and generating (n+2) bit trimming bits, generating reference voltage corresponding to the (n+2) bit trimming bits based on the (n+2) bit trimming bits;

[0029] 4) comparing the reference voltage and the target voltage, and generating the enable-off signal when the reference voltage reaches the target voltage, and obtaining a trimming code, the trimming code being a ratio of an effective duration of the clock enable signal to a frequency of the clock signal;

[0030] wherein n is a positive integer greater than or equal to 1.

[0031] Optionally, during the trimming process, the reference voltage monotonically increases in order from small to large, or the reference voltage monotonically decreases in order from large to small.

[0032] Optionally, the trimming method further comprises: 5) a step of trimming and solidifying the fuse based on the trimming code.

[0033] As described above, the trimming circuit and the trimming method of the present application use the self-adaptive principle combined with the successive approximation principle to trim the reference voltage, without a trimming table, so that any voltage in the trimming range can be trimmed, and the minimum step V STEP deviation distribution can be completely ignored, and the trimming accuracy is as high as + / - 0.5V STEP ; Moreover, the trimming code is determined by the ratio of the effective duration of the clock enable signal to the frequency of the clock signal, which is irrelevant to the accuracy of the clock signal, and can meet the trimming requirements of high-precision systems. The present application is simple to operate, and only needs to continuously output the clock signal to obtain the final trimming code; and part of the circuit of the present application can be reused in the chip circuit, only a part of the circuit needs to be additionally added, and the circuit is simple and will not increase the layout area. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1 A schematic diagram showing the parameter value distribution before chip trimming.

[0035] Figure 2 A schematic diagram showing the parameter value distribution after chip trimming.

[0036] Figure 3 A schematic diagram of the trimming circuit of the present application.

[0037] Figure 4 A schematic diagram of the clock frequency division module of the present application.

[0038] Figure 5 Another schematic diagram of the clock dividing module of the present application.

[0039] Figure 6 A schematic diagram of the fuse control module and the reference voltage generating module of the present application.

[0040] Figure 7 A timing diagram of the signals related to the trimming circuit of the present application during the trimming process.

[0041] Element Number Description

[0042] 10 trimming circuit

[0043] 100 enable control module

[0044] 200 clock generating module

[0045] 300 clock dividing module

[0046] 400 fuse control module

[0047] 401 fuse array

[0048] 500 reference voltage generating module

[0049] 600 comparison module

[0050] 700 target voltage generating module DETAILED DESCRIPTION

[0051] The present application is herein described, by way of example only, with reference to certain embodiments thereof. It is to be understood that variations and modifications of the embodiments can be made based on the description set forth herein, without departing from the scope and spirit of the application. The application can also be implemented in different embodiments and applied to different applications, and the various details of the application can be modified in sub-modes based on different views and applications, without departing from the spirit of the application.

[0052] Reference will now be made to the drawings, wherein Figures 3 to 7 It is to be understood that the drawings are to be used only for illustrative purposes and the drawings shown in the figures are only to schematically show the basic concept of the present application and thus, in the drawings, only the components related to the present application are shown rather than the components shown in the actual implementation, the number, shape and size of the components in the actual implementation can be arbitrarily changed and the layout of the components can be more complicated.

[0053] As Figure 3As shown, the embodiment provides a trimming circuit 10, which comprises an enable control module 100, a clock generation module 200, a clock division module 300, a fuse control module 400, a reference voltage generation module 500, and a comparison module 600. Further, the trimming circuit 10 further comprises a target voltage generation module 700.

[0054] The enable control module 100 is configured to generate and output a clock enable signal EN according to a trimming enable signal TrimEN and a shutdown signal SC.

[0055] Specifically, the enable control module 100 is configured to generate and output the clock enable signal EN when the trimming enable signal TrimEN is valid, and stop outputting the clock enable signal EN when the shutdown signal SC is valid. In actual applications, any circuit capable of achieving the above functions is applicable to the embodiment, and the embodiment does not limit the specific circuit implementation of the enable control module 100.

[0056] The clock generation module 200 is connected to the output end of the enable control module 100, and is configured to generate and output a clock signal CLK according to the clock enable signal EN.

[0057] Specifically, the clock generation module 200 is implemented by an oscillator, which is controlled by the clock enable signal EN and generates and outputs a clock signal CLK with a stable frequency when the clock enable signal EN is valid. In actual applications, the oscillator can be multiplexed with the oscillator of a chip without additional settings.

[0058] The clock division module 300 is connected to the output end of the clock generation module 200, and is configured to divide the clock signal CLK to generate and output (n+1) trimming control bits clk0-clkn; wherein n is a positive integer greater than or equal to 1, and the value of n is determined by the number of fuses in the trimming circuit 10, that is, n=fuse number-1. In actual applications, the clock division module 300 can be fully or partially multiplexed with the clock division circuit of a chip, which depends on the division bit number of the clock division circuit of the chip. If the division bit numbers are the same, the clock division module 300 can be fully multiplexed, and if the division bit numbers are insufficient, the clock division module 300 can be partially multiplexed.

[0059] Specifically, in an example, the clock dividing module 300 includes: (n+1) D flip-flops DFF0-DFFn; wherein the reset terminals of the (n+1) D flip-flops DFF0-DFFn are connected to the trimming enable signal TrimEN, the clock terminal of the first D flip-flop DFF0 is connected to the clock signal CLK, the clock terminals of the last n D flip-flops DFF1-DFFn are connected to the output non-inverted terminals of the previous D flip-flops, the data input terminals of the (n+1) D flip-flops DFF0-DFFn are connected to the output inverted terminals of the respective D flip-flops, and the output non-inverted terminals of the (n+1) D flip-flops DFF0-DFFn are used as the output terminals of the clock dividing module 300 to output (n+1) trimming control bits clk0-clkn (as shown in Figure 4

[0060] For the clock dividing module 300 in this example, the trimming control bits output successively by the clock dividing module 300 change monotonically in ascending order, so that the reference voltage Vref generated by the reference voltage generating module 500 also changes monotonically in ascending order, thereby enabling the comparison module 600 to perform comparison operations based on the principle of successive approximation.

[0061] In another example, the clock dividing module 300 includes: (n+1) D flip-flops DFF0-DFFn; wherein the reset terminals of the (n+1) D flip-flops DFF0-DFFn are connected to the trimming enable signal TrimEN, the clock terminal of the first D flip-flop DFF0 is connected to the clock signal CLK, the clock terminals of the last n D flip-flops DFF1-DFFn are connected to the output non-inverted terminals of the previous D flip-flops, the output non-inverted terminal of the nth D flip-flop DFFn is left unconnected, the data input terminals of the (n+1) D flip-flops DFF0-DFFn are connected to the output inverted terminals of the respective D flip-flops, and the output inverted terminals of the (n+1) D flip-flops DFF0-DFFn are used as the output terminals of the clock dividing module 300 to output (n+1) trimming control bits clk0-clkn (as shown in Figure 5

[0062] For the clock dividing module 300 in this example, the trimming control bits output successively by the clock dividing module 300 change monotonically in descending order, so that the reference voltage Vref generated by the reference voltage generating module 500 also changes monotonically in descending order, thereby enabling the comparison module 600 to perform comparison operations based on the principle of successive approximation.

[0063] ​​The fuse control module 400 is connected to the output end of the clock frequency division module 300, and is configured to control the fuse array 401 according to the (n+1) bit trimming control bits clk0-clkn, and generate and output (n+2) bit trimming bits Fb0-Fb(n+1).

[0064] Specifically, the fuse control module 400 includes (n+1) AND gates AND0-ANDn and (n+1) fuse arrays 401. The fuse array 401 includes one fuse and one switch, and the fuse and the switch are connected in series. The first input end of the (n+1) AND gates AND0-ANDn is connected to the (n+1) bit trimming control bits clk0-clkn, the second input end of the (n+1) AND gates AND0-ANDn is connected to the trimming enable signal TrimEN, and the output end of the (n+1) AND gates AND0-ANDn is connected to the control end of the (n+1) switches S0-Sn. The (n+1) fuse arrays 401 are connected in series to form (n+2) nodes, and the (n+2) nodes are used as the output end of the fuse control module 400 to output the (n+2) bit trimming bits Fb0-Fb(n+1) (as shown in the figure). Figure 6

[0065] In this embodiment, the corresponding trimming control bit and the trimming enable signal TrimEN are subjected to logical AND operation through the AND gate, and the opening and closing of the corresponding switch are controlled through the logical operation result, so as to simulate the burning behavior of the fuse. For example, when the corresponding switch is open, the corresponding fuse is not connected to the subsequent reference voltage generation module 500, which is equivalent to the fuse blowing behavior. When the corresponding switch is closed, the corresponding fuse is connected to the subsequent reference voltage generation module 500, which is equivalent to the fuse not blowing behavior. In this way, the (n+2) bit trimming bits Fb0-Fb(n+1) are output.

[0066] The reference voltage generation module 500 is connected to the output end of the fuse control module 400, and is configured to generate and output the reference voltage Vref corresponding to the (n+2) bit trimming bits Fb0-Fb(n+1).

[0067] Specifically, the reference voltage generation module 500 includes a first voltage dividing resistor R1, a second voltage dividing resistor R2, and (n+1) trimming resistors 2 0 *Rtrim-2 n *Rtrim;wherein the first voltage dividing resistor R1, the (n+1) trimming resistors 2 0 *Rtrim-2 n ​Rtrim and the second voltage dividing resistor R2 are connected in series between a reference voltage Vr and a reference ground voltage VSS and form (n+2) connection nodes, the (n+2) connection nodes correspond to the (n+2) bits of the trimming bits Fb0-Fb(n+1), and the first voltage dividing resistor R1 and the first trimming resistor R2 are connected in series between the (n+2) connection nodes and the reference ground voltage VSS 0 The connection node between Rtrim and Rtrim is taken as an output terminal of the reference voltage generating module 500, and is used to output a corresponding reference voltage Vref (as shown in FIG. 2). Figure 6 More specifically, the resistance values of the (n+1) trimming resistors increase exponentially by 2, and satisfy the formula 2 m-1 Rtrim, where m is the mth trimming resistor in the (n+1) trimming resistors, and Rtrim is the set trimming resistance value.

[0068] In this embodiment, the reference voltage generating module 500 is a resistor voltage dividing circuit, and the (n+2) bits of the trimming bits Fb0-Fb(n+1) output by the fuse control module 400 are used to control the voltage dividing ratio of the resistor voltage dividing circuit, so as to generate a corresponding reference voltage Vref; wherein the minimum step size satisfies the formula Vr is a reference voltage, R1 is the resistance value of the first voltage dividing resistor, R2 is the resistance value of the second voltage dividing resistor, Rtrim is the set trimming resistance value, and K=2 0 +2 1 +…+2 n .

[0069] The comparison module 600 is connected to the output terminal of the reference voltage generating module 500, and is used to compare the reference voltage Vref and a target voltage VS, and generate and output the enable-off signal SC when the reference voltage Vref reaches the target voltage VS.

[0070] Specifically, the comparison module 600 is implemented by a comparator; wherein a first input terminal of the comparator is connected to the target voltage VS, a second input terminal of the comparator is connected to the reference voltage Vref, and an output terminal of the comparator is taken as the output terminal of the comparison module 600. Optionally, the first input terminal is the non-inverting input terminal of the comparator, and the second input terminal is the inverting input terminal of the comparator.

[0071] In the embodiment, when the reference voltage Vref does not reach the target voltage VS, the comparator outputs high level in the case that the reference voltage Vref monotonously increases from small to large, and the comparator outputs low level in the case that the reference voltage Vref monotonously decreases from large to small; when the reference voltage Vref reaches the target voltage VS, the output of the comparator flips, i.e., the output of the comparator changes from high level to low level in the case that the reference voltage Vref monotonously increases from small to large, and the output of the comparator changes from low level to high level in the case that the reference voltage Vref monotonously decreases from large to small, at this time, the enable-off signal SC is valid.

[0072] The output terminal of the target voltage generation module 700 is connected to an input terminal of the comparison module 600, for generating and outputting the target voltage VS.

[0073] Specifically, the target voltage generation module 700 can be implemented by a resistance voltage division circuit, for example, in a battery management system, which can be a voltage division of a battery voltage.

[0074] In actual application, for the trimming circuit 10 in the embodiment, in order to read out the clock enable signal EN and the clock signal CLK to calculate the trimming code, the reading pins of the corresponding signals can be set, such as the EN pin and the CLK pin; at the same time, in order to input the trimming enable signal TrimEN and generate the target voltage VS, the input pins of the corresponding signals can be set, such as the TrimEN pin and the VIN pin.

[0075] Correspondingly, the embodiment further provides a trimming method, which comprises:

[0076] 1) generating a clock enable signal when the trimming enable signal is valid, and stopping outputting the clock enable signal when the enable-off signal is valid.

[0077] 2) generating a clock signal based on the clock enable signal, frequency-dividing the clock signal and generating (n+1) -bit trimming control bits; wherein n is a positive integer greater than or equal to 1.

[0078] Specifically, an oscillator is used to generate a clock signal with a stable frequency, and a D flip-flop is used to realize clock frequency division to generate (n+1) -bit trimming control bits. In the trimming process, when the trimming control bits are generated multiple times, the multiple trimming control bits generated in sequence monotonously increase from small to large, or monotonously decrease from large to small.

[0079] 3) fuse control based on the (n+1) bit trim control bits and generate (n+2) bit trim bits, generate reference voltage corresponding to the (n+2) bit trim bits.

[0080] Specifically, the method for generating reference voltage includes: performing logical "and" operation between (n+1) bit trim control bits and trim enable signal respectively, and generating (n+1) switch control signals; controlling the opening and closing of corresponding switches in the fuse array based on the (n+1) switch control signals, so as to control whether the corresponding fuse is connected to the resistance voltage dividing circuit, and generating corresponding reference voltage based on resistance voltage division. During the trimming process, the reference voltage monotonically increases in order from small to large, or the reference voltage monotonically decreases in order from large to small.

[0081] 4) comparing the reference voltage and the target voltage, and generating the enable-off signal when the reference voltage reaches the target voltage, and thereby obtaining the trim code, which is the ratio of the effective duration of the clock enable signal to the frequency of the clock signal.

[0082] Further, the trimming method further includes: 5) the step of trimming and fixing the fuse based on the trim code. In practical application, methods such as laser, electric burning, etc. can be used to realize fuse trimming and fixing.

[0083] Please refer to Figures 3-6 , and refer to Figure 7 , the specific trimming process involved in the trimming circuit and trimming method of the embodiment will be described; taking n=3 as an example, the reference voltage monotonically increases in order from small to large.

[0084] After the chip is powered on, when the trim enable signal TrimEN is valid, the clock enable signal EN is valid, and the clock signal CLK is generated; the clock signal CLK is clocked to generate 4-bit trim control bits clk0-clk3 (corresponding to trimcode0

[0000] -15

[1111] ); fuse control is performed based on the 4-bit trim control bits clk0-clk3, and reference voltages V0-V15 are generated; the reference voltages are compared with the target voltage; when the reference voltage V13 is equal to the target voltage VS, the enable-off signal is generated to stop outputting the clock enable signal, at which time the trimming is completed.

[0085] The trim code is obtained by calculating the ratio of the effective duration of the clock enable signal to the frequency of the clock signal, which is the number of pulses of the clock signal in the effective duration of the clock enable signal, which is 13, converted to binary as 1101. Finally, the fuse is fixed based on the trim code to complete the trimming.

[0086] It should be noted that due to signal delay in signal transmission and processing, decimal number will appear when calculating the trimming code, at this time, the integer part is reserved as the trimming code.

[0087] In summary, the trimming circuit and trimming method of the present application adopts the adaptive principle combined with the successive approximation principle to trim the reference voltage, and can trim any voltage within the trimming range without trimming table, and can completely ignore the minimum step V STEP The cumulative error influence caused by the deviation distribution makes the trimming accuracy up to + / - 0.5V STEP ; and the trimming code is determined by the ratio of the effective duration of the clock enable signal and the frequency of the clock signal, and is irrelevant to the accuracy of the clock signal, and can meet the trimming requirements of high-precision systems. The present application is simple to operate, and only needs to continuously give the clock signal to obtain the final trimming code; and part of the circuit of the present application can be reused in the chip circuit, and only needs to additionally increase part of the circuit, so the circuit is simple and will not increase too much layout area. Therefore, the present application effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0088] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes completed by those skilled in the art without departing from the spirit and technical thought disclosed by the present application should be covered by the claims of the present application.

Claims

1. A tuning circuit, characterized in that, The adjustment circuit includes: an enable control module, a clock generation module, a clock divider module, a fuse control module, a reference voltage generation module, and a comparison module. The enable control module is used to generate and output a clock enable signal based on the adjustment enable signal and the enable disable signal; The clock generation module is connected to the output terminal of the enable control module and is used to generate and output a clock signal according to the clock enable signal. The clock divider module is connected to the output of the clock generation module and is used to divide the clock signal to generate and output (n+1) trim control bits. The fuse control module is connected to the output of the clock divider module and is used to control the fuse array according to the (n+1) trim control bits, and generate and output (n+2) trim control bits. The reference voltage generation module is connected to the output terminal of the fuse control module and is used to generate and output a reference voltage corresponding to the (n+2) trimming bits. The comparison module is connected to the output terminal of the reference voltage generation module, and is used to compare the reference voltage and the target voltage, and generate and output the enable / disable signal when the reference voltage reaches the target voltage. During the adjustment process, the clock divider module outputs multiple times, and the (n+1) adjustment control bits output multiple times change monotonically in ascending order, so that the reference voltage changes monotonically in ascending order; or, the (n+1) adjustment control bits output multiple times change monotonically in descending order, so that the reference voltage changes monotonically in descending order. This allows the comparison module to perform a comparison operation based on the successive approximation principle. Here, the adjustment code is the ratio of the effective duration of the clock enable signal to the frequency of the clock signal, and n is a positive integer greater than or equal to 1.

2. The adjustment circuit according to claim 1, characterized in that, The clock divider module includes (n+1) D flip-flops; wherein the reset terminals of the (n+1) D flip-flops are connected to the adjustment enable signal, the clock terminal of the first D flip-flop is connected to the clock signal, the clock terminals of the next n D flip-flops are connected to the non-inverting output terminals of the previous D flip-flop, the data input terminals of the (n+1) D flip-flops are connected to their respective inverting output terminals, and the non-inverting output terminals of the (n+1) D flip-flops serve as the output terminals of the clock divider module.

3. The adjustment circuit according to claim 2, characterized in that, The inverting outputs of (n+1) D flip-flops are used as the outputs of the clock divider module.

4. The adjustment circuit according to claim 1, characterized in that, The fuse control module includes (n+1) AND gates and (n+1) fuse arrays. Each fuse array includes one fuse and one switch, with the fuse and the switch connected in series. The first input of each of the (n+1) AND gates is connected to the (n+1) trimming control bits, the second input of each of the (n+1) AND gates is connected to the trimming enable signal, and the output of each of the (n+1) AND gates is connected to the control terminals of the (n+1) switches. The (n+1) fuse arrays are connected in series to form (n+2) nodes, which serve as the output terminals of the fuse control module.

5. The adjustment circuit according to claim 1, characterized in that, The reference voltage generation module includes a first voltage divider resistor, a second voltage divider resistor, and (n+1) adjustment resistors; wherein, the first voltage divider resistor, (n+1) adjustment resistors, and the second voltage divider resistor are connected in series between the reference voltage and the reference ground voltage to form (n+2) connection nodes, and the (n+2) connection nodes are connected to (n+2) adjustment positions respectively, and the connection node between the first voltage divider resistor and the first adjustment resistor serves as the output terminal of the reference voltage generation module.

6. The adjustment circuit according to claim 1, characterized in that, The comparison module is implemented using a comparator; wherein, the first input terminal of the comparator is connected to the target voltage, the second input terminal is connected to the reference voltage, and the output terminal serves as the output terminal of the comparison module.

7. The adjustment circuit according to any one of claims 1-6, characterized in that, The adjustment circuit further includes a target voltage generation module for generating and outputting the target voltage.

8. A method for adjusting settings, characterized in that, The adjustment method includes: 1) Generate a clock enable signal when the adjustment enable signal is valid, and stop outputting the clock enable signal when the enable disable signal is valid; 2) Generate a clock signal based on the clock enable signal, divide the clock signal by frequency and generate (n+1) trim control bits; 3) Based on the (n+1) trim control bit, perform fuse control and generate (n+2) trim bits, and generate a corresponding reference voltage based on the (n+2) trim bits; 4) Compare the reference voltage and the target voltage, and generate the enable / disable signal when the reference voltage reaches the target voltage, thereby obtaining a modifier code, wherein the modifier code is the ratio of the effective duration of the clock enable signal to the frequency of the clock signal; During the adjustment process, (n+1) adjustment control bits are output multiple times. The (n+1) adjustment control bits output multiple times are monotonically increasing in ascending order, so that the reference voltage is monotonically increasing in ascending order. Alternatively, the (n+1) adjustment control bits output multiple times are monotonically decreasing in descending order, so that the reference voltage is monotonically decreasing in descending order. This is based on the principle of successive approximation for comparison operation. Where n is a positive integer greater than or equal to 1.

9. The adjustment method according to claim 8, characterized in that, The adjustment method further includes: 5) the step of adjusting and solidifying the fuse based on the adjustment code.

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