Method, apparatus and integrated circuit for calibrating on-chip clock

Abstract

The application relates to the technical field of clock signal processing, and discloses a calibration method of an on-chip clock. The calibration method comprises the following steps: obtaining a first frequency of a sampled clock; determining a target sampling count corresponding to both the first frequency and a target frequency; sampling a frequency signal output by the sampled clock at an output frequency of the on-chip clock, and recording a first sampling count; in the case that the absolute value of the difference between the first sampling count and the target sampling count is greater than a preset threshold value, adjusting a calibration value of the on-chip clock, and resampling the frequency signal output by the sampled clock at the output frequency of the on-chip clock to record the first sampling count; and in the case that the absolute value of the difference between the first sampling count and the target sampling count is less than or equal to the preset threshold value, confirming that the calibration of the on-chip clock is completed. The calibration method can improve the calibration efficiency of the on-chip clock. The application further discloses a calibration device of the on-chip clock and an integrated circuit.

Description

Technical Field

[0001] The present application relates to the technical field of clock signal processing, for example, to an on-chip clock calibration method, apparatus and integrated circuit. Background

[0002] At present, an on-chip clock can output clocks of different frequencies according to different input calibration values. As the calibration value increases, the output frequency gradually rises, but does not follow a simple linear relationship. If a clock of a specific frequency is required in a certain scenario, the calibration value needs to be adjusted to a corresponding value.

[0003] The existing processing method is to manually adjust the calibration through iteration, so that the output frequency finally meets the target value. See Figure 1 , which is a simplified schematic diagram of the existing manual calibration adjustment. Using the dichotomy method, the calibration value is first set to the median 5, the output frequency f5 is compared with the target frequency fd on the machine through a test program. Since fd<f5, the calibration value is then set to the median 3 in the range of 1 to 5, and then fd is compared with f3... After such iterations, it is finally found that when the calibration value is 4, the frequency of the on-chip clock meets the target frequency fd.

[0004] In the process of implementing the embodiments of the present disclosure, it is found that at least the following problems exist in the related art:

[0005] The existing manual iterative calibration adjustment method has low efficiency. Summary of the Invention

[0006] To provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not an extensive overview, nor is it intended to identify key / critical elements or delineate the scope of protection of these embodiments, but serves as a preamble to the subsequent detailed description.

[0007] The embodiments of the present disclosure provide an on-chip clock calibration method, apparatus and integrated circuit, so as to improve the calibration efficiency of the on-chip clock.

[0008] In some embodiments, the on-chip clock calibration method includes: obtaining a first frequency of the sampled clock; determining a target sampling count corresponding to the first frequency and a target frequency based on the correspondence between frequency and sampling count; sampling the frequency signal output by the sampled clock at the output frequency of the on-chip clock and recording a first sampling count; adjusting the calibration value of the on-chip clock and re-sampling the frequency signal output by the sampled clock at the output frequency of the on-chip clock if the absolute value of the difference between the first sampling count and the target sampling count is greater than a preset threshold value, and recording a first sampling count; confirming that the on-chip clock calibration is complete if the absolute value of the difference between the first sampling count and the target sampling count is less than or equal to a preset threshold value.

[0009] Optionally, determining the target sampling count corresponding to the first frequency and the target frequency based on the correspondence between frequency and sampling count includes:

[0010]

[0011] Among them, CNT dst For the target sampling count, f dst For the target frequency, f clk This is the first frequency.

[0012] Optionally, sampling the frequency signal output by the sampled clock at the output frequency of the on-chip clock and recording a first sampling count includes: performing frequency division processing on the frequency signal output by the sampled clock to obtain a second frequency corresponding to the first frequency; the product of the first frequency and the frequency division coefficient is the second frequency; sampling the frequency signal corresponding to the second frequency at the output frequency of the on-chip clock for multiple consecutive cycles; the cycle is the period of the frequency signal corresponding to the second frequency.

[0013] Optionally, determining the target sampling count corresponding to the first frequency and the target frequency based on the correspondence between frequency and sampling count includes:

[0014]

[0015] Among them, CNT dst For target sampling count, div is the frequency division coefficient, period is the number of consecutive periods, and f dst For the target frequency, f clk This is the first frequency.

[0016] Optionally, determining the target sampling count corresponding to the first frequency and the target frequency includes: obtaining a multiplier of the target frequency when the target frequency is not within the output frequency range of the on-chip clock; and determining the target sampling count corresponding to the first frequency and the multiplier of the target frequency based on the correspondence between frequency and sampling count.

[0017] Optionally, adjusting the calibration value of the on-chip clock includes: reducing the calibration value of the on-chip clock to reduce the output frequency of the on-chip clock when the absolute value of the difference between the first sampling count and the target sampling count is greater than a preset threshold and the difference is greater than zero.

[0018] Optionally, adjusting the calibration value of the on-chip clock includes: increasing the calibration value of the on-chip clock to increase the output frequency of the on-chip clock when the absolute value of the difference between the first sampling count and the target sampling count is greater than a preset threshold and the difference is less than zero.

[0019] Optionally, each time the frequency signal of the sampled clock is sampled at the output frequency of the on-chip clock, the on-chip clock is first set to start oscillating for a set duration, and then the frequency signal of the sampled clock is sampled at the output frequency of the on-chip clock.

[0020] Optionally, after confirming the completion of the on-chip clock calibration, the on-chip clock calibration method further includes: recording the final calibration value of the on-chip clock, the final sampling count, and the number of iterations; wherein, each time the frequency signal output by the sampled clock is sampled at the output frequency of the on-chip clock, the first sampling count is recorded, and the number of iterations is incremented by 1.

[0021] In some embodiments, the on-chip clock calibration device includes an acquisition module, a first determination module, a sampling module, an adjustment module, and a second determination module.

[0022] The obtaining module is used to obtain a first frequency of the sampled clock; the first determining module is used to determine the target sampling count corresponding to the first frequency and the target frequency according to the correspondence between frequency and sampling count; the sampling module is used to sample the frequency signal output by the sampled clock at the output frequency of the on-chip clock and record the first sampling count; the adjusting module is used to adjust the calibration value of the on-chip clock and resample the frequency signal output by the sampled clock at the output frequency of the on-chip clock when the absolute value of the difference between the first sampling count and the target sampling count is greater than a preset threshold value, and record the first sampling count; the second determining module is used to confirm that the calibration of the on-chip clock is completed when the absolute value of the difference between the first sampling count and the target sampling count is less than or equal to a preset threshold value.

[0023] In some embodiments, the on-chip clock calibration apparatus includes a processor and a memory storing program instructions, the processor being configured to perform the aforementioned on-chip clock calibration method when executing the program instructions.

[0024] In some embodiments, the integrated circuit includes the aforementioned on-chip clock calibration device.

[0025] The on-chip clock calibration method, apparatus, and integrated circuit provided in this disclosure can achieve the following technical effects:

[0026] By introducing a sampled clock, the on-chip clock is used to sample and count the sampled clock (first sampling count). In this way, the target sampling count is calculated by using the first frequency of the sampled clock and the target frequency, which can be used as a standard to measure the output frequency of the on-chip clock. Then, the absolute value of the difference between the target sampling count and the first sampling count is calculated. Based on the relationship between this absolute value and a preset threshold value, the calibration value of the on-chip clock is automatically adjusted, realizing automatic calibration of the on-chip clock and improving the calibration efficiency of the on-chip clock.

[0027] The above general description and the description below are exemplary and illustrative only and are not intended to limit this application. Attached Figure Description

[0028] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrative descriptions and drawings do not constitute a limitation on the embodiments. Elements having the same reference numerals in the drawings are considered similar elements, and wherein:

[0029] Figure 1 This is a simplified diagram illustrating manual calibration.

[0030] Figure 2 This is a schematic diagram of the state transition of an on-chip clock calibration method provided in an embodiment of this application;

[0031] Figure 3 This is a schematic flowchart of an on-chip clock calibration method provided in an embodiment of this application;

[0032] Figure 4 This is a clock sampling schematic diagram provided in an embodiment of this application;

[0033] Figure 5 This is a schematic flowchart of an on-chip clock calibration method provided in an embodiment of this application;

[0034] Figure 6 This is a schematic flowchart of an on-chip clock calibration method provided in an embodiment of this application;

[0035] Figure 7This is a schematic diagram of an on-chip clock calibration device provided in an embodiment of this application;

[0036] Figure 8 This is a schematic diagram of an on-chip clock calibration device provided in an embodiment of this application. Detailed Implementation

[0037] To provide a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for illustrative purposes only and are not intended to limit the embodiments of this disclosure. In the following technical description, for ease of explanation, several details are used to provide a full understanding of the disclosed embodiments. However, one or more embodiments may still be implemented without these details. In other cases, well-known structures and devices may be simplified in their depiction to simplify the drawings.

[0038] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this disclosure described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0039] Unless otherwise stated, the term "multiple" means two or more.

[0040] In this embodiment of the disclosure, the character " / " indicates that the objects before and after it are in an "or" relationship. For example, A / B means: A or B.

[0041] The term "and / or" describes an association between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or A and B.

[0042] Figure 2 This is a schematic diagram of the state transition of an on-chip clock calibration method provided in an embodiment of this application.

[0043] like Figure 2 As shown, the calibration methods for the on-chip clock include the following states: IDLE, REDY, SAMPLE, ADJUST, and FINISH, where:

[0044] IDLE: Idle state. The chip is in this state when it is first powered on or after calibration is completed.

[0045] READY: Ready state, refers to the time required for the on-chip clock to start oscillating, which can be configured via registers.

[0046] SAMPLE: Sampling state refers to the sampling and counting of the on-chip clock using a fast clock.

[0047] ADJUST: Adjustment state refers to comparing the sampled count with the target sampled count and then adjusting the calibration value.

[0048] FINISH: The state of completion indicates that calibration is complete and the frequency of the on-chip clock output is equal to the target value.

[0049] Figure 3 This is a schematic flowchart of an on-chip clock calibration method provided in an embodiment of this application.

[0050] Combination Figure 3 As shown, the on-chip clock calibration method includes:

[0051] S301, Obtain the first frequency of the sampled clock.

[0052] The first frequency of the sampled clock is a known value.

[0053] S302. Based on the correspondence between frequency and sampling count, determine the target sampling count corresponding to the first frequency and the target frequency.

[0054] The correspondence between frequency and sampling count refers to the correspondence between the first frequency, the target frequency, and the target sampling count.

[0055] The correspondence between frequency and sampling count can be stored in the database in the form of a one-to-one correspondence data table. After obtaining the first frequency and the target frequency, the target sampling count corresponding to the first frequency and the target frequency can be obtained by querying the database.

[0056] Alternatively, the correspondence between frequency and sampling count can be pre-stored as a formula. After obtaining the first frequency and the target frequency, substituting the first frequency and the target frequency into the pre-stored formula will yield the target sampling count corresponding to the first frequency and the target frequency.

[0057] For example, the target sampling count corresponding to the first frequency and the target frequency can be determined by the following formula:

[0058]

[0059] Among them, CNT dst For the target sampling count, f dst For the target frequency, f clk This is the first frequency.

[0060] S303. Sample the frequency signal of the clock output by the sampled clock at the output frequency of the on-chip clock, and record the first sampling count.

[0061] exist Figure 2 In the SAMPLE state, this sampling step is performed.

[0062] S304. If the absolute value of the difference between the first sampling count and the target sampling count is greater than a preset threshold, adjust the calibration value of the on-chip clock, and resample the frequency signal output by the sampled clock at the output frequency of the on-chip clock, and record the first sampling count.

[0063] The purpose of adjusting the calibration value of the on-chip clock is to adjust the output frequency of the on-chip clock.

[0064] The on-chip clock calibration value can be adjusted in the following ways:

[0065] If the absolute value of the difference between the first sample count and the target sample count is greater than a preset threshold and the difference is greater than zero, the calibration value of the on-chip clock is reduced to reduce the output frequency of the on-chip clock.

[0066] If the absolute value of the difference between the first sample count and the target sample count is greater than a preset threshold and the difference is less than zero, the calibration value of the on-chip clock is increased to increase the output frequency of the on-chip clock.

[0067] In each reduction or increase of the on-chip clock calibration value, the magnitude of the reduction or increase is positively correlated with the error rate. For example, the lower the required error rate, the smaller the reduction or increase in the calibration value; conversely, the higher the required error rate, the larger the reduction or increase. Those skilled in the art can determine the appropriate reduction or increase in the calibration value based on the required error rate.

[0068] Both the magnitude of decreasing and increasing the calibration value can be configured via registers.

[0069] exist Figure 2 In the ADJUST state, the step of adjusting the calibration value of the on-chip clock is executed. After adjusting the calibration value of the on-chip clock, it enters the READY state to restart the on-chip clock, and then enters the SAMPLE state to execute the sampling step. Adjusting the output frequency of the on-chip clock refers to adjusting the output frequency after the on-chip clock restarts.

[0070] Further, determining the target sampling count corresponding to the first frequency and the target frequency may include: obtaining a multiplier of the target frequency when the target frequency is not within the output frequency range of the on-chip clock; and determining the target sampling count corresponding to the first frequency and the multiplier of the target frequency based on the correspondence between frequency and sampling count.

[0071] S305. If the absolute value of the difference between the first sample count and the target sample count is less than or equal to a preset threshold, confirm that the on-chip clock calibration is complete.

[0072] Those skilled in the art can set the specific value of the preset threshold according to the error rate requirements. For example, if the error rate requirement is higher, the specific value of the preset threshold will be smaller; if the error rate requirement is lower, the specific value of the preset threshold will be larger. The preset threshold value can be configured through a register.

[0073] The above steps correspond to Figure 2 The FINISH state in the system.

[0074] By introducing a sampled clock, the on-chip clock is used to sample and count the sampled clock (first sampling count). In this way, the target sampling count is calculated by using the first frequency of the sampled clock and the target frequency, which can be used as a standard to measure the output frequency of the on-chip clock. Then, the absolute value of the difference between the target sampling count and the first sampling count is calculated. Based on the relationship between this absolute value and a preset threshold value, the calibration value of the on-chip clock is automatically adjusted, realizing automatic calibration of the on-chip clock and improving the calibration efficiency of the on-chip clock.

[0075] The following provides a further explanation of how the target sampling count is obtained.

[0076] Optionally, sampling the frequency signal output by the sampled clock at the output frequency of the on-chip clock and recording the first sampling count includes: performing frequency division processing on the frequency signal output by the sampled clock to obtain a second frequency corresponding to the first frequency; the product of the first frequency and the frequency division coefficient is the second frequency; sampling the frequency signal corresponding to the second frequency at the output frequency of the on-chip clock for multiple consecutive cycles; the period is the period of the frequency signal corresponding to the second frequency.

[0077] The more cycles corresponding to the first frequency included in the aforementioned multiple consecutive cycles, the smaller the error rate and the longer the calibration time; conversely, the fewer cycles corresponding to the first frequency included in the aforementioned multiple consecutive cycles, the larger the error rate and the shorter the calibration time. Those skilled in the art can determine the appropriate frequency division coefficient and the number of multiple consecutive cycles based on the actual error rate requirements and calibration time requirements.

[0078] Correspondingly, based on the correspondence between frequency and sampling count, the target sampling count corresponding to the first frequency and the target frequency is determined, including:

[0079]

[0080] Among them, CNT dstFor target sampling count, div is the frequency division coefficient, period is the number of consecutive periods, and f dst For the target frequency, f clk This is the first frequency.

[0081] In the process of sampling the frequency signal output by the sampled clock at the output frequency of the on-chip clock, there are errors in both the first and last sampling results. Sampling the frequency signal corresponding to the second frequency at the output frequency of the on-chip clock for multiple consecutive cycles can significantly increase the sampling count, distribute the errors in the first and last sampling results evenly among more sampling results, and reduce sampling error.

[0082] Figure 4 This is a clock sampling diagram provided in an embodiment of this application, which serves as an exemplary illustration of the sampling process of the on-chip clock calibration method.

[0083] Combination Figure 4 As shown, CLK is the sampled clock with a known frequency; CLK is divided to obtain CLK_DIV, and the division factor can be configured through a register; CLK_ONCHIP is the sampling clock, output by the on-chip clock, with an unknown frequency; CLK_ONCHIP is used to sample multiple consecutive cycles of CLK_DIV, and the number of consecutive sampling cycles can also be configured through a register, that is, CLK_ONCHIP is used to count the samples of SAMPLE_VLD in the above figure; CNT is a counter.

[0084] Figure 5 This is a schematic flowchart of an on-chip clock calibration method provided in an embodiment of this application.

[0085] Combination Figure 5 As shown, the on-chip clock calibration method includes:

[0086] S501, Obtain the first frequency of the sampled clock.

[0087] S502. Based on the correspondence between frequency and sampling count, determine the target sampling count corresponding to the first frequency and the target frequency.

[0088] S503 sets the on-chip clock oscillation duration.

[0089] This setting duration is greater than or equal to the duration required for the on-chip clock to start oscillating, and can be configured via a register.

[0090] S504 samples the frequency signal of the clock output at the on-chip clock output frequency.

[0091] S505: If the absolute value of the difference between the first sample count and the target sample count is greater than a preset threshold, adjust the calibration value of the on-chip clock. Then execute S503.

[0092] S506. If the absolute value of the difference between the first sample count and the target sample count is less than or equal to a preset threshold, confirm that the on-chip clock calibration is complete.

[0093] Figure 6 This is a schematic flowchart of an on-chip clock calibration method provided in an embodiment of this application.

[0094] Combination Figure 6 As shown, the on-chip clock calibration method includes:

[0095] S601, Obtain the first frequency of the sampled clock.

[0096] S602. Based on the correspondence between frequency and sampling count, determine the target sampling count corresponding to the first frequency and the target frequency.

[0097] S603. Sample the frequency signal of the clock output by the sampled clock at the output frequency of the on-chip clock, and record the first sampling count.

[0098] S604. If the absolute value of the difference between the first sampling count and the target sampling count is greater than a preset threshold, adjust the calibration value of the on-chip clock, and resample the frequency signal output by the sampled clock at the output frequency of the on-chip clock, and record the first sampling count.

[0099] S605. If the absolute value of the difference between the first sample count and the target sample count is less than or equal to a preset threshold, confirm that the on-chip clock calibration is complete.

[0100] S606, the final calibration value of the clock on the recording, the final sample count, and the number of iterations.

[0101] Each iteration involves sampling the frequency signal of the clock output at the on-chip clock's output frequency, recording the first sampling count, and incrementing the iteration count by 1. This step corresponds to... Figure 1 The FINISH state in the chip primarily latches key signals during the iterative calibration process: completion flag, alarm flag indicating that the on-chip clock output frequency exceeds the specified range, final calibration value, final sample count value, and number of iterations.

[0102] Figure 7 This is a schematic diagram of an on-chip clock calibration device provided in an embodiment of this application.

[0103] Combination Figure 7As shown, the on-chip clock calibration device includes an acquisition module 71, a first determination module 72, a sampling module 73, an adjustment module 74, and a second determination module 75.

[0104] The acquisition module 71 is used to acquire the first frequency of the sampled clock.

[0105] The first determining module 72 is used to determine the target sampling count corresponding to the first frequency and the target frequency based on the correspondence between frequency and sampling count.

[0106] The sampling module 73 is used to sample the frequency signal of the clock output at the output frequency of the on-chip clock and record the first sampling count.

[0107] The adjustment module 74 is used to adjust the calibration value of the on-chip clock when the absolute value of the difference between the first sampling count and the target sampling count is greater than a preset threshold value, and to resample the frequency signal output by the sampled clock at the output frequency of the on-chip clock, and record the first sampling count.

[0108] The second determining module 75 is used to confirm the completion of on-chip clock calibration if the absolute value of the difference between the first sampling count and the target sampling count is less than or equal to a preset threshold value.

[0109] Optionally, the first determining module 72 is specifically used to determine the target sampling count corresponding to the first frequency and the target frequency in the following manner:

[0110]

[0111] Among them, CNT dst For the target sampling count, f dst For the target frequency, f clk This is the first frequency.

[0112] Optionally, the sampling module 73 includes a frequency division unit and a sampling unit; the frequency division unit is used to perform frequency division processing on the frequency signal output by the sampled clock to obtain a second frequency corresponding to the first frequency; the product of the first frequency and the frequency division coefficient is the second frequency; the sampling unit is used to sample the frequency signal corresponding to the second frequency for multiple consecutive cycles at the output frequency of the on-chip clock; the period is the period of the frequency signal corresponding to the second frequency.

[0113] Correspondingly, the first determining module 72 is specifically used to determine the target sampling count corresponding to the first frequency and the target frequency in the following manner:

[0114]

[0115] Among them, CNT dstFor target sampling count, div is the frequency division coefficient, period is the number of consecutive periods, and f dst For the target frequency, f clk This is the first frequency.

[0116] Optionally, the first determining module 72 includes:

[0117] The acquisition unit is used to obtain a multiple of the target frequency when the target frequency is not within the output frequency range of the on-chip clock.

[0118] The determining unit is used to determine the target sampling count corresponding to the first frequency and the harmonic of the target frequency based on the correspondence between frequency and sampling count.

[0119] Optionally, the adjustment module 74 includes a reduction unit and an increase unit; the reduction unit is used to reduce the calibration value of the on-chip clock to reduce the output frequency of the on-chip clock when the absolute value of the difference between the first sample count and the target sample count is greater than a preset threshold value and the difference is greater than zero; the increase unit is used to increase the calibration value of the on-chip clock to increase the output frequency of the on-chip clock when the absolute value of the difference between the first sample count and the target sample count is greater than a preset threshold value and the difference is less than zero.

[0120] Optionally, the sampling module 73 is used to first start the on-chip clock to oscillate for a set duration, and then sample the frequency signal output by the clock being sampled using the output frequency of the on-chip clock.

[0121] Optionally, the on-chip clock calibration device further includes a recording module, which records the final calibration value of the on-chip clock, the final sampling count, and the number of iterations; wherein, each time it is repeated, the frequency signal output by the sampled clock is sampled at the output frequency of the on-chip clock, and the first sampling count is recorded, and the number of iterations is incremented by 1.

[0122] In some embodiments, the on-chip clock calibration apparatus includes a processor and a memory storing program instructions, wherein the processor is configured to execute the on-chip clock calibration method provided in the foregoing embodiments when executing the program instructions.

[0123] like Figure 8 As shown, this disclosure provides an on-chip clock calibration device, which includes:

[0124] The processor 81 and memory 82 may also include a communication interface 83 and a bus 84. The processor 81, communication interface 83, and memory 82 can communicate with each other via the bus 84. The communication interface 83 can be used for information transmission. The processor 81 can call logic instructions in the memory 82 to execute the on-chip clock calibration method provided in the foregoing embodiments.

[0125] Furthermore, the logic instructions in the aforementioned memory 82 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium.

[0126] The memory 82, as a computer-readable storage medium, can be used to store software programs and computer-executable programs, such as program instructions / modules corresponding to the methods in the embodiments of this disclosure. The processor 81 executes functional applications and data processing by running the software programs, instructions, and modules stored in the memory 82, thereby implementing the methods in the above-described method embodiments.

[0127] The memory 82 may include a program storage area and a data storage area. The program storage area may store the operating system and application programs required for at least one function; the data storage area may store data created based on the use of the terminal device. Furthermore, the memory 82 may include high-speed random access memory and may also include non-volatile memory.

[0128] This disclosure provides an integrated circuit that includes the on-chip clock calibration device provided in the foregoing embodiments.

[0129] This disclosure provides a computer-readable storage medium storing computer-executable instructions configured to perform the on-chip clock calibration method provided in the foregoing embodiments.

[0130] This disclosure provides a computer program product, which includes a computer program stored on a computer-readable storage medium. The computer program includes program instructions that, when executed by a computer, cause the computer to perform the on-chip clock calibration method provided in the foregoing embodiments.

[0131] The aforementioned computer-readable storage medium may be a transient computer-readable storage medium or a non-transitory computer-readable storage medium.

[0132] The technical solutions of this disclosure can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes one or more instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods in this disclosure. The aforementioned storage medium can be a non-transitory storage medium, including: USB flash drive, portable hard drive, read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk, and other media capable of storing program code; it can also be a transient storage medium.

[0133] The foregoing description and accompanying drawings fully illustrate embodiments of this disclosure to enable those skilled in the art to practice them. Other embodiments may include structural, logical, electrical, procedural, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the order of operations may vary. Parts and features of some embodiments may be included in or replace parts and features of other embodiments. Moreover, the terminology used in this application is for describing embodiments only and is not intended to limit the claims. As used in the description of embodiments and claims, the singular forms “a,” “an,” and “the” are intended to equally include the plural forms unless the context clearly indicates otherwise. Additionally, when used in this application, the terms “comprise” and its variations “comprises” and / or “comprising” refer to the presence of stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Unless otherwise specified, an element defined by the phrase "comprising a..." does not exclude the presence of other identical elements in the process, method, or apparatus that includes that element. In this document, each embodiment may focus on describing the differences from other embodiments, and similar or identical parts between embodiments can be referred to mutually. For methods, products, etc., disclosed in the embodiments, if they correspond to the method section disclosed in the embodiments, then the relevant parts can be referred to the description of the method section.

[0134] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of this disclosure. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0135] The methods and products (including but not limited to devices and equipment) disclosed in the embodiments herein can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of units may be merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms. Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units may be selected to implement this embodiment according to actual needs. Furthermore, the functional units in the embodiments of this disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0136] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code, which contains one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. Each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

Claims

1. A calibration method for an on-chip clock, characterized in that, include: Obtain the first frequency of the sampled clock; Based on the correspondence between frequency and sampling count, determine the target sampling count corresponding to the first frequency and the target frequency; The frequency signal output by the sampled clock is sampled at the output frequency of the on-chip clock, and the first sampling count is recorded; If the absolute value of the difference between the first sampling count and the target sampling count is greater than a preset threshold, the calibration value of the on-chip clock is adjusted, and the frequency signal output by the sampled clock is resampled at the output frequency of the on-chip clock, and the first sampling count is recorded. If the absolute value of the difference between the first sampling count and the target sampling count is less than or equal to a preset threshold, the calibration of the on-chip clock is confirmed to be complete. The process of sampling the frequency signal output by the sampled clock at the output frequency of the on-chip clock and recording a first sampling count includes: performing frequency division processing on the frequency signal output by the sampled clock to obtain a second frequency corresponding to the first frequency; the product of the first frequency and the frequency division coefficient is the second frequency; sampling the frequency signal corresponding to the second frequency at the output frequency of the on-chip clock for multiple consecutive cycles; the cycle is the period of the frequency signal corresponding to the second frequency. Correspondingly, based on the correspondence between frequency and sampling count, the target sampling count corresponding to the first frequency and the target frequency is determined, including: in, For target sampling count, For frequency division coefficients, The number of consecutive periods, For the target frequency, This is the first frequency.

2. The calibration method according to claim 1, characterized in that, Based on the correspondence between frequency and sampling count, the target sampling count corresponding to the first frequency and the target frequency is determined, further including: in, For target sampling count, For the target frequency, This is the first frequency.

3. The calibration method according to claim 1, characterized in that, Determining the target sampling count corresponding to the first frequency and the target frequency includes: When the target frequency is not within the output frequency range of the on-chip clock, a multiple of the target frequency is obtained; Based on the correspondence between frequency and sampling count, the target sampling count corresponding to the first frequency and the harmonic of the target frequency is determined.

4. The calibration method according to claim 1, characterized in that, Adjusting the calibration value of the on-chip clock includes: If the absolute value of the difference between the first sample count and the target sample count is greater than a preset threshold and the difference is greater than zero, the calibration value of the on-chip clock is reduced to reduce the output frequency of the on-chip clock. If the absolute value of the difference between the first sampling count and the target sampling count is greater than a preset threshold and the difference is less than zero, the calibration value of the on-chip clock is increased to increase the output frequency of the on-chip clock.

5. The calibration method according to any one of claims 1 to 4, characterized in that, Each time the frequency signal of the sampled clock is sampled at the output frequency of the on-chip clock, the on-chip clock is first set to start oscillating for a set duration, and then the frequency signal of the sampled clock is sampled at the output frequency of the on-chip clock.

6. The calibration method according to any one of claims 1 to 4, characterized in that, After confirming the completion of the on-chip clock calibration, the process also includes: Record the final calibration value, final sample count, and number of iterations of the on-chip clock; Each time the process is repeated, the frequency signal of the clock output is sampled at the output frequency of the on-chip clock, and the first sampling count is recorded. The iteration count is incremented by 1.

7. A calibration device for an on-chip clock, characterized in that, include: The acquisition module is used to obtain the first frequency of the sampled clock. The first determining module is used to determine the target sampling count corresponding to the first frequency and the target frequency based on the correspondence between frequency and sampling count. The sampling module is used to sample the frequency signal output by the sampled clock at the output frequency of the on-chip clock and record the first sampling count; The adjustment module is used to adjust the calibration value of the on-chip clock when the absolute value of the difference between the first sampling count and the target sampling count is greater than a preset threshold value, and to resample the frequency signal output by the sampled clock at the output frequency of the on-chip clock, and record the first sampling count. The second determining module is used to confirm that the calibration of the on-chip clock is completed when the absolute value of the difference between the first sampling count and the target sampling count is less than or equal to a preset threshold value. The process of sampling the frequency signal output by the sampled clock at the output frequency of the on-chip clock and recording a first sampling count includes: performing frequency division processing on the frequency signal output by the sampled clock to obtain a second frequency corresponding to the first frequency; the product of the first frequency and the frequency division coefficient is the second frequency; sampling the frequency signal corresponding to the second frequency at the output frequency of the on-chip clock for multiple consecutive cycles; the cycle is the period of the frequency signal corresponding to the second frequency. Correspondingly, based on the correspondence between frequency and sampling count, the target sampling count corresponding to the first frequency and the target frequency is determined, including: in, For target sampling count, For frequency division coefficients, The number of consecutive periods, For the target frequency, This is the first frequency.

8. A calibration device for an on-chip clock, comprising a processor and a memory storing program instructions, characterized in that, The processor is configured to perform the on-chip clock calibration method as described in any one of claims 1 to 6 when executing the program instructions.

9. An integrated circuit, characterized in that, Includes the on-chip clock calibration device as described in claim 7 or 8.

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