Memory controller and memory chip

Abstract

The application discloses a storage controller and a storage chip, the storage controller comprising a memory, a controller and a control register group, the controller taking out instructions from the memory by executing a transfer type instruction, decoding and executing the taken instructions to obtain execution data, and writing the generated corresponding execution data into the control register group through a bit operation type instruction, then the control register group can perform read, erase and write operations on the storage unit according to the execution data and in combination with an analog circuit and / or a hardware logic circuit, in this process, the controller can only use two types of instructions and does not need to perform corresponding data operation, not only reducing the instruction type, but also reducing the running load of the controller, and the running efficiency of the controller can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of storage, in particular to a storage controller and a storage chip. BACKGROUND

[0002] In the prior art, the controller of the storage chip usually realizes the read, write and erase operations through a special circuit. However, the algorithm based on the special circuit is fixed, and if the algorithm needs to be changed, the corresponding special circuit needs to be adjusted. Therefore, it is inconvenient to upgrade the read-erase-write algorithm and the storage capacity.

[0003] In addition, the controller of the storage chip in the prior art needs to operate data, that is, data transmission, arithmetic operation and logical operation. Correspondingly, data transmission instructions, arithmetic operation instructions and logical operation instructions need to be set, which increases the running load of the controller and the types of instructions.

[0004] It should be noted that the above introduction about the background technology is only for the convenience of clearly and completely understanding the technical solutions of the present application. Therefore, the technical solutions involved above cannot be considered as known to those skilled in the art only because they appear in the background of the present application. SUMMARY

[0005] The present application provides a storage controller and a storage chip to alleviate the technical problem that the storage controller needs to operate data, resulting in more types of instructions and increased running load.

[0006] In a first aspect, the present application provides a storage controller, which includes a memory, a controller and a control register group. The memory is used to store an instruction set, and the instruction set includes a transfer instruction and a bit operation instruction. The controller is electrically connected with the memory and is used to call, decode and execute at least one instruction in the instruction set to generate corresponding execution data. The control register group is electrically connected with the controller and is used to store and control the read-erase-write operation of at least one storage unit according to the execution data.

[0007] In some embodiments, the control register group includes a read control register, which is electrically connected with the controller and is used to control the read operation of at least one storage unit.

[0008] In some embodiments, the read control register includes a read enable operation bit, a read voltage enable operation bit, a read preparation end operation bit, a read pre-processing operation bit, and a read unit control bit, the read enable operation bit is used to control whether to perform a read operation; the read voltage enable operation bit is used to control whether to enable a read voltage of the at least one memory cell; the read preparation end operation bit is used to control whether to end a read preparation operation of the at least one memory cell; the read pre-processing operation bit is used to control whether to perform a read pre-processing operation of the at least one memory cell; and the read unit control bit is used to control whether to perform a read operation on the memory cell.

[0009] In some embodiments, the control register group includes a write control register, the write control register is electrically connected to the controller, and the write control register is used to control a write operation of the at least one memory cell.

[0010] In some embodiments, the write control register includes a write enable operation bit, a write voltage enable operation bit, a write preparation end operation bit, a write pre-processing operation bit, a write unit control bit, a first program state enable bit, a second program state enable bit, and a third program state enable bit, the write enable operation bit is used to control whether to perform a write operation; the write voltage enable operation bit is used to control whether to enable a write voltage of the at least one memory cell; the write preparation end operation bit is used to control whether to end a write preparation operation of the at least one memory cell; the write pre-processing operation bit is used to control whether to perform a write pre-processing operation of the at least one memory cell; the write unit control bit is used to control whether to perform a write operation on the memory cell; the first program state enable bit is used to control whether to perform a first program state; the second program state enable bit is used to control whether to perform a second program state; and the third program state enable bit is used to control whether to perform a third program state.

[0011] In some embodiments, the control register group includes an erase control register, the erase control register is electrically connected to the controller, and the erase control register is used to control an erase operation of the at least one memory cell.

[0012] In some embodiments, the erase control register includes an erase enable operation bit, an erase voltage enable operation bit, an erase preparation end operation bit, an erase pre-treatment operation bit, an erase unit control bit, a first erase state enable bit, a second erase state enable bit, and a third erase state enable bit, the erase enable operation bit is used to control whether to perform an erase operation, the erase voltage enable operation bit is used to control whether to enable an erase voltage of the at least one memory cell, the erase preparation end operation bit is used to control whether to end an erase preparation operation of the at least one memory cell, the erase pre-treatment operation bit is used to control whether to perform an erase pre-treatment operation of the at least one memory cell, the erase unit control bit is used to control whether to perform an erase operation on the memory cell, the first erase state enable bit is used to control whether to perform a first erase state, the second erase state enable bit is used to control whether to perform a second erase state, and the third erase state enable bit is used to control whether to perform a third erase state.

[0013] In some embodiments, the control register group includes an over-erase correction control register, the over-erase correction control register is electrically connected to the controller, and the over-erase correction control register is used to control an over-erase correction operation of the at least one memory cell.

[0014] In some embodiments, the over-erase correction control register includes an over-erase correction enable operation bit, an over-erase correction voltage enable operation bit, an over-erase correction preparation end operation bit, an over-erase correction pre-treatment operation bit, an over-erase correction unit control bit, a first over-erase correction state enable bit, a second over-erase correction state enable bit, and a third over-erase correction state enable bit, the over-erase correction enable operation bit is used to control whether to perform an over-erase correction operation, the over-erase correction voltage enable operation bit is used to control whether to enable an over-erase correction voltage of the at least one memory cell, the over-erase correction preparation end operation bit is used to control whether to end an over-erase correction preparation operation of the at least one memory cell, the over-erase correction pre-treatment operation bit is used to control whether to perform an over-erase correction pre-treatment operation of the at least one memory cell, the over-erase correction unit control bit is used to control whether to perform an over-erase correction operation on the memory cell, the first over-erase correction state enable bit is used to control whether to perform a first over-erase correction state, the second over-erase correction state enable bit is used to control whether to perform a second over-erase correction state, and the third over-erase correction state enable bit is used to control whether to perform a third over-erase correction state.

[0015] In some embodiments, the memory controller further includes a state register, the state register is electrically connected to the controller, and the state register is used to indicate a current operation area and / or an operation type.

[0016] In some embodiments, the state register includes an over-erase operation indication bit, a write operation indication bit, an erase operation indication bit, a read operation indication bit, a waiting operation indication bit, a whole area operation indication bit, a sector operation indication bit, and a block area operation indication bit, the over-erase operation indication bit is used to indicate whether the specified area is in an over-erase correction operation; the write operation indication bit is used to indicate whether the specified area is in a write operation; the erase operation indication bit is used to indicate whether the specified area is in an erase operation; the read operation indication bit is used to indicate whether it is in a read operation; the waiting operation indication bit is used to indicate whether it is in a waiting operation; the whole area operation indication bit is used to indicate whether it is in a whole area operation; the sector operation indication bit is used to indicate whether it is in a sector operation; and the block area operation indication bit is used to indicate whether it is in a block area operation.

[0017] In some embodiments, each transfer class instruction includes an operation code of 6 bits and an indication address of 8 bits; and each bit operation class instruction includes an operation code of 6 bits and register bit selection data of 8 bits.

[0018] In some embodiments, the operation code of 6 bits includes a main operation code of 3 bits and a sub-operation code of 3 bits.

[0019] In a second aspect, the present application provides a storage chip, which includes the storage controller in at least one of the above embodiments.

[0020] The storage controller and the storage chip provided by the present application can take out instructions from the memory by executing the transfer class instructions, decode and execute the taken instructions to obtain execution data, and then write the generated corresponding execution data into the control register group through the bit operation class instructions. Then, the control register group can perform read, erase and write operations on the storage unit according to the execution data and in combination with the analog circuit and / or the hardware logic circuit. In this process, the controller can only use two types of instructions and does not need to perform corresponding data operations, which not only reduces the types of instructions, but also reduces the running load of the controller, thereby improving the running efficiency of the controller. Meanwhile, the present application can realize the read, erase and write operations on the storage unit on the basis of the execution of the instruction set by the controller and in combination with the control register group, which can at least partially replace or even completely replace the use of the special circuit in the traditional technical solution, thereby facilitating the upgrading of the software algorithm and the storage capacity.

[0021] In addition, based on the architecture of the present application, the control register group is used to assist the memory operation, which can be further realized through the hardware logic circuit or through the software algorithm in subsequent read, write and erase operations, thereby providing convenience and possibility for subsequent memory function development. BRIEF DESCRIPTION OF DRAWINGS

[0022] The technical solution and other beneficial effects of the present invention will become apparent from the following detailed description of specific embodiments of the invention, in conjunction with the accompanying drawings.

[0023] Figure 1 This is a schematic diagram of the structure of a storage controller provided in an embodiment of the present invention.

[0024] Figure 2 for Figure 1 The diagram shows the structure of the read control register.

[0025] Figure 3 for Figure 1 The diagram shows the structure of the write control register.

[0026] Figure 4 for Figure 1 The diagram shows the structure of the erase control register.

[0027] Figure 5 for Figure 1 The diagram shows the structure of the over-erasure correction control register.

[0028] Figure 6 for Figure 1 The diagram shows the structure of the status register. Detailed Implementation

[0029] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0030] In view of the aforementioned technical problems of increased instruction types and operational load in storage controllers due to the need for data computation, this embodiment provides a storage controller. Please refer to [link to relevant documentation]. Figures 1 to 6 ,like Figure 1 As shown, the storage controller includes a memory 100, a controller 200, and a control register set 300. The memory 100 stores an instruction set, which includes transfer instructions and bit manipulation instructions. The controller 200 is electrically connected to the memory 100 and is used to call, decode, and execute at least one instruction from the instruction set to generate corresponding execution data. The control register set 300 is electrically connected to the controller 200 and is used to store and control read, erase, and write operations of at least one memory unit based on the execution data. Preferably, the memory 100 is a read-only memory.

[0031] It can be understood that the storage controller provided by the embodiment controls the controller 200 to fetch instructions from the storage 100 by executing the transfer type instruction, decodes and executes the fetched instructions to obtain execution data, and writes the generated corresponding execution data into the control register group 300 through the bit operation type instruction. Then, the control register group 300 can perform read, erase and write operations on the storage unit according to the execution data and in combination with the analog circuit and / or hardware logic circuit. In this process, the controller 200 can only use two types of instructions and does not need to perform corresponding data operations, thereby reducing the types of instructions and the running load of the controller 200, improving the running efficiency of the controller 200; at the same time, the application can realize the read, erase and write operations on the storage unit on the basis of the execution of the instruction set by the controller 200, in combination with the control register group 300, avoiding the use of special circuits in the prior art, and facilitating the upgrading of software algorithms and storage capacity.

[0032] It should be noted that the read, erase and write operation can include at least one of a read operation, a write operation, an erase operation and an over-erase correction operation. The read operation can be a read operation implemented by the storage controller on at least one storage unit. The write operation can be a write operation implemented by the storage controller on at least one storage unit. The erase operation can be an erase operation implemented by the storage controller on at least one storage unit. The over-erase correction operation can be an over-erase correction process implemented by the storage controller on at least one storage unit.

[0033] The transfer type instruction can be a control program transfer type instruction, which can include an unconditional transfer type instruction and a conditional transfer type instruction. The bit operation type instruction can include a set bit instruction and a clear bit instruction. The set bit instruction can be used to set one or more bits of a register. The clear bit instruction can be used to clear one or more bits of a register. In this way, the code value on the corresponding bit of each register can be cleared or set. When there is a time interval between the execution of the transfer type instruction and / or the bit operation type instruction, the above instruction set can be appropriately configured with a waiting instruction for performing a waiting operation to transition through the time interval. It can be understood that the waiting instruction is not necessary.

[0034] Specifically, as shown in Table 1-1, "opcode(6bit)" is used to represent the operation code of 6 bits in the control program transfer type instruction or the bit operation type instruction, "instruction address(8bit)" is used to represent the instruction address of 8 bits in the control program transfer type instruction, and "bit-register(8bit)" is used to represent the register bit selection data of 8 bits.

[0035] Wherein, as shown in Table 1-2 and Table 1-3, the 6-bit operation code in Table 1-1 can be further divided into a 3-bit main operation code "opcode 3bit" and a 3-bit sub-operation code "sub-opcode 3bit". The "flag register bit" in Table 1-2 can be specifically represented as the three combined bits corresponding to the third to tenth rows in the second column of Table 1-3, which correspond to different conditional jump instructions in turn. The "address of control register" in the fourth row of Table 1-2 can be specifically represented as the three combined bits corresponding to the eleventh to fourteenth rows in the second column of Table 1-3, each of which can determine a bit of a register, and then set the bit through the main operation code. The "address of control register" in the fifth row of Table 1-2 can be specifically represented as the three combined bits corresponding to the fifteenth to eighteenth rows in the second column of Table 1-3, each of which can determine a bit of a register, and then clear the bit through the main operation code. In this way, the bit values of the registers can be operated through the custom instruction set shown in Table 1-2 or Table 1-3, and then the read, erase and write operations of the storage unit can be realized through the hardware logic circuit, and the read, erase and write operations of the storage unit can also be realized through the software algorithm, which provides convenience and possibility for the subsequent development of memory functions.

[0036] Since the present patent only uses four control registers to control subsequent read, write, erase and over-erase correction operations, the hardware structure is simplified, and a simplified instruction set is used in cooperation with the four control registers, which only includes transfer type and bit operation type instructions, and the control program transfer type instruction or the bit operation type instruction only uses a 6-bit operation code to indicate the main operation of the memory, which also reduces the program running pressure.

[0037] Table 1-1

[0038] opcode (6 bit) instruction address (8 bit) opcode (6 bit) bit-register (8 bit)

[0039] Table 1-2

[0040]

[0041]

[0042] Table 1-3

[0043]

[0044]

[0045] Wherein, the controller 200 can further include a compiler, which can convert various types of instructions into corresponding machine codes, for example, assembly instructions can be converted into machine codes that the controller 200 can recognize.

[0046] Specifically, the controller 200 can be a microcontroller chip, a central processing chip, a digital processing chip, an off-the-shelf programmable logic array, an off-the-shelf programmable logic device, etc.

[0047] In one embodiment, the control register group 300 includes a read control register 310, which is electrically connected to the controller 200 and is used to control the read operation of at least one memory cell.

[0048] In one embodiment, the control register group 300 further includes a write control register 320, which is electrically connected to the controller 200 and is used to control write operations of at least one memory cell.

[0049] In one embodiment, the control register group 300 further includes an erase control register 330, which is electrically connected to the controller 200 and is used to control the erase operation of at least one memory cell.

[0050] In one embodiment, the control register group 300 further includes an over-erasure correction control register 340, which is electrically connected to the controller 200 and is used to control the over-erasure correction operation of at least one memory cell.

[0051] In one embodiment, the storage controller further includes a status register 400, which is electrically connected to the controller 200. The status register 400 is used to indicate the current operating region and / or operating type. The operating region can be divided into a whole region, a sector, and a block region. A whole region represents the entire storage area of ​​a storage chip, a sector represents one or more sectors of a storage chip, and a block region represents one or more storage block regions of a storage chip.

[0052] like Figure 2 As shown, in one embodiment, the read control register 310 includes a read enable bit, a read voltage start bit, a read preparation end bit, a read preprocessing bit, and a read unit control bit. The read enable bit controls whether a read operation is performed; the read voltage start bit controls whether to start the read voltage of at least one memory cell; the read preparation end bit controls whether to end the read preparation operation of at least one memory cell; the read preprocessing bit controls whether to perform a read preprocessing operation of at least one memory cell; and the read unit control bit controls whether to perform a read operation on the memory cell.

[0053] For example, the capacity of the read control register 310 can be at least 5 bits, preferably generally 8 bits, the 0th bit can be a read enable operation bit M_RDr, when it is 1, it indicates that the read operation of at least one memory cell is allowed; when it is 0, it indicates that the read operation of at least one memory cell is prohibited. The 1st bit can be a read voltage start operation bit M_PUMPr, when it is 1, it indicates that the read voltage of at least one memory cell is allowed to start; when it is 0, it indicates that the read voltage of at least one memory cell is prohibited to start. The 2nd bit can be a read preparation end operation bit M_DISCHr, when it is 1, it indicates that the read preparation operation of at least one memory cell is allowed to end; when it is 0, it indicates that the read preparation operation of at least one memory cell is prohibited to end. The 3rd bit can be a read preprocessing operation bit M_PREr, when it is 1, it indicates that the read preprocessing operation of at least one memory cell is allowed to perform; when it is 0, it indicates that the read preprocessing operation of at least one memory cell is prohibited to perform. The 4th bit can be a read unit control bit M_CHARGEr, when it is 1, it indicates that the read operation of the memory cell is allowed; when it is 0, it indicates that the read operation of the memory cell is prohibited. The 5th to 7th bits are temporarily reserved (Reserved), optionally, the user can define the function of the 5th to 7th bits by himself.

[0054] It can be understood that based on the embodiment, the read operation of at least one memory cell can be realized.

[0055] As shown in Figure 3 In one embodiment, the write control register 320 includes a write enable operation bit, a write voltage start operation bit, a write preparation end operation bit, a write preprocessing operation bit, a write unit control bit, a first programming state enable bit, a second programming state enable bit, and a third programming state enable bit. The write enable operation bit is used to control whether to perform the write operation of at least one memory cell; the write voltage start operation bit is used to control whether to start the write voltage of at least one memory cell; the write preparation end operation bit is used to control whether to end the write preparation operation of at least one memory cell; the write preprocessing operation bit is used to control whether to perform the write preprocessing operation of at least one memory cell; the write unit control bit is used to control whether to perform the write operation of the memory cell; the first programming state enable bit is used to control whether to perform the first programming state; the second programming state enable bit is used to control whether to perform the second programming state; and the third programming state enable bit is used to control whether to perform the third programming state.

[0056] For example, the write control register 320 can have a capacity of at least 8 bits. Bit 0 can be a write enable bit P_RDr, which, when 1, indicates that a write operation on at least one memory cell is allowed; when 0, it indicates that a write operation on at least one memory cell is prohibited. Bit 1 can be a write voltage enable bit P_PUMPr, which, when 1, indicates that a write voltage on at least one memory cell is allowed; when 0, it indicates that a write voltage on at least one memory cell is prohibited. Bit 2 can be a write preparation end bit P_DISCHr, which, when 1, indicates that a write preparation operation on at least one memory cell is allowed to end; when 0, it indicates that a write preparation operation on at least one memory cell is prohibited. Bit 3 can be a write preprocessing bit P_PREr, which, when 1, indicates that a write preprocessing operation on at least one memory cell is allowed; when 0, it indicates that a write preprocessing operation on at least one memory cell is prohibited. Bit 4 can be the write unit control bit P_CHARGEr. When it is 1, write operations to the memory unit are allowed; when it is 0, write operations to the memory unit are prohibited. Bit 5 can be the first programming state enable bit P_ST2. When it is 1, the first programming state is allowed; when it is 0, the first programming state is prohibited. Bit 6 can be the second programming state enable bit P_ST1. When it is 1, the second programming state is allowed; when it is 0, the second programming state is prohibited. Bit 7 can be the third programming state enable bit P_ST0. When it is 1, the third programming state is allowed; when it is 0, the third programming state is prohibited.

[0057] It is understood that, based on this embodiment, a write operation on at least one storage unit can be implemented.

[0058] like Figure 4 As shown, in one embodiment, the erase control register 330 includes an erase enable bit, an erase voltage start bit, an erase preparation end bit, an erase preprocessing bit, an erase unit control bit, a first erase state enable bit, a second erase state enable bit, and a third erase state enable bit. The erase enable bit controls whether to perform an erase operation; the erase voltage start bit controls whether to start the erase voltage of at least one memory cell; the erase preparation end bit controls whether to end the erase preparation operation of at least one memory cell; the erase preprocessing bit controls whether to perform an erase preprocessing operation of at least one memory cell; the erase unit control bit controls whether to perform an erase operation on the memory cell; the first erase state enable bit controls whether to perform a first erase state; the second erase state enable bit controls whether to perform a second erase state; and the third erase state enable bit controls whether to perform a third erase state.

[0059] For example, the capacity of the erase control register 330 can be at least 8 bits (bits), the 0th bit can be an erase enable operation bit E_RDr, when it is 1, it indicates that at least one storage unit is allowed to perform an erase operation; when it is 0, it indicates that at least one storage unit is prohibited to perform an erase operation. The 1st bit can be an erase voltage start operation bit E_PUMPr, when it is 1, it indicates that at least one storage unit is allowed to start an erase voltage; when it is 0, it indicates that at least one storage unit is prohibited to start an erase voltage. The 2nd bit can be an erase preparation end operation bit E_DISCHr, when it is 1, it indicates that at least one storage unit is allowed to end an erase preparation operation; when it is 0, it indicates that at least one storage unit is prohibited to end an erase preparation operation. The 3rd bit can be an erase preprocessing operation bit E_PREr, when it is 1, it indicates that at least one storage unit is allowed to perform an erase preprocessing operation; when it is 0, it indicates that at least one storage unit is prohibited to perform an erase preprocessing operation. The 4th bit can be an erase unit control bit E_CHARGEr, when it is 1, it indicates that at least one storage unit is allowed to perform an erase operation; when it is 0, it indicates that at least one storage unit is prohibited to perform an erase operation. The 5th bit can be a first erase state enable bit E_ST2, when it is 1, it indicates that at least one storage unit is allowed to perform a first erase state; when it is 0, it indicates that at least one storage unit is prohibited to perform a first erase state. The 6th bit can be a second erase state enable bit E_ST1, when it is 1, it indicates that at least one storage unit is allowed to perform a second erase state; when it is 0, it indicates that at least one storage unit is prohibited to perform a second erase state. The 7th bit can be a third erase state enable bit E_ST0, when it is 1, it indicates that at least one storage unit is allowed to perform a third erase state; when it is 0, it indicates that at least one storage unit is prohibited to perform a third erase state.

[0060] It can be understood that based on the embodiment, an erase operation on at least one storage unit can be implemented.

[0061] As Figure 5As shown, in one embodiment, the over-erase correction control register 340 includes an over-erase correction enable operation bit, an over-erase correction voltage enable operation bit, an over-erase correction preparation end operation bit, an over-erase correction pre-processing operation bit, an over-erase correction unit control bit, a first over-erase correction state enable bit, a second over-erase correction state enable bit, and a third over-erase correction state enable bit. The over-erase correction enable operation bit is used to control whether to perform an over-erase correction operation. The over-erase correction voltage enable operation bit is used to control whether to enable an over-erase correction voltage of at least one memory cell. The over-erase correction preparation end operation bit is used to control whether to end an over-erase correction preparation operation of at least one memory cell. The over-erase correction pre-processing operation bit is used to control whether to perform an over-erase correction pre-processing operation of at least one memory cell. The over-erase correction unit control bit is used to control whether to perform an over-erase correction operation on a memory cell. The first over-erase correction state enable bit is used to control whether to perform a first over-erase correction state. The second over-erase correction state enable bit is used to control whether to perform a second over-erase correction state. The third over-erase correction state enable bit is used to control whether to perform a third over-erase correction state.

[0062] For example, the capacity of the over-erase correction control register 340 can be at least 8 bits (bits), the 0th bit can be an over-erase correction enable operation bit O_RDr, when it is 1, it indicates that at least one storage unit is allowed to perform an over-erase correction operation; when it is 0, it indicates that at least one storage unit is prohibited to perform an over-erase correction operation. The 1st bit can be an over-erase correction voltage start operation bit O_PUMPr, when it is 1, it indicates that at least one storage unit is allowed to start an over-erase correction voltage; when it is 0, it indicates that at least one storage unit is prohibited to start an over-erase correction voltage. The 2nd bit can be an over-erase correction preparation end operation bit O_DISCHr, when it is 1, it indicates that at least one storage unit is allowed to end an over-erase correction preparation operation; when it is 0, it indicates that at least one storage unit is prohibited to end an over-erase correction preparation operation. The 3rd bit can be an over-erase correction preprocessing operation bit O_PREr, when it is 1, it indicates that at least one storage unit is allowed to perform an over-erase correction preprocessing operation; when it is 0, it indicates that at least one storage unit is prohibited to perform an over-erase correction preprocessing operation. The 4th bit can be an over-erase correction unit control bit O_CHARGEr, when it is 1, it indicates that at least one storage unit is allowed to perform an over-erase correction operation; when it is 0, it indicates that at least one storage unit is prohibited to perform an over-erase correction operation. The 5th bit can be a first over-erase correction state enable bit O_ST2, when it is 1, it indicates that at least one storage unit is allowed to perform a first over-erase correction state; when it is 0, it indicates that at least one storage unit is prohibited to perform a first over-erase correction state. The 6th bit can be a second over-erase correction state enable bit O_ST1, when it is 1, it indicates that at least one storage unit is allowed to perform a second over-erase correction state; when it is 0, it indicates that at least one storage unit is prohibited to perform a second over-erase correction state. The 7th bit can be a third over-erase correction state enable bit O_ST0, when it is 1, it indicates that at least one storage unit is allowed to perform a third over-erase correction state; when it is 0, it indicates that at least one storage unit is prohibited to perform a third over-erase correction state.

[0063] It can be understood that based on the present embodiment, an over-erase correction operation on at least one storage unit can be implemented.

[0064] As Figure 6As shown, in one embodiment, the status register 400 includes an over-erase operation indication bit, a write operation indication bit, an erase operation indication bit, a read operation indication bit, a waiting operation indication bit, a whole-area operation indication bit, a sector operation indication bit, and a block-area operation indication bit, the over-erase operation indication bit is used to indicate whether the specified area is in an over-erase correction operation; the write operation indication bit is used to indicate whether the specified area is in a write operation; the erase operation indication bit is used to indicate whether the specified area is in an erase operation; the read operation indication bit is used to indicate whether it is in a read operation; the waiting operation indication bit is used to indicate whether it is in a waiting operation; the whole-area operation indication bit is used to indicate whether it is in a whole-area operation; the sector operation indication bit is used to indicate whether it is in a sector operation; and the block-area operation indication bit is used to indicate whether it is in a block-area operation.

[0065] For example, the capacity of the status register 400 can be at least 8 bits (bits), the 0th bit can be an over-erase operation indication bit OECr, when it is 1, it indicates that it is in an over-erase correction operation; when it is 0, it indicates that it is not in an over-erase correction operation. The 1st bit can be a write operation indication bit PGMr, when it is 1, it indicates that the specified area is in a write operation; when it is 0, it indicates that the specified area is not in a write operation. The 2nd bit can be an erase operation indication bit ERASEr, when it is 1, it indicates that the specified area is in an erase operation; when it is 0, it indicates that the specified area is not in an erase operation. The 3rd bit can be a read operation indication bit READr, when it is 1, it indicates that it is in a read operation; when it is 0, it indicates that it is not in a read operation. The 4th bit can be a waiting operation indication bit TIMEr, when it is 1, it indicates that it is in a waiting operation; when it is 0, it indicates that it is not in a waiting operation. The 5th bit can be a whole-area operation indication bit CHIPr, when it is 1, it indicates that it is in a whole-area operation; when it is 0, it indicates that it is not in a whole-area operation. The 6th bit can be a sector operation indication bit SECTORr, when it is 1, it indicates that it is in a sector operation; when it is 0, it indicates that it is not in a sector operation. The 7th bit can be a block-area operation indication bit BLOCKr, when it is 1, it indicates that it is in a block-area operation; when it is 0, it indicates that it is not in a block-area operation.

[0066] In one embodiment, the present embodiment provides a storage chip, which includes the storage controller in at least one of the above embodiments.

[0067] It can be understood that the storage chip provided by the embodiment, the controller 200 takes out the instruction from the memory 100 by executing the transfer type instruction, decodes and executes the taken instruction to obtain execution data, and then writes the generated corresponding execution data into the control register group 300 through the bit operation type instruction. Then, the control register group 300 can perform read, erase and write operations on the storage unit according to the execution data and in combination with the analog circuit and / or the hardware logic circuit. In this process, the controller 200 can only use two types of instructions and does not need to perform corresponding data operation, which not only reduces the instruction type, but also reduces the running load of the controller 200, and can improve the running efficiency of the controller 200. At the same time, the application can realize the read, erase and write operations on the storage unit on the basis of the execution of the instruction set by the controller 200, in combination with the control register group 300. At least, the use of the special circuit in the traditional technical solution can be partially replaced or even completely replaced, which is convenient for upgrading the software algorithm and the storage capacity.

[0068] It can be understood that based on the architecture of the present application, the control register group 300 is used to assist the memory operation. In subsequent read, write and erase operations, the operation can be further realized by the hardware logic circuit or by the software algorithm, which provides convenience and possibility for subsequent memory function development. Of course, it can be understood that if the software algorithm is further used to realize the related function in the subsequent process, the operation instruction type can be increased as needed.

[0069] The storage chip can be a flash memory chip, which can be but is not limited to a Nor flash chip, and can also be other storage chips applicable to the present application.

[0070] In the above embodiments, the description of each embodiment has its own emphasis, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0071] The storage controller and the storage chip provided by the embodiments of the present application are described in detail above, and the principles and implementation manners of the present application are described by applying specific examples. The above description of the embodiments is only used to help understand the technical solutions and the core ideas of the present application; those skilled in the art should understand that the technical solutions recorded in the above embodiments can be modified, or some technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A storage controller, characterized in that, include: A memory for storing an instruction set, which includes jump instructions and bit manipulation instructions; The controller, electrically connected to the memory, is used to call, decode, and execute at least one instruction in the instruction set to generate corresponding execution data; as well as A control register group, electrically connected to the controller, is used to write the execution data based on the bit manipulation instructions, and to control the read, erase, and write operations of at least one memory unit according to the execution data.

2. The storage controller according to claim 1, characterized in that, The control register group includes a read control register, which is electrically connected to the controller and is used to control the read operation of the at least one memory unit.

3. The storage controller according to claim 2, characterized in that, The read control register includes: The read enable bit is used to control whether a read operation is performed. The read voltage start operation bit is used to control whether to start the read voltage of the at least one memory cell; The read preparation end operation bit is used to control whether to end the read preparation operation of the at least one memory cell; A read preprocessing operation bit is used to control whether to perform a read preprocessing operation on the at least one memory cell; and The read unit control bit is used to control whether to perform a read operation on the memory cell.

4. The storage controller according to claim 1, characterized in that, The control register group includes a write control register, which is electrically connected to the controller and is used to control the write operation of the at least one memory cell.

5. The storage controller according to claim 4, characterized in that, The write control register includes: The write enable bit is used to control whether a write operation is performed; Write voltage enable operation bit, used to control whether to enable the write voltage of the at least one memory cell; The write preparation end operation bit is used to control whether to end the write preparation operation of the at least one memory cell; A write preprocessing operation bit is used to control whether to perform a write preprocessing operation on the at least one memory cell; The write unit control bit is used to control whether a write operation is performed on the memory cell; The first programming state enable bit is used to control whether the first programming state is entered. The second programming state enable bit is used to control whether the second programming state is entered; and The third programming state enable bit is used to control whether the third programming state is performed.

6. The storage controller according to claim 1, characterized in that, The control register group includes an erase control register, which is electrically connected to the controller and is used to control the erase operation of the at least one memory cell.

7. The storage controller according to claim 6, characterized in that, The erase control register includes: The erase enable bit is used to control whether an erase operation is performed; The erase voltage start operation bit is used to control whether to start the erase voltage of the at least one memory cell; The erase preparation end operation bit is used to control whether to end the erase preparation operation of the at least one memory cell; The erase preprocessing operation bit is used to control whether to perform the erase preprocessing operation of the at least one memory cell; The erase unit control bit is used to control whether to perform an erase operation on the memory cell; The first erase state enable bit is used to control whether the first erase state is performed. The second erase state enable bit is used to control whether the second erase state is performed; and The third erase state enable bit is used to control whether the third erase state is performed.

8. The storage controller according to claim 1, characterized in that, The control register group includes an over-erasure correction control register, which is electrically connected to the controller and is used to control the over-erasure correction operation of the at least one memory cell.

9. The storage controller according to claim 8, characterized in that, The over-erasure correction control register includes: The over-erasure correction enable bit is used to control whether an over-erasure correction operation is performed. An over-erasure correction voltage start operation bit is used to control whether to start the over-erasure correction voltage of the at least one memory cell; The over-erasure correction preparation end operation bit is used to control whether to end the over-erasure correction preparation operation of the at least one memory cell; An over-erasure correction preprocessing operation bit is used to control whether to perform an over-erasure correction preprocessing operation on the at least one memory cell. The over-erasure correction unit control bit is used to control whether an over-erasure correction operation is performed on the memory cell; The first over-erasure correction state enable bit is used to control whether the first over-erasure correction state is performed. The second over-erasure correction state enable bit is used to control whether the second over-erasure correction state is performed. The third over-erasure correction state enable bit is used to control whether the third over-erasure correction state is performed.

10. The storage controller according to any one of claims 1 to 9, characterized in that, The storage controller also includes a status register electrically connected to the controller, the status register being used to indicate the current operating region and / or operating type.

11. The storage controller according to claim 10, characterized in that, The status register includes: The over-erasure operation indicator bit is used to indicate whether the specified area is in an over-erasure correction operation; The write operation indicator bit is used to indicate whether a specified area is in the process of being written. The erase operation indicator bit is used to indicate whether a specified area is in the process of being erased; The read operation indicator bit is used to indicate whether a read operation is in progress. The waiting operation indicator bit is used to indicate whether the operation is in a waiting state. The whole-area operation indicator bit is used to indicate whether the whole-area operation is in progress; The sector operation indicator bit is used to indicate whether a sector operation is in progress; and The block area operation indicator bit is used to indicate whether a block area operation is in progress.

12. The storage controller according to claim 1, characterized in that, Each of the transfer instructions includes a 6-bit opcode and an 8-bit address pointer; each of the bit manipulation instructions includes a 6-bit opcode and an 8-bit register bit selection data.

13. The storage controller according to claim 12, characterized in that, The 6-bit opcode includes a 3-bit main opcode and a 3-bit sub-opcode.

14. A memory chip, characterized in that, Includes the storage controller as described in any one of claims 1 to 13.

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