Write Accelerator Buffering and Hibernation

Abstract

The present application relates to write accelerator buffering and hibernation. A memory system may initiate a first operation to enter a first power mode having lower power consumption than a second power mode. In some cases, the memory system may determine whether an amount of data stored in a buffer of a single-level cell associated with write accelerator information satisfies a threshold based on initiating the first operation. The memory system may determine whether to perform a second operation to transfer the amount of data stored in the buffer of the single-level cell to a portion of a memory including multiple-level cells based on determining whether the amount of data satisfies the threshold. The memory system may enter the first power mode based on determining to perform the second operation to transfer the amount of data from the buffer to the portion of the memory.

Description

[0001] Cross Reference

[0002] This application claims priority to U.S. patent application Ser. No. 17 / 645,265, filed by PORZIO et al. on December 20, 2021, entitled “WRITE BOOSTER BUFFER AND HIBERNATE,” which is assigned to the present assignee and is expressly incorporated herein by reference. Technical Field

[0003] The technical field relates to one or more systems for memory, and more particularly, to write accelerator buffering and hibernation. Background Art

[0004] Memory devices are widely used to store information in various electronic devices, such as computers, user devices, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell can be programmed to one of two supported states, typically corresponding to a logical 1 or a logical 0. In some examples, a single memory cell can support more than two possible states, any of which can be stored by the memory cell. To access information stored by a memory device, a component can read or sense the state of one or more memory cells within the memory device. To store information, a component can write or program one or more memory cells within the memory device to a corresponding state.

[0005] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), 3-dimensional cross-point memory (3D cross-point), NOR and NAND memory devices, etc. Memory devices can be volatile or non-volatile. Unless periodically refreshed by an external power source, volatile memory cells (e.g., DRAM cells) may lose their programmed state over time. Non-volatile memory cells (e.g., NAND memory cells) can maintain their programmed state for extended periods of time even in the absence of an external power source. Summary of the Invention

[0006] A device is described. The device may include: a memory system; and a controller coupled to the memory system, wherein the controller is configured to cause the device to perform the following operations: initiating a first operation of entering a first power mode at the memory system, the first power mode having lower power consumption than a second power mode; determining whether an amount of data stored in a buffer of a single-level cell associated with write accelerator information satisfies a threshold based at least in part on initiating the first operation of entering the first power mode; determining whether to perform a second operation of transferring the amount of data stored in the buffer of the single-level cell to a portion of a memory including multi-level cells based at least in part on determining whether the amount of data satisfies the threshold; and entering the first power mode based at least in part on determining to perform the second operation of transferring the amount of data from the buffer to the portion of the memory.

[0007] A non-transitory computer-readable medium storing code is described. The code includes instructions executable by a processor to: initiate a first operation of entering a first power mode at a memory system, the first power mode having lower power consumption than a second power mode; determine whether an amount of data stored in a buffer of a single-level cell associated with write accelerator information satisfies a threshold based at least in part on initiating the first operation of entering the first power mode; determine whether to perform a second operation of transferring the amount of data stored in the buffer of the single-level cell to a portion of a memory including multiple-level cells based at least in part on determining whether the amount of data satisfies the threshold; and enter the first power mode based at least in part on determining to perform the second operation of transferring the amount of data from the buffer to the portion of the memory.

[0008] A method is described. The method includes: initiating a first operation at a memory system to enter a first power mode, the first power mode having lower power consumption than a second power mode; determining whether an amount of data stored in a buffer of a single-level cell associated with write accelerator information satisfies a threshold based at least in part on initiating the first operation to enter the first power mode; determining whether to perform a second operation to transfer the amount of data stored in the buffer of the single-level cell to a portion of a memory including multi-level cells based at least in part on determining whether the amount of data satisfies the threshold; and entering the first power mode based at least in part on determining to perform the second operation to transfer the amount of data from the buffer to the portion of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1An example of a system supporting write accelerator buffering and hibernation according to examples disclosed herein is described.

[0010] Figure 2 An example of a system supporting write accelerator buffering and hibernation according to examples disclosed herein is described.

[0011] Figure 3 An example of a flow chart illustrating support for write accelerator buffering and hibernation according to examples disclosed herein.

[0012] Figure 4 A block diagram is shown of a memory system supporting write accelerator buffering and hibernation according to examples disclosed herein.

[0013] Figure 5 A flow chart illustrating one or more methods of supporting write accelerator buffering and hibernation according to examples disclosed herein is shown. DETAILED DESCRIPTION

[0014] Some memory systems may include a write accelerator mode. Write accelerator mode may allow the memory system to write information faster than in normal mode (e.g., non-write accelerator mode). During write accelerator mode, the memory system may write data to the single-level cell (SLC) portion of the memory and then, at a later time, move the data to the triple-level cell (TLC) portion of the memory as part of a background operation. In some cases, the SLC portion of the memory may be an example of a write accelerator buffer. During normal mode, the memory system may write data directly to the TLC portion of the memory, which may take more time than writing to the SLC portion of the memory. In some cases, the memory system may enter a sleep mode (e.g., a low-power mode). Before entering sleep mode, the memory system may clear the write accelerator buffer by folding the contents of the write accelerator buffer into a TLC block. If data in the write accelerator buffer is overwritten, the contents folded into the TLC block may be invalid, thereby increasing the number of programming operations and programming cycles performed without significant benefit.

[0015] In some cases, it may be desirable to improve the operation of a memory system by reducing overall system power consumption and increasing the efficiency of the memory system. Overwriting data in the write accelerator buffer and invalidating the contents folded into the TLC blocks may cause the memory system to experience performance losses, increased signaling overhead, and increased processing overhead for performing operations. For example, the memory system may write invalid data from the write accelerator buffer to the TLC blocks before entering sleep mode. Such operations may not be useful and may incur costs in the memory system. In such cases, regardless of the amount of data stored in the write accelerator buffer, clearing the write accelerator buffer may reduce the performance of the memory system, increase power consumption, etc.

[0016] Systems, devices, and techniques for memory systems are described for determining whether to flush a write accelerator buffer based on the amount of data stored in the write accelerator buffer and, in some cases, a durability parameter associated with the memory system. In some cases, systems, devices, and techniques for memory systems are described for performing techniques for monitoring the write accelerator buffer based on the total bytes written (TBW) of the memory system. In such cases, if the TBW of the memory system meets a threshold, the memory system may avoid flushing (e.g., flushing) the contents of the write accelerator buffer to the TLC portion of the memory until the write accelerator buffer meets a fill threshold. For example, if the amount of data in the write accelerator buffer is below a threshold, the memory system may avoid flushing the contents of the write accelerator buffer to the TLC portion of the memory. If the amount of data in the write accelerator buffer is above a threshold, the memory system may flush the contents of the write accelerator buffer before entering sleep mode. In some cases, the memory system may modify the write accelerator fill threshold to improve performance when operating in write accelerator mode and entering sleep mode. For example, the memory system may monitor the fullness level of the write accelerator buffer and adjust (eg, lower) the write accelerator fill threshold, thereby delaying refresh operations and limiting the impact on write accelerator performance.

[0017] Determining whether the TBW of a memory system meets a threshold and determining whether the amount of data in a write accelerator buffer meets a threshold before performing a refresh operation can improve memory system performance by reducing the number of write operations involving potentially less useful data. Performing a refresh operation before entering sleep mode can reduce the amount of write accelerator data that can be overwritten and potentially invalid content, thereby reducing power consumption and allowing for more efficient and faster device programming. Such techniques can improve memory system performance, resulting in increased read speeds, reduced power consumption, reduced processing complexity, and improved processing time.

[0018] First, in reference Figure 1The features of the present disclosure are described in the context of a system. Figures 2 to 3 Features of the present disclosure are described in the context of systems and flow charts. Figures 4 to 5 These and other features of the present disclosure are further illustrated and described in the context of a device diagram and flow chart related to write accelerator buffering and hibernation.

[0019] Figure 1 An example of a system 100 supporting write accelerator buffering and hibernation according to examples disclosed herein is illustrated. The system 100 includes a host system 105 coupled to a memory system 110.

[0020] The memory system 110 may be or include any device or set of devices, wherein the device or set of devices includes at least one memory array. For example, the memory system 110 may be or include a universal flash storage (UFS) device, an embedded multimedia controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital (SD) card, a solid-state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), among other possibilities.

[0021] The computing system 100 may be included in a computing device, such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, drone, train, car, or other transportation vehicle), an Internet of Things (IoT)-enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or any other computing device that includes a memory and a processing device.

[0022] The system 100 may include a host system 105, which may be coupled to a memory system 110. In some instances, this coupling may include an interface with a host system controller 106, which may be an instance of a controller or control component configured to cause the host system 105 to perform various operations according to the examples described herein. The host system 105 may include one or more devices, and in some cases, may include a processor chipset and a software stack executed by the processor chipset. For example, the host system 105 may include an application configured to communicate with the memory system 110 or the devices therein. The processor chipset may include one or more cores, one or more caches (e.g., memory local to or included in the host system 105), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect Express (PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). The host system 105 may use the memory system 110, for example, to write data to and read data from the memory system 110. Although in Figure 1 One memory system 110 is shown in FIG. 1 , but the host system 105 can be coupled to any number of memory systems 110 .

[0023] The host system 105 can be coupled to the memory system 110 via at least one physical host interface. In some cases, the host system 105 and the memory system 110 can be configured to communicate via the physical host interface using an associated protocol (e.g., to exchange or otherwise convey control, address, data, and other signals between the memory system 110 and the host system 105). Examples of physical host interfaces can include, but are not limited to, a SATA interface, a UFS interface, an eMMC interface, a PCIe interface, a USB interface, a Fibre Channel interface, a Small Computer System Interface (SCSI), a Serial Attached SCSI (SAS), a Double Data Rate (DDR) interface, a DIMM interface (e.g., a DDR-capable DIMM socket interface), an Open NAND Flash Interface (ONFI), and a Low Power Double Data Rate (LPDDR) interface. In some examples, one or more such interfaces can be included in or otherwise supported between the host system controller 106 of the host system 105 and the memory system controller 115 of the memory system 110. In some examples, host system 105 may be coupled to memory system 110 via a respective physical host interface for each memory device 130 included in memory system 110, or via a respective physical host interface for each type of memory device 130 included in memory system 110 (e.g., host system controller 106 may be coupled to memory system controller 115).

[0024] The memory system 110 may include a memory system controller 115 and one or more memory devices 130. The memory device 130 may include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Figure 1 , two memory devices 130-a and 130-b are shown in the example of , but memory system 110 may include any number of memory devices 130. Furthermore, if memory system 110 includes more than one memory device 130, different memory devices 130 within memory system 110 may include the same or different types of memory cells.

[0025] The memory system controller 115 can be coupled to and communicate with the host system 105 (e.g., via a physical host interface) and can be an example of a controller or control component configured to cause the memory system 110 to perform various operations according to the examples described herein. The memory system controller 115 can also be coupled to and communicate with the memory devices 130 to perform operations that can generally be referred to as access operations at the memory devices 130, such as reading data, writing data, erasing data, or refreshing data, as well as other such operations. In some cases, the memory system controller 115 can receive commands from the host system 105 and communicate with one or more memory devices 130 to execute such commands (e.g., at a memory array within the one or more memory devices 130). For example, the memory system controller 115 can receive commands or operations from the host system 105 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices 130. In some cases, the memory system controller 115 may exchange data with the host system 105 and with one or more memory devices 130 (e.g., in response to or otherwise associated with commands from the host system 105). For example, the memory system controller 115 may convert responses associated with the memory devices 130 (e.g., data packets or other signals) into corresponding signals for the host system 105.

[0026] The memory system controller 115 may be configured for other operations associated with the memory device 130. For example, the memory system controller 115 may perform or manage operations such as wear leveling operations, garbage collection operations, error control operations such as error detection operations or error correction operations, encryption operations, cache operations, media management operations, background refresh, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 130.

[0027] The memory system controller 115 may include hardware, such as one or more integrated circuits or discrete components, buffer memory, or a combination thereof. The hardware may include circuitry having dedicated (e.g., hard-coded) logic to perform the operations attributed herein to the memory system controller 115. The memory system controller 115 may be or include a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry.

[0028] The memory system controller 115 may also include local memory 120. In some cases, the local memory 120 may include read-only memory (ROM) or other memory that may store operating code (e.g., executable instructions) that may be executed by the memory system controller 115 to perform the functions attributed herein to the memory system controller 115. In some cases, the local memory 120 may additionally or alternatively include static random access memory (SRAM) or other memory used by the memory system controller 115 for, for example, internal storage or operations related to the functions attributed herein to the memory system controller 115.

[0029] Memory device 130 may include one or more arrays of non-volatile memory cells. For example, memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase change memory (PCM), select memory, other chalcogenide-based memory, ferroelectric random access memory (RAM) (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), electrically erasable programmable ROM (EEPROM), or any combination thereof. Additionally or alternatively, memory device 130 may include one or more arrays of volatile memory cells. For example, memory device 130 may include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0030] In some examples, the memory devices 130 may include (e.g., on the same die or within the same package) a local controller 135 that may perform operations on one or more memory cells of the respective memory devices 130. The local controller 135 may operate in conjunction with the memory system controller 115 or may perform one or more functions attributed herein to the memory system controller 115. For example, Figure 1As illustrated, memory device 130-a may include a local controller 135-a, and memory device 130-b may include a local controller 135-b.

[0031] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a memory die 160. For example, in some cases, memory device 130 may be a package that includes one or more die 160. In some examples, die 160 may be a piece of electronic-grade semiconductor cut from a wafer (e.g., a silicon die cut from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a corresponding set of blocks 170, wherein each block 170 may include a corresponding set of pages 175, and each page 175 may include a set of memory cells.

[0032] In some cases, the NAND memory device 130 may include memory cells configured to store one bit of information each, which may be referred to as SLC. Additionally or alternatively, the NAND memory device 130 may include memory cells configured to store multiple bits of information each, which may be referred to as multi-level cells (MLC) if configured to store two bits of information each, TLC if configured to store three bits of information each, quad-level cells (QLC) if configured to store four bits of information each, or more generally, multi-level memory cells. Relative to SLC memory cells, multi-level memory cells may provide greater storage density, but in some cases may involve narrower read or write tolerances or greater complexity for supporting circuitry.

[0033] In some cases, a plane 165 may refer to a group of blocks 170, and in some cases, concurrent operations may occur within different planes 165. For example, concurrent operations may be performed on memory cells within different blocks 170, as long as the different blocks 170 are in different planes 165. In some cases, individual blocks 170 may be referred to as physical blocks, and a virtual block 180 may refer to a group of blocks 170 within which concurrent operations may occur. For example, concurrent operations may be performed on blocks 170-a, 170-b, 170-c, and 170-d within planes 165-a, 165-b, 165-c, and 165-d, respectively, and blocks 170-a, 170-b, 170-c, and 170-d may be collectively referred to as a virtual block 180. In some cases, a virtual block may include blocks 170 from different memory devices 130 (e.g., including blocks in one or more planes of memory device 130-a and memory device 130-b). In some cases, blocks 170 within a virtual block may have the same block address within their respective planes 165 (e.g., block 170-a may be "block 0" of plane 165-a, block 170-b may be "block 0" of plane 165-b, etc.). In some cases, performing concurrent operations in different planes 165 may be subject to one or more restrictions, such as performing concurrent operations on memory cells within different pages 175 that have the same page address within their respective planes 165 (e.g., related to command decode, page address decode circuitry, or other circuitry shared across planes 165).

[0034] In some cases, block 170 can include memory cells organized into rows (pages 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 can share (e.g., be coupled to) a common word line, and memory cells in the same string can share (e.g., be coupled to) a common digit line (which can alternatively be referred to as a bit line).

[0035] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first level of granularity (e.g., at a page-level granularity), but can be erased at a second level of granularity (e.g., at a block-level granularity). That is, a page 175 can be the smallest unit of memory (e.g., a group of memory cells) that can be independently programmed or read (e.g., programmed or read simultaneously as part of a single program or read operation), and a block 170 can be the smallest unit of memory (e.g., a group of memory cells) that can be independently erased (e.g., erased simultaneously as part of a single erase operation). Furthermore, in some cases, a NAND memory cell can be erased before it can be rewritten with new data. Thus, for example, in some cases, a used page 175 may not be updated until the entire block 170 containing the page 175 has been erased.

[0036] In some cases, the memory system controller 115 or the local controller 135 may perform operations for the memory device 130 (e.g., as part of one or more media management algorithms), such as wear leveling, background flushing, garbage collection, scrubbing, block scanning, health monitoring, or other operations, or any combination thereof. For example, within the memory device 130, a block 170 may have some pages 175 containing valid data and some pages 175 containing invalid data. To avoid waiting for all pages 175 in a block 170 to have invalid data in order to erase and reuse the block 170, an algorithm known as "garbage collection" may be invoked to allow the block 170 to be erased and freed as a free block for subsequent write operations. Garbage collection may refer to a set of media management operations that includes, for example, selecting a block 170 containing valid and invalid data, selecting a page 175 in the block containing valid data, copying the valid data from the selected page 175 to a new location (e.g., a free page 175 in another block 170), marking the data in the previously selected page 175 as invalid, and erasing the selected block 170. Thus, the amount of erased blocks 170 may be increased so that more blocks 170 are available to store subsequent data (eg, data subsequently received from the host system 105 ).

[0037] The system 100 may include any number of non-transitory computer-readable media that support write accelerator buffering and hibernation. For example, the host system 105, the memory system controller 115, or the memory device 130 (e.g., the local controller 135) may include or otherwise have access to one or more non-transitory computer-readable media that store instructions (e.g., firmware) to perform the functions attributed herein to the host system 105, the memory system controller 115, or the memory device 130. For example, if executed by the host system 105 (e.g., by the host system controller 106), by the memory system controller 115, or by the memory device 130 (e.g., by the local controller 135), such instructions may cause the host system 105, the memory system controller 115, or the memory device 130 to perform one or more associated functions as described herein.

[0038] In some cases, when the TBW of the memory system meets a threshold, system 100 may implement techniques for managing a write accelerator buffer. System 100 may initiate a first operation to enter a first power mode (e.g., a sleep mode) that has lower power consumption than a second power mode. In some examples, system 100 may determine whether the TBW to memory system 110 meets the threshold in response to initiating the first operation. In some cases, system 100 may determine whether the amount of data stored in a buffer of an SLC associated with the write accelerator information (e.g., a write accelerator buffer) meets a threshold in response to initiating the first operation. In such cases, system 100 may determine whether the fill level of the write accelerator buffer meets the threshold.

[0039] System 100 may determine whether to perform a second operation (e.g., a refresh operation) to transfer the amount of data stored in the buffer of the SLC to a portion of the memory including the multi-level cell in response to determining whether the amount of data meets a threshold. For example, system 100 may determine that the TBW meets a threshold and the amount of data meets a threshold. In such a case, system 100 may determine to perform the second operation in response to the determination. System 100 may enter the first power mode in response to performing the second operation to transfer the amount of data from the buffer to the portion of the memory.

[0040] Figure 2 An example of a system 200 supporting write accelerator buffering and hibernation according to the examples disclosed herein is illustrated. The system 200 may include a host system 205 and a memory system 210, which may be about Figure 1 Examples of corresponding apparatus described.

[0041] The memory system may include a first portion 215 and a second portion 220. The first portion 215 may be an example of an SLC portion of memory. In some cases, the NAND memory system 210 may include memory cells configured to each store one bit of information, which may be referred to as SLC. The second portion 220 may be an example of a portion of memory including multi-level cells. The multi-level cells may include multi-level cells configured to store two bits of data (e.g., MLC), triple-level cells configured to store three bits of data (e.g., TLC), or quad-level cells configured to store four bits of data (e.g., QLC). In such cases, the second portion 220 may be an example of a TLC portion of memory or a QLC portion of memory.

[0042] For example, the NAND memory system 210 may include memory cells configured to each store multiple bits of information, which may be referred to as MLC if each is configured to store two bits of information, TLC if each is configured to store three bits of information, QLC if each is configured to store four bits of information, or more generally, multi-level memory cells. Relative to SLC memory cells, multi-level memory cells may provide greater storage density, but in some cases may involve narrower read or write margins for supporting circuitry and increased time for reading and writing data.

[0043] First portion 215 may include buffer 225. Buffer 225 may be an example of a write accelerator buffer. In such a case, buffer 225 may be an example of a buffer of an SLC associated with write accelerator information. For example, buffer 225 may be an example of an SLC portion of memory that may include SLC blocks dedicated for write accelerator mode. Operating in write accelerator mode may include initially writing data to the SLC portion of memory (e.g., first portion 215) and then moving the data to the TLC portion of memory (e.g., second portion 220) as part of background operations. In such a case, memory system 210 may receive a command from host system 205 instructing memory system 210 to write data to a specific buffer (e.g., buffer 225) for faster performance.

[0044] For example, the host system 205 may send a write boost write command to the memory system 210. The memory system 210 may receive the write boost write command and initiate a write accelerator mode. The memory system 210 may activate the write accelerator mode in response to receiving the write accelerator command. In some cases, the memory system 210 may use the write accelerator mode to configure a portion of a data block (e.g., NAND memory cells) to be written. For example, the memory system 210 may write data to the SLC portion of the memory, which may allow the memory system 210 to write information faster than writing to the TLC portion. During the write accelerator mode, the memory system 210 may begin filling (e.g., storing) data in the buffer 225 (e.g., the SLC portion of the memory). Writing data to the SLC portion of the memory may take less time than writing to the TLC portion of the memory.

[0045] In some cases, memory system 210 may operate in a non-tracking mode. Non-tracking mode may be configured to perform a refresh operation before entering sleep mode, regardless of the amount of data stored in buffer 225. In such cases, host system 205 may transmit a request to memory system 210 to perform a refresh operation. Memory system 210 may flush buffer 225 and clear the contents of buffer 225 directly in response to receiving the request. In other examples, host system 205 may set a flag indicating a refresh operation during sleep mode. In such cases, memory system 210 may flush buffer 225 in response to recognizing that the flag is set and clear the contents of buffer 225. In some cases, the memory system may clear (e.g., flush) buffer 225 directly in response to receiving a request to perform a refresh operation and / or recognizing that the flag is set. For example, memory system 210 may remove data from buffer 225 before entering sleep mode.

[0046] Sleep mode may be an example of a low-power mode. During sleep mode or before entering sleep mode, the memory system 210 may perform background operations. A refresh operation may be an example of moving data from the buffer 225 of the first portion 215 to the second portion 220 (e.g., the TLC portion of the memory). In such cases, the memory system 210 may clear the contents of the buffer 225 during the refresh operation. In some examples, based on a refresh flag being set during sleep mode and / or the memory system 210 operating in a non-tracking mode, the memory system 210 may clear the contents of the buffer 225 until the buffer 225 is empty (e.g., contains no data). In other examples, the memory system 210 may clear the contents of the buffer 225 until the buffer 225 reaches a threshold 230, as described herein. For example, the memory system may activate tracking mode to determine whether to perform a refresh operation before entering the first sleep mode.

[0047] In some systems, the memory system 210 may flush the buffer 225 until the buffer 225 is completely empty (e.g., 0% full or 100% empty). If the memory system enters sleep mode multiple times within a duration, it is possible that data in the write accelerator buffer is transferred to the TLC block multiple times, and invalid data in the write accelerator buffer may even be transferred multiple times. In such cases, the new data in the TLC block may be marked as invalid, but not until after the data is transferred. In such cases, transferring write accelerator information (e.g., data stored in the buffer 225) and then immediately invalidating some of the data may increase the number of NAND programming operations and increase the consumption of NAND program / erase (PE) cycles. The memory system 210 can avoid folding invalid data into the TLC block by delaying the folding process. If the memory system 210 delays the folding process, the memory system 210 may overwrite (e.g., invalidate) a portion of the written data. As the duration of the delay increases, the memory system 210 may perform an increasing number of refresh operations to transfer the data in the buffer 225 to other blocks, thereby increasing overhead and reducing processing time.

[0048] To address these deficiencies, the memory system 210 may delay flushing the buffer 225 until a threshold 230 for the buffer 225 is satisfied. For example, the memory system 210 may determine whether the amount of data stored in the buffer of the SLC associated with the write accelerator information satisfies the threshold 230. In such cases, the threshold 230 may be an example of a fullness level of the buffer 225. For example, the threshold 230 may indicate a value for the amount of data stored in the buffer 225. In some cases, the threshold 230 may be an example of a percentage of available space in the buffer 225.

[0049] In some cases, the contents of buffer 225 may exceed threshold 230. In such cases, memory system 210 may determine that the contents of buffer 225 exceed the threshold and perform a refresh operation until the contents of buffer 225 are less than or equal to threshold 230. In other examples, memory system 210 may set parameters to ignore host instructions to refresh during sleep mode until buffer 225 fills to the value of threshold 230. In some examples, memory system 210 may set parameters to ignore host instructions to refresh during sleep mode until buffer 225 fills to a percentage of available space in buffer 225 (e.g., threshold 230). In response to memory system 210 determining that buffer 225 fills to threshold 230, memory system 210 may perform a refresh operation. Alternatively, in response to memory system 210 determining that buffer 225 does not fill to threshold 230, memory system 210 may refrain from performing a refresh operation.

[0050] Performing a refresh operation may be an example of clearing the contents of the buffer 225. In some examples, the memory system 210 may transfer data from the buffer 225 of the first portion 215 to the second portion 220 during the refresh operation. In such cases, the memory system 210 may keep hot content (e.g., recently written data) in the buffer 225 and avoid transferring the hot content to the second portion 220.

[0051] In some cases, threshold 230 may be an example of a percentage of unavailable (e.g., write) space in buffer 225. In one example, memory system 210 may set threshold 230 to 30% of the fill space. In such cases, memory system 210 may flush data from the buffer until threshold 230 is reached. For example, memory system 210 may flush buffer 225 to threshold 230 so that buffer 225 may contain at least 30% of the fill space (e.g., stored data). In the event that the next write operation overwrites the contents of buffer 225, memory system 210 may maintain at least 30% of buffer 225 with stored data.

[0052] In some cases, as the memory system ages, it may be necessary to employ these write accelerator buffer flushing techniques. When the memory system is relatively new, it may prioritize performance and flush the write accelerator buffer to the TLC blocks each time it enters sleep mode. As the memory system ages, it may want to limit the amount of write operations. Therefore, the memory system 210 may determine whether the TBW to the memory system 210 meets a second threshold different from threshold 230, and then begin implementing these techniques when the TBW meets the threshold. In some cases, the threshold may be an example of the amount of TBW. For example, the memory system 210 may set parameters to ignore host instructions to flush during sleep mode until the buffer 225 fills to threshold 230 indicating the TBW. In some cases, the TBW may represent the amount of data that the host system 205 can write to the memory system 210. For example, the host system 205 may issue a write command or a read command to access the memory system 210. Management operations may be performed while a host-initiated operation (e.g., a host-initiated write operation) is being performed. Such a procedure may cause the amount of TBW to increase because more data may be written to or read from the memory system 210 than requested by the host system 205 .

[0053] In some cases, the memory system 210 may determine that the TBW fails to meet the threshold 230 (e.g., is below the threshold 230). In such cases, the memory system 210 may clear (e.g., flush) the contents of the buffer 225 so that the buffer 225 may not contain any stored data (e.g., is 0% full). In some cases, the memory system 210 may refrain from performing a flush operation directly in response to determining that the TBW fails to meet the threshold 230. In other examples, the memory system 210 may determine that the TBW meets (e.g., exceeds) the threshold 230. In such cases, the memory system 210 may flush the contents of the buffer 225 to the threshold 230.

[0054] The contents of buffer 225 can be flushed so that after memory system 210 exits sleep mode, memory system 210 can utilize the entire space of buffer 225 during the next active session to accept write accelerator commands from host system 205, thereby improving the performance of memory system 210. Write accelerator mode can improve the performance of write operations. Due to the fullness of buffer 225, the performance of memory system 210 may decrease. In such cases, memory system 210 can adjust the threshold 230 of buffer 225 based on the activity of memory system 210.

[0055] The memory system 210 may monitor the fullness level of the buffer 225. In some examples, the memory system 210 may monitor a threshold 230 for the buffer 225. The memory system 210 may determine that the buffer 225 is full (e.g., 100% full) and may slow down write traffic in the write accelerator mode in response to determining that the buffer 225 is full. In such cases, the memory system 210 may adjust the threshold 230. For example, the memory system 210 may reduce the threshold 230. In some examples, the memory system 210 may reduce the threshold 230 by increments of one percent or a nominal value. The memory system 210 may continue to reduce the threshold 230 by 1% each time the buffer 225 fills to 100% full. By using an automatic adjustment factor, the memory system 210 may lower the threshold 230 and determine the threshold 230 between delaying refresh operations and limiting the impact on write accelerator performance.

[0056] In some cases, the memory system 210 may identify incoming data to be stored in the buffer 225. The memory system 210 may monitor the fill level (e.g., threshold 230) of the buffer 225 and determine that the buffer 225 may not be able to store the incoming data. For example, the memory system 210 may determine that the buffer 225 is full. In such cases, the memory system 210 may reduce the fill threshold size (e.g., threshold 230) until the buffer 225 is able to store the incoming data.

[0057] For example, the host system 205 may transmit a write command to the memory system 210. The memory system 210 may recognize the incoming write command and determine that the buffer 225 is full (e.g., does not contain available space to store the incoming write command). In such a case, the memory system 210 may automatically lower the threshold 230. For example, the memory system 210 may estimate a desired threshold 230 based on the usage pattern of the memory system 210 and adjust the threshold 230 (e.g., to a lower value) until the desired threshold 230 is met.

[0058] In some cases, the memory system 210 may determine the amount of buffer 225 that the memory system 210 utilizes over a day or other duration. For example, the memory system 210 may determine the amount of buffer 225 that is filled at the end of the day. In one example, the memory system 210 may determine that 50% of the buffer 225 is available for use at the end of the day. In such a case, the memory system 210 may set the threshold 230 to 50% full (e.g., unavailable space for storing data). The memory system 210 may determine that 40% of the buffer 225 is available for use for the next day. In such a case, the memory system 210 may adjust (e.g., lower) the threshold to 40% full.

[0059] In some cases, determining whether the TBW meets a threshold before performing a refresh operation and determining whether the amount of data meets the threshold can increase the TBW by preventing invalid folded data. In some examples, the system 200 can reduce power consumption by reducing the amount of write accelerator folding procedures. Waiting to perform a refresh operation until the threshold 230 is reached can extend write accelerator performance and increase the lifespan of the memory system 210 by providing improved performance and increased write accelerator alignment.

[0060] Figure 3 An example of a flowchart 300 illustrating support for write accelerator buffering and hibernation according to examples disclosed herein. Flowchart 300 may include a host system 305 and a memory system 310. Host system 305 and memory system 310 may be about Figure 1 and 2 Examples of corresponding devices described. Alternative examples of the following content may be implemented, in which some steps are performed in a different order than described or not performed at all. In some cases, the steps may include additional features not mentioned below, or other steps may be added.

[0061] Aspects of flowchart 300 may be implemented by a controller and other components. Additionally or alternatively, aspects of flowchart 300 may be implemented as instructions stored in a memory (e.g., firmware stored in a memory coupled to a controller). For example, when executed by a controller, the instructions may cause the controller to perform the operations of flowchart 300.

[0062] At 305, a sleep mode can be initiated. For example, the memory system can initiate a first operation at the memory system into a first power mode having lower power consumption than a second power mode. In some cases, the first power mode can be an example of a sleep mode, a low power mode, a sleep mode, or a combination thereof. The second power mode can be an example of an active mode, a high power mode, an access mode, or a combination thereof.

[0063] The memory system may recognize a request to perform a refresh operation (e.g., a second operation) associated with the memory system in response to a first operation initiating entry into a first power mode. For example, the memory system may receive the request to perform a refresh operation directly in response to the operation initiating entry into a sleep mode. In some cases, the request may not be received by the memory system, but may be generated internally. In such cases, the memory system may generate the request to perform the refresh operation.

[0064] At 310, a tracking mode may be activated. For example, the memory system may activate the tracking mode before entering a sleep mode (e.g., the first power mode) to determine whether to perform a refresh operation (e.g., the second operation). Tracking mode may be an example in which a refresh operation is performed until a percentage of free space in the buffer meets a threshold. In some cases, the memory system may activate a manually controlled threshold technique in which the memory system sets a threshold for the buffer and performs a refresh operation until the threshold is reached. In such cases, the threshold may be greater than or equal to zero. Non-tracking mode may be an example in which a refresh operation is performed until the buffer is empty. In such cases, the threshold may be zero. In some cases, tracking mode may be entered before initiating sleep mode.

[0065] At 315, it may be determined whether the TBW meets a threshold. For example, the memory system may determine whether the TBW to the memory system meets a threshold. In some examples, the memory system may determine whether the TBW to the memory system meets the threshold based on activating a tracking mode and / or initiating a sleep mode.

[0066] In some cases, the memory system may determine that the TBW fails to meet a threshold. In such cases, at 335, the refresh operation may be avoided. For example, the memory system may avoid performing a refresh operation in direct response to determining that the TBW fails to meet a threshold. In some cases, entering a sleep mode (e.g., a first power mode) without performing a refresh operation (e.g., a second operation) may occur in direct response to determining that the TBW fails to meet a threshold and determining to avoid performing a refresh operation. In such cases, if the TBW fails to meet the threshold, the memory system may avoid performing a refresh operation.

[0067] In some examples, the memory system may determine that the TBW meets a threshold. In such cases, at 320, it may be determined whether the data meets the threshold. For example, the memory system may determine whether the amount of data stored in the buffer of the SLC associated with the write accelerator information meets the threshold based on initiating the first operation to enter the first power mode. In such cases, the memory system may determine whether the write buffer fill meets the threshold.

[0068] In some cases, determining whether the amount of data meets the threshold may be based on activating the tracking mode. In some instances, determining whether the amount of data meets the threshold may be a direct response to determining whether the TBW meets the threshold. For example, if the TBW meets the threshold, the memory system may check the write buffer fill threshold. The memory system may determine whether the percentage of available space in the buffer meets the threshold after initiating the sleep mode. For example, the memory system may determine whether the fullness level of the write accelerator buffer meets the threshold. In some cases, the memory system may determine whether the amount of space used by the write accelerator buffer to store data meets the threshold. The amount of data may be a nominal value of the value of the data, a percentage of the total amount of data, or an example of a combination thereof. The memory system may determine whether the write accelerator buffer size meets the threshold. In some cases, the memory system may determine whether the write traffic is slowed down.

[0069] The memory system may determine that the amount of data fails to meet a threshold. In some cases, the memory system may determine that a percentage of available space in the buffer fails to meet a threshold in response to determining that the TBW meets the threshold. In such cases, at 335, a refresh operation may be avoided. For example, the memory system may avoid a refresh operation in response to determining that the amount fails to meet the threshold. In some cases, after determining that the amount fails to meet the threshold and determining to avoid a refresh operation, entry into a sleep mode may occur without performing a refresh operation. In such cases, if the amount of data fails to meet the threshold, the memory system may avoid a refresh operation.

[0070] The memory system may determine that the amount of data meets a threshold in response to determining that the TBW meets a threshold. In some cases, the memory system may determine that a percentage of available space in the buffer meets a threshold after initiating a sleep mode. The memory system may determine that a write accelerator buffer size meets a threshold. In some cases, the memory system may determine that write traffic is slowed.

[0071] At 325, a determination may be made as to whether to perform a refresh operation. For example, the memory system may determine, in direct response to determining that the amount of data satisfies a threshold, whether to perform a refresh operation (e.g., a second operation) to transfer the amount of data stored in the buffer of the SLC to a portion of the memory comprising a multi-level cell. The multi-level cell may be an example of a multi-level cell configured to store two bits of data, a tri-level cell configured to store three bits of data, or a quad-level cell configured to store four bits of data. In such cases, the memory system may include an SLC, a TLC, a QLC, or a combination thereof. In some cases, determining whether to perform a refresh operation may be based on activating a tracking mode.

[0072] In some cases, the memory system may determine to avoid performing a refresh operation at 335. In other examples, a refresh operation may be performed at 330. For example, the memory system may perform a refresh operation in response to determining that the amount of data meets a threshold and / or determining to perform a refresh operation. In such cases, the memory system may perform a refresh operation if the write buffer fill (e.g., the amount of data in the write buffer) meets the threshold.

[0073] An example of performing a refresh operation is to avoid transferring the data last written before the memory system enters sleep mode. In such cases, the memory system may avoid transferring the data last written before the memory system enters sleep mode in response to determining that the amount of data meets a threshold and / or determining to perform a refresh operation. For example, the memory system may retain hot content in a write accelerator buffer (e.g., avoid transferring the hot content). In such cases, the most recently written data block may not be refreshed.

[0074] In some cases, performing a flush operation may be an example of transferring data from an SLC cache to a TLC cache. The memory system may transfer data from the SLC cache to the TLC cache in response to determining that the amount of data meets a threshold and / or determining that a percentage meets a threshold. In some cases, the flush operation may be performed until the amount of data equals the threshold. For example, the memory system may flush the memory system to a threshold.

[0075] At 340, a sleep mode may be entered. For example, the memory system may enter the sleep mode directly in response to determining to perform a refresh operation to transfer the amount of data from the buffer to the portion of the memory. In such cases, the memory system may enter the sleep mode after performing the refresh operation. In some examples, the memory system may enter the sleep mode after refraining from performing a refresh operation. In such cases, the memory system may enter the sleep mode without performing a refresh operation.

[0076] At 345, a post-operation analysis can be performed. For example, the memory system can check a fill threshold, and after completing the sleep mode, the memory system can perform a post-operation analysis. The post-operation analysis can include determining the number of refresh operations performed by the memory system. If the number of refresh operations performed by the memory system is equal to or greater than a threshold, the memory system can adjust the threshold.

[0077] For example, the memory system may adjust the threshold directly in response to determining that the percentage of available space in the buffer is below a threshold. In such cases, if the write accelerator buffer is full, the memory system may lower the write accelerator fill threshold. For example, the memory system may reduce the write accelerator fill threshold by a nominal value, one percent increments, or other increments of value and / or percentage. In some examples, the memory system may determine the threshold after activating a tracking mode (e.g., a learning mode) to automatically control the threshold. In such cases, the threshold may be adjusted based on current usage statistics, previous usage static data on the write buffer, or both.

[0078] Figure 4 A block diagram 400 is shown of a memory system 420 that supports write accelerator buffering and hibernation according to examples disclosed herein. The memory system 420 may be a memory system 420 as described in reference to FIG. Figures 1 to 3 Memory system 420 or its various components may be examples of means for performing various aspects of write accelerator buffering and hibernation as described herein. For example, memory system 420 may include a request component 425, a threshold component 430, a refresh component 435, a hibernation component 440, or any combination thereof. Each of these components may communicate with each other, directly or indirectly (e.g., via one or more buses).

[0079] The request component 425 may be configured to or otherwise support means for initiating a first operation at the memory system to enter a first power mode having lower power consumption than a second power mode. The threshold component 430 may be configured to or otherwise support means for determining whether the amount of data stored in the buffer of the single-level cell associated with the write accelerator information satisfies a threshold based at least in part on initiating the first operation to enter the first power mode. The refresh component 435 may be configured to or otherwise support means for determining whether to perform a second operation to transfer the amount of data stored in the buffer of the single-level cell to a portion of the memory including the multi-level cell based at least in part on determining whether the amount of data satisfies the threshold. The sleep component 440 may be configured to or otherwise support means for entering the first power mode based at least in part on determining to perform the second operation to transfer the amount of data from the buffer to the portion of the memory.

[0080] In some examples, refresh component 435 can be configured to or otherwise support means for performing a second operation based at least in part on determining that the amount of data satisfies a threshold and determining to perform the second operation, wherein entering the first power mode is based at least in part on performing the second operation.

[0081] In some examples, entering the first power mode occurs without performing the second operation based at least in part on determining that the amount of data fails to satisfy a threshold and determining to avoid performing the second operation.

[0082] In some examples, threshold component 430 may be configured to or otherwise support means for determining whether the total written bytes of the memory system satisfy a second threshold, wherein determining whether the amount of data satisfies the threshold is based at least in part on determining whether the total written bytes satisfy the second threshold.

[0083] In some examples, the hibernation component 440 can be configured to or otherwise support means for activating a tracking mode at the memory system to determine whether to perform the second operation before entering the first power mode, wherein determining that the amount of data satisfies the threshold and determining to perform the second operation are based at least in part on activating the tracking mode.

[0084] In some examples, to support determining whether the amount of data satisfies the threshold, threshold component 430 can be configured or otherwise support means for determining that a percentage of available space in the buffer after initiation occurs satisfies the threshold.

[0085] In some examples, threshold component 430 can be configured or otherwise support means for adjusting the threshold based at least in part on determining that the percentage of available space in the buffer is below a second threshold.

[0086] In some examples, refresh component 435 can be configured as or otherwise support means for identifying a request to perform a refresh operation associated with the memory system based at least in part on the first operation to initiate entry into the first power mode.

[0087] In some examples, refresh component 435 can be configured as or otherwise support means for avoiding transferring data last written before the memory system entered the first power mode based at least in part on determining that an amount of data satisfies a threshold.

[0088] In some examples, the second operation is performed until the amount of data equals a threshold. In some examples, the first power mode includes a sleep mode. In some examples, the multi-level cell includes: a multi-level cell configured to store two bits of data; a three-level cell configured to store three bits of data; or a four-level cell configured to store four bits of data.

[0089] Figure 5 A flowchart illustrating a method 500 for supporting write accelerator buffering and hibernation according to examples disclosed herein is shown. The operations of the method 500 may be implemented by a memory system or components thereof as described herein. For example, the operations of the method 500 may be implemented by reference to Figures 1 to 4 The memory system described herein performs. In some examples, the memory system may execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the memory system may use dedicated hardware to perform aspects of the functions described below.

[0090] At 505, a first operation may be initiated. The method may include initiating a first operation at a memory system to enter a first power mode, the first power mode having lower power consumption than a second power mode. The operation of 505 may be performed according to examples disclosed herein. In some examples, aspects of the operation of 505 may be as described with reference to Figure 4 The described request component 425 executes.

[0091] At 510, it may be determined whether the amount of data satisfies a threshold. The method may include determining whether the amount of data stored in a buffer of a single level unit associated with write accelerator information satisfies a threshold based at least in part on a first operation of initiating entry into a first power mode. The operation of 510 may be performed according to examples disclosed herein. In some examples, the method may be performed by a processor as described in reference to Figure 4 The threshold component 430 is described as performing aspects of the operation of 510 .

[0092] At 515, a determination may be made as to whether to perform a second operation. The method may include determining, based at least in part on determining whether the amount of data satisfies a threshold, whether to perform a second operation of transferring the amount of data stored in the buffer of the single-level cell to a portion of the memory including the multi-level cell. The operation of 515 may be performed according to examples as disclosed herein. In some examples, aspects of the operation of 515 may be described as described with reference to Figure 4 The refresh component 435 is described as executing.

[0093] At 520, a first power mode may be entered. The method may include entering the first power mode based at least in part on determining to perform a second operation of transferring the amount of data from the buffer to the portion of the memory. The operation of 520 may be performed according to examples disclosed herein. In some examples, the operation may be performed as described in reference to Figure 4 The hibernation component 440 is described as performing aspects of the operations of 520 .

[0094] In some examples, an apparatus as described herein may perform one or more methods, such as method 500. The apparatus may include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following aspects of the present disclosure, or any combination thereof:

[0095] Aspect 1: The device includes features, circuit systems, logic, components or instructions or any combination thereof for the following operations: initiating a first operation to enter a first power mode at a memory system, the first power mode having lower power consumption than a second power mode; determining whether an amount of data stored in a buffer of a single-level cell associated with write accelerator information satisfies a threshold based at least in part on the first operation to initiate entry into the first power mode; determining whether to perform a second operation to transfer the amount of data stored in the buffer of the single-level cell to a portion of a memory including multi-level cells based at least in part on determining whether the amount of data satisfies the threshold; and performing the second operation to transfer the amount of data from the buffer to the portion of the memory based at least in part on the determination.

[0096] Aspect 2: The apparatus of Aspect 1, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for performing the following operations: performing the second operation based at least in part on determining that the amount of data satisfies the threshold and determining to perform the second operation, wherein entering the first power mode is based at least in part on performing the second operation.

[0097] Aspect 3: An apparatus according to any one of Aspects 1 to 2, further comprising operations, features, circuit systems, logic, components or instructions or any combination thereof for the following operations: entering the first power mode occurs without performing the second operation based at least in part on determining that the amount of data fails to meet the threshold and determining to avoid performing the second operation.

[0098] Aspect 4: An apparatus according to any one of Aspects 1 to 3, further comprising operations, features, circuit systems, logic, components or instructions or any combination thereof for the following operations: determining whether the total written bytes of the memory system meet a second threshold, wherein determining whether the amount of data meets the threshold is at least partially based on determining whether the total written bytes meet the second threshold.

[0099] Aspect 5: The apparatus of aspect 4, further comprising operations, features, circuit systems, logic, means or instructions, or any combination thereof, for activating a tracking mode at the memory system to determine whether to perform the second operation before entering the first power mode, wherein determining that the amount of data satisfies the threshold and determining to perform the second operation are based at least in part on activating the tracking mode.

[0100] Aspect 6: An apparatus according to any one of Aspects 1 to 5, wherein determining whether the amount of data satisfies the threshold further comprises operations, features, circuit systems, logic, components or instructions or any combination thereof for the following operations: determining whether the percentage of available space in the buffer after the start occurs satisfies the threshold.

[0101] Aspect 7: The apparatus of aspect 6, further comprising operations, features, circuitry, logic, means or instructions, or any combination thereof, for adjusting the threshold based at least in part on determining that the percentage of the available space in the buffer is below a second threshold.

[0102] Aspect 8: An apparatus according to any one of aspects 1 to 7, further comprising operations, features, circuit systems, logic, components or instructions, or any combination thereof, for performing the following operations: identifying a request to perform a refresh operation associated with the memory system based at least in part on the first operation of initiating entry into the first power mode.

[0103] Aspect 9: An apparatus according to any one of aspects 1 to 8, further comprising operations, features, circuit systems, logic, components or instructions or any combination thereof for performing the following operations: avoiding transmitting data last written before the memory system enters the first power mode based at least in part on determining that the amount of data meets the threshold.

[0104] Aspect 10: The apparatus of any one of aspects 1 to 9, further comprising operations, features, circuitry, logic, means, or instructions, or any combination thereof, for performing the second operation until the amount of data equals the threshold.

[0105] Aspect 11: The apparatus of any one of aspects 1 to 10, further comprising operations, features, circuitry, logic, means, or instructions, or any combination thereof, for: the first power mode comprises a sleep mode.

[0106] Aspect 12: The apparatus of any one of Aspects 1 to 11, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for the following operations: the multi-level cell comprises a multi-level cell configured to store two data bits, a tri-level cell configured to store three data bits, or a quad-level cell configured to store four data bits.

[0107] It should be noted that the methods described above describe possible embodiments, and that the operations and steps may be rearranged or otherwise modified, and other embodiments are possible. Furthermore, portions from two or more of the methods may be combined.

[0108] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some figures may illustrate a signal as a single signal; however, the signal may represent a bus of signals, where the bus may have various bit widths.

[0109] The terms "electronic communication," "conductive contact," "connected," and "coupled" may refer to a relationship between components that supports the flow of signals between the components. Components are considered to be in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) if any conductive path exists between the components that can support the flow of signals between the components at any time. At any given time, the conductive path between components in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) may be an open circuit or a closed circuit based on the operation of the device that includes the connected components. The conductive path between the connected components may be a direct conductive path between the components, or the conductive path between the connected components may be an indirect conductive path that may include an intermediate component such as a switch, transistor, or other component. In some examples, the flow of signals between the connected components may be interrupted for a period of time, for example, using one or more intermediate components such as a switch or transistor.

[0110] The term "coupling" refers to a condition in which a signal is moved from an open-circuit relationship between components, in which signals are currently unable to communicate between the components via a conductive path, to a closed-circuit relationship in which signals are able to communicate between the components via the conductive path. If a component, such as a controller, couples other components together, the component initiates a change that allows signals to flow between the other components via the conductive path that previously did not permit signal flow.

[0111] The term "isolation" refers to a relationship between components where signals are currently unable to flow between them. If an open circuit exists between the components, the components are isolated from each other. For example, if a switch is open, the components separated by the switch between two components are isolated from each other. If a controller isolates two components, it implements a change that prevents signals from flowing between the components using the conductive path that previously allowed signal flow.

[0112] The terms "if," "when," "based on," or "based at least in part on" are used interchangeably. In some instances, if the terms "if," "when," "based on," or "based at least in part on" are used to describe a conditional action, a conditional process, or a connection between parts of a process, the terms are interchangeable.

[0113] The term "in response to" may refer to a condition or action that occurs at least in part (if not entirely) as a result of a preceding condition or action. For example, a first condition or action may be performed, and a second condition or action may occur at least in part as a result of the preceding condition or action occurring (whether directly after the first condition or action or after one or more other intermediate conditions or actions occur after the first condition or action).

[0114] In addition, the term "directly in response to" or "directly in response to" may refer to a condition or action that occurs as a direct result of a previous condition or action. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a previous condition or action occurring regardless of whether other conditions or actions occur. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a previous condition or action occurring, such that no other intermediate conditions or actions occur between the earlier condition or action and the second condition or action, or a limited number of one or more intermediate steps or actions occur between the earlier condition or action and the second condition or action. Unless otherwise specified, any condition or action described herein as being "based on," "at least partially based on," or "in response to" some other step, action, event, or condition and performed may be performed additionally or alternatively (e.g., in alternative instances) "directly in response to" or "directly in response to" such other condition or action.

[0115] The devices including memory arrays discussed herein can be formed on a semiconductor substrate, such as silicon, germanium, a silicon-germanium alloy, gallium arsenide, gallium nitride, or the like. In some examples, the substrate is a semiconductor wafer. In some other examples, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a subregion of the substrate can be controlled by doping using various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, by ion implantation, or by any other doping method.

[0116] The switch components or transistors discussed herein may represent field-effect transistors (FETs) and include three-terminal devices comprising a source, a drain, and a gate. The terminals can be connected to other electronic components via conductive materials such as metals. The source and drain can be conductive and can include heavily doped (e.g., degenerate) semiconductor regions. The source and drain can be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., the majority carriers are electrons), then the FET can be referred to as an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), then the FET can be referred to as a p-type FET. The channel can be terminated by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can make the channel conductive. If a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, then the transistor can be "switched on" or "activated." If a voltage less than the threshold voltage of the transistor is applied to the transistor gate, then the transistor can be "off" or "deactivated."

[0117] The description set forth herein in conjunction with the accompanying drawings describes example configurations and does not represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration" and is not "preferred" or "advantageous" over other examples. The detailed description includes specific details to provide an understanding of the described technology. However, these technologies can be practiced without these specific details. In some cases, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0118] In the drawings, similar components or features may have the same reference label. Furthermore, various components of the same type may be distinguished by following the reference label with a dash and a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label, regardless of the second reference label.

[0119] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored as one or more instructions or codes on a computer-readable medium or transmitted via a computer-readable medium. Other examples and implementations are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hardwiring, or a combination of any of these. Features implementing the functions may also be physically located at various locations, including being distributed so that parts of the functions are implemented at different physical locations.

[0120] For example, the various illustrative blocks and components described in connection with the disclosure herein may be implemented or performed using a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor; however, in the alternative, the processor may be any processor, controller, microcontroller, or state machine. A processor may be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0121] As used herein, "or" used in a list of items (e.g., a list of items beginning with a phrase such as "at least one of" or "one or more of"), including in the claims, indicates an inclusive list, such that a list of at least one of, for example, A, B, or C means A or B or C, or AB or AC or BC, or ABC (i.e., A and B and C). Additionally, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, an exemplary step described as "based on condition A" could be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on."

[0122] Computer-readable media include both non-transitory computer storage media and communication media, and communication media include any media that facilitates the transfer of computer programs from one place to another. Non-transitory storage media can be any available media that can be accessed by a general-purpose or special-purpose computer. By way of example and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and can be accessed by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Also, any connection is appropriately referred to as a computer-readable medium. For example, if software is transmitted from a website, server or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technologies such as infrared, radio and microwaves, then the coaxial cable, fiber optic cable, twisted pair, DSL or wireless technologies such as infrared, radio and microwaves are included in the definition of media. As used herein, disk and disc include CDs, laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0123] The description herein is provided to enable one skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A device comprising: Memory system; as well as A controller coupled to the memory system, wherein the controller is configured to cause the device to: initiating a first operation at the memory system to enter a first power mode having lower power consumption than a second power mode; determining whether the total written bytes of the memory system meet a first threshold; determining, based at least in part on the first operation to initiate entry into the first power mode, whether an amount of data stored in a buffer of a single level unit associated with write accelerator information satisfies a second threshold, wherein determining whether the amount of data satisfies the second threshold is based at least in part on determining whether the total written bytes satisfies the first threshold; determining whether to perform a second operation of transferring the amount of data stored in the buffer of the single-level cell to a portion of a memory including multiple-level cells based at least in part on determining whether the amount of data satisfies the second threshold; as well as The first power mode is entered based at least in part on determining to perform the second operation of transferring the amount of data from the buffer to the portion of memory.

2. The apparatus of claim 1 , wherein the controller is further configured to cause the apparatus to: The second operation is performed based at least in part on determining that the amount of data satisfies the second threshold and determining to perform the second operation, wherein entering the first power mode is based at least in part on performing the second operation. 3 . The apparatus of claim 1 , wherein entering the first power mode occurs without performing the second operation based at least in part on determining that the amount of data fails to satisfy the second threshold and determining to avoid performing the second operation.

4. The apparatus of claim 1 , wherein the controller is further configured to cause the apparatus to: A tracking mode is activated at the memory system to determine whether to perform the second operation before entering the first power mode, wherein determining the amount of data satisfies the second threshold and determining to perform the second operation is based at least in part on activating the tracking mode.

5. The apparatus of claim 1 , determining whether the amount of data satisfies the second threshold further comprising: A determination is made as to whether a percentage of available space in the buffer after the initiation occurs satisfies the second threshold.

6. The apparatus of claim 5, wherein the controller is further configured to cause the apparatus to: The second threshold is adjusted based at least in part on a determination that the percentage of the available space of the buffer is below a third threshold.

7. The apparatus of claim 1 , wherein the controller is further configured to cause the apparatus to: A request to perform a refresh operation associated with the memory system is identified based at least in part on the first operation to initiate entry into the first power mode.

8. The apparatus according to claim 1, further comprising: Based at least in part on determining that the amount of data satisfies the second threshold, transferring data last written before the memory system entered the first power mode is avoided.

9. The apparatus of claim 1, wherein the second operation is performed until the amount of data equals the second threshold.

10. The device of claim 1, wherein the first power mode comprises a sleep mode.

11. The apparatus of claim 1 , wherein: The multi-level cell includes: a multi-level cell configured to store two data bits; a triple-level cell configured to store three data bits; or a quad-level cell configured to store four data bits.

12. A non-transitory computer-readable medium storing code, the code comprising instructions executable by a processor to: initiating a first operation at a memory system to enter a first power mode having lower power consumption than a second power mode; determining whether the total written bytes of the memory system meet a first threshold; determining, based at least in part on the first operation to initiate entry into the first power mode, whether an amount of data stored in a buffer of a single level unit associated with write accelerator information satisfies a second threshold, wherein determining whether the amount of data satisfies the second threshold is based at least in part on determining whether the total written bytes satisfies the first threshold; determining whether to perform a second operation of transferring the amount of data stored in the buffer of the single-level cell to a portion of a memory including multiple-level cells based at least in part on determining whether the amount of data satisfies the first threshold; as well as The first power mode is entered based at least in part on determining to perform the second operation of transferring the amount of data from the buffer to the portion of memory.

13. The non-transitory computer-readable medium of claim 12, wherein the instructions are further executable by the processor to: The second operation is performed based at least in part on determining that the amount of data satisfies the second threshold and determining to perform the second operation, wherein entering the first power mode is based at least in part on performing the second operation.

14. The non-transitory computer-readable medium of claim 12, wherein entering the first power mode occurs without performing the second operation based at least in part on determining that the amount of data fails to satisfy the second threshold and determining to avoid performing the second operation.

15. The non-transitory computer-readable medium of claim 12, wherein the instructions are further executable by the processor to: A tracking mode is activated at the memory system to determine whether to perform the second operation before entering the first power mode, wherein determining the amount of data satisfies the second threshold and determining to perform the second operation is based at least in part on activating the tracking mode.

16. The non-transitory computer-readable medium of claim 12, determining whether the amount of data satisfies the second threshold further comprising: A determination is made as to whether a percentage of available space in the buffer after the initiation occurs satisfies the second threshold.

17. The non-transitory computer-readable medium of claim 16, wherein the instructions are further executable by the processor to: The second threshold is adjusted based at least in part on a determination that the percentage of the available space of the buffer is below a third threshold.

18. A method comprising: initiating a first operation at a memory system to enter a first power mode having lower power consumption than a second power mode; determining whether the total written bytes of the memory system meet a first threshold; determining, based at least in part on the first operation to initiate entry into the first power mode, whether an amount of data stored in a buffer of a single level unit associated with write accelerator information satisfies a second threshold, wherein determining whether the amount of data satisfies the second threshold is based at least in part on determining whether the total written bytes satisfies the first threshold; determining whether to perform a second operation of transferring the amount of data stored in the buffer of the single-level cell to a portion of a memory including multiple-level cells based at least in part on determining whether the amount of data satisfies the second threshold; as well as The first power mode is entered based at least in part on determining to perform the second operation of transferring the amount of data from the buffer to the portion of memory.

19. The method of claim 18, further comprising: The second operation is performed based at least in part on determining that the amount of data satisfies the second threshold and determining to perform the second operation, wherein entering the first power mode is based at least in part on performing the second operation.

20. The method of claim 18, wherein entering the first power mode occurs without performing the second operation based at least in part on determining that the amount of data fails to satisfy the second threshold and determining to avoid performing the second operation.

21. The method of claim 18, further comprising: A tracking mode is activated at the memory system to determine whether to perform the second operation before entering the first power mode, wherein determining the amount of data satisfies the second threshold and determining to perform the second operation is based at least in part on activating the tracking mode.

22. The method of claim 18, determining whether the amount of data satisfies the second threshold further comprising: A determination is made as to whether a percentage of available space in the buffer after the initiation occurs satisfies the second threshold.

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