Memory cache pool maintenance method, device, system and storage medium

Abstract

The embodiments of the present application provide a memory cache pool maintenance method, device, system and storage medium. In the embodiments of the present application, for a storage-computing separation architecture, a processing unit interconnected with a computing unit is added to a computing node and a memory node, and the consistency maintenance task of the memory cache data is pushed down to the processing unit for execution, rather than being completed on the computing unit. Since the processing unit has the ability to directly access the local memory cache pool or the shared memory cache pool, the data transmission process in the memory cache data consistency maintenance process is mostly completed within the processing unit without uploading to the computing unit, which can eliminate the delay in data transmission between the computing unit and the network card, thereby achieving the purpose of reducing data transmission delay in the process of maintaining cache data consistency.

Description

Technical Field

[0001] The present application relates to the field of cloud computing technology, and in particular to a memory cache pool maintenance method, device, system and storage medium. Background Art

[0002] With the development of cloud-native technologies, cloud-native database applications have emerged. These applications leverage cloud-based hardware and software resources to pool and allocate storage and computing resources on demand, resulting in higher resource utilization and availability. However, different database applications have varying requirements for storage and computing resources. Therefore, dynamically scaling computing and memory resources on demand based on the application's load is crucial for achieving stable high throughput and low latency, while also improving resource utilization and saving costs.

[0003] To this end, cloud-native database applications adopt a storage-computing separation architecture. In this storage-computing separation architecture, compute nodes mainly provide computing resources. Remote memory nodes, as extensions of the memory buffer pool resources on the compute nodes, are responsible for providing remote memory buffer pool resources. Persistent storage nodes provide persistent storage resources, forming three independent resource pools. The computing resources on the compute nodes and the memory buffer pool resources provided by the remote memory nodes are separated. The expansion and contraction of each resource pool are carried out independently, which is conducive to achieving more refined resource on-demand requests and elasticity.

[0004] In a storage-and-computing separation architecture, persistent storage resources are relied upon for reliability and fault tolerance, while a memory cache pool is used to cache data in persistent storage for rapid response. Furthermore, data in the remote memory cache pool can be shared by multiple compute nodes, which helps reduce storage costs but also introduces cache data consistency issues. Maintaining and facilitating cache data consistency directly impacts the throughput and response latency of database applications, and is crucial to application performance and scalability. Reducing data transmission latency while maintaining cache data consistency is a major technical challenge facing the storage-and-computing separation architecture. Summary of the Invention

[0005] Various aspects of the present application provide a memory cache pool maintenance method, device, system, and storage medium for reducing data transmission delays while maintaining cache data consistency.

[0006] An embodiment of the present application provides a computing node, including: a first computing unit and a first processing unit, wherein the first computing unit is interconnected with the first processing unit; the first computing unit is used to run an upper-layer application and provide a local memory cache pool for caching page data for the upper-layer application, and the local memory cache pool can be directly accessed by the first processing unit; the first processing unit is also network-connected to a second processing unit in at least one memory node, and is used to interact with the second processing unit to synchronize page data and / or page status between the local memory cache pool and a shared memory cache pool provided by the at least one memory node for the upper-layer application.

[0007] An embodiment of the present application provides a memory node, comprising: a second computing unit and a second processing unit, wherein the second computing unit is interconnected with the second processing unit; the second computing unit is used to provide a shared memory cache pool for an upper-layer application running on at least one computing node, and the shared memory cache pool can be directly accessed by the second processing unit; the second processing unit is also network-connected to the first processing unit in at least one computing node, and is used to interact with the first processing unit to synchronize page data and / or page status between the shared memory cache pool and a local memory cache pool provided by the at least one computing node for the upper-layer application.

[0008] An embodiment of the present application also provides a memory cache pool maintenance method, which is applied to a computing node, wherein the computing node includes a first computing unit and a first processing unit, the first processing unit being interconnected with the first computing unit, and being network-connected with a second processing unit in at least one memory node. The method includes: the first processing unit interacting with the second processing unit in the at least one memory node to synchronize page data and / or page status between a local memory cache pool provided by the first computing unit for an upper-layer application and a shared memory cache pool provided by the at least one memory node for the upper-layer application; wherein the local memory cache pool can be directly accessed by the first processing unit.

[0009] An embodiment of the present application also provides a memory cache pool maintenance method, which is applied to a memory node, wherein the memory node includes a second computing unit and a second processing unit, the second processing unit being interconnected with the second computing unit, and being network-connected with the first processing unit in at least one computing node. The method includes: the second processing unit interacting with the first processing unit in the at least one computing node to synchronize page data and / or page status between a shared memory cache pool provided by the memory node for the upper-layer application and a local memory cache pool provided by the at least one computing node for the upper-layer application; wherein the shared memory cache pool can be directly accessed by the second processing unit.

[0010] An embodiment of the present application also provides a storage and computing separation system, comprising: the above-mentioned multiple computing nodes, the above-mentioned at least one memory node and at least one storage node; wherein, the at least one storage node is used to persistently store page data in the shared memory cache pool and / or the local memory cache pool.

[0011] An embodiment of the present application also provides a processing unit, which includes: a processing module, a network card module and a storage module, wherein a computer program is stored in the storage module, and the processing module executes the computer program stored in the storage module to implement the steps in the memory cache pool maintenance method.

[0012] An embodiment of the present application further provides a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, the processor is enabled to implement the steps in the memory cache pool maintenance method.

[0013] In an embodiment of the present application, for a storage-computing separation architecture, a processing unit interconnected with the computing unit is added to the computing node and the memory node, and the consistency maintenance task of the memory cache data is pushed down to the processing unit for execution, rather than being completed on the computing unit. Since the processing unit has the ability to directly access the local memory cache pool or the shared memory cache pool, the data transmission process in the memory cache data consistency maintenance process is mostly completed within the processing unit without being uploaded to the computing unit. This can eliminate the delay in data transmission between the computing unit and the network card, thereby achieving the purpose of reducing the data transmission delay in the process of maintaining cache data consistency. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0015] Figure 1 A schematic diagram of the structure of a storage and computing separation system provided in an embodiment of the present application;

[0016] Figure 2 A schematic diagram of the structure of another storage and computing separation system provided in an embodiment of the present application;

[0017] Figure 3 A schematic diagram illustrating an exemplary cache pool consistency maintenance method according to an embodiment of the present application;

[0018] Figure 4 An exemplary DSA-integrated CIPU slave node page status update flow chart provided in an embodiment of the present application;

[0019] Figure 5 An exemplary schematic diagram of cache pool consistency maintenance logic provided in an embodiment of the present application;

[0020] Figure 6 A comparison diagram of a dual-write process in the prior art and an exemplary dual-write process provided in an embodiment of the present application;

[0021] Figure 7 A signaling interaction diagram of an exemplary memory cache pool maintenance method provided in an embodiment of the present application;

[0022] Figure 8 This is a signaling interaction diagram of another memory cache pool maintenance method exemplified in this application;

[0023] Figure 9 This is a signaling interaction diagram of another memory cache pool maintenance method exemplified in this application;

[0024] Figure 10 A schematic diagram of the structure of a processing unit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0025] To make the purpose, technical solutions, and advantages of this application more clear, the technical solutions of this application will be clearly and completely described below in conjunction with the specific embodiments of this application and the corresponding drawings. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0026] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of relevant countries and regions, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0027] In response to the technical problem faced by the existing storage and computing separation architecture of how to reduce data transmission delay in the process of maintaining cache data consistency, in an embodiment of the present application, for the storage and computing separation architecture, a processing unit interconnected with the computing unit is added to the computing node and the memory node, and the memory cache data consistency maintenance task is pushed down to the processing unit for execution instead of being completed on the computing unit. Since the processing unit has the ability to directly access the local memory cache pool or the shared memory cache pool, the data transmission process in the memory cache data consistency maintenance process is mostly completed within the processing unit without being uploaded to the computing unit. This can eliminate the delay in data transmission between the computing unit and the network card, thereby achieving the purpose of reducing data transmission delay in the process of maintaining cache data consistency.

[0028] The following describes in detail the technical solutions provided by various embodiments of the present application in conjunction with the accompanying drawings.

[0029] Figure 1 This is a schematic diagram of the structure of a storage and computing separation system provided in an embodiment of the present application. Figure 1 As shown, the system includes: multiple computing nodes 10, at least one memory node 20 and at least one storage node 30.

[0030] In this embodiment, the device implementation form of the computing node 10, memory node 20, and storage node 30 is not limited. For example, the computing node 10 can be any device with computing capabilities, such as, but not limited to, a smartphone, a laptop, a desktop computer, a wearable device, a traditional server, a cloud server, a server cluster, etc. The memory node 20 can be any device capable of providing memory resources, such as, but not limited to, a computer, a traditional server, a cloud server, etc. Correspondingly, the storage node 30 can be any device capable of providing persistent storage resources, such as various storage devices.

[0031] In this embodiment, the computing node 10 primarily provides computing power for running upper-layer applications and provides a relatively limited local memory cache pool for the upper-layer applications to accommodate the various data that the upper-layer applications need to access frequently. In this embodiment, the type of upper-layer application is not limited and can be various applications with memory and persistent storage requirements, such as various cloud computing services, database instances, stream computing services, video processing services, etc. Of course, the data generated by different upper-layer applications will also vary. In this embodiment, the storage node 30 is responsible for providing persistent and reliable shared storage resources for the upper-layer applications. For example, if the upper-layer application is a database instance, it can store the database instance's write-ahead logging (WAL) data, database tables, and checkpoints. The memory node 20 serves as an intermediate layer between the local memory cache pool and persistent shared storage, primarily used to provide a shared memory cache pool for the upper-layer applications. The shared memory cache pool is an extension of the local memory cache pool. In this embodiment, the local memory cache pool and the shared memory cache pool are managed in the form of memory pages, and the data in these memory cache pools is referred to as page data.

[0032] like Figure 1 As shown, the computing nodes 10, memory nodes 20 and storage nodes 30 are interconnected through a network, and the network interconnection methods include but are not limited to: Ethernet, Remote Direct Memory Access (RDMA), etc. Among them, multiple computing nodes 10 can be distributed and deployed in different locations. Correspondingly, when there are multiple memory nodes 20, they can also be distributed and deployed in different locations. And when there are multiple storage nodes 30, they can also be distributed and deployed in different locations. Optionally, Figure 1 In the example, multiple computing nodes 10 form a computing cluster, at least one memory node 20 forms a memory storage cluster, and at least one storage node 30 forms a persistent storage cluster. It should be noted that managing various nodes in a cluster form is only an example and is not limited thereto.

[0033] In this embodiment, the computing node 10 includes a first computing unit 11 and a first processing unit 12 with network communication capability and computing capability, and the first computing unit 11 and the first processing unit 12 are interconnected; the memory node 20 includes a second computing unit 21 and a second processing unit 22 with network communication capability and computing capability, and the second computing unit 21 and the second processing unit 22 are interconnected. The first computing unit 11 and the second computing unit 21 can be any device with computing capability, such as but not limited to: a central processing unit (CPU), a data processing unit (DPU) and other chips or modules. The first processing unit 12 and the second processing unit 22 can be any device with network communication capability and computing capability, such as some cloud infrastructure units (CIPU) with integrated network card modules, smart network cards (Smart NIC), network interface cards (NIC), DPU, infrastructure processors (IPU) and other chips or modules. In Figure 1 In the figure, the first computing unit 11 and the second computing unit 21 are CPUs, and the first processing unit 12 and the second processing unit 22 are CIPUs are used as an example, but the present invention is not limited thereto.

[0034] In this embodiment, the first computing unit 11 and the second computing unit 21 have similar functions, primarily providing computing power for their respective nodes. However, due to the different functions of the computing node 10 and the memory node 20, their computing power and memory configurations differ. Similarly, the first processing unit 12 and the second processing unit 22 have similar functions, primarily providing memory cache consistency maintenance services for their respective nodes. However, due to the different functions of the computing node 10 and the memory node 20, their computing power, network capabilities, and memory configurations differ.

[0035] In this embodiment, if Figure 2As shown, the first computing unit 11 is responsible for running the upper-layer application on the computing node 10 to which it belongs, and provides the upper-layer application with a local memory cache pool for caching page data, and is responsible for the management of the local memory cache pool, such as the allocation, initialization and configuration of the local memory cache pool. Furthermore, during the operation of the upper-layer application, the first computing unit 11 can also receive user requests and respond to user requests. Depending on the upper-layer application, the user request and the way of responding to the user request will be different, and the embodiment of the present application does not focus on this. The upper-layer application can be any application running on the computing node 10 and requiring data caching through the local memory cache pool and the shared memory cache pool provided by the memory node 20, such as but not limited to a database instance. In the computing node 10, the first computing unit 11 can run one or more upper-layer applications, and will provide a corresponding local memory cache pool for each upper-layer application. Accordingly, as Figure 2 As shown, the second computing unit 21 in the memory node 20 is responsible for providing a shared memory cache pool for upper-layer applications running on at least one compute node 10 and managing the shared memory cache pool, such as allocation, initialization, and configuration of the shared memory cache pool. It should be noted that the correspondence between memory nodes 20 and compute nodes 10 can be one-to-one, many-to-one, or one-to-many. That is, a memory node 20 can provide a shared memory cache pool for upper-layer applications on one or more compute nodes 10, and a compute node 10 can use one or more memory nodes 20 to provide its shared memory cache pool. The correspondence between compute nodes 10 and memory nodes 20 can be maintained in advance.

[0036] Further, if Figure 2 As shown, the first computing unit 11 also maintains metadata of the local memory cache pool. These metadata are data required for managing the local memory cache pool, including but not limited to: free lists, various linked lists, page status information (such as invalidation, exclusive, shared, etc.), and address mapping tables. Figure 2As shown, the second computing unit 21 maintains metadata of the shared memory cache pool. These metadata are data required for managing the shared memory cache pool, including but not limited to: free lists, various linked lists, page status information, and address mapping tables. Among them, whether it is the metadata of the local memory cache pool or the metadata of the shared memory cache pool, the various linked lists in these metadata include but are not limited to: page access information maintenance linked lists, such as the Least Recently Used (LRU) linked lists, linked lists for storing dirty data, free linked lists, etc. The address mapping table is used to store the mapping relationship between the physical address and the logical address of the page data. As the local memory cache pool or the shared memory cache pool is accessed, the corresponding metadata will also be updated synchronously.

[0037] In this embodiment, a first processing unit 12 is added to the computing node 10. The first processing unit 12 is interconnected with the first computing unit 11 via an interconnection channel. Based on the interconnection channel, the local memory cache pool and its metadata can be directly accessed without passing through the first computing unit 11. For example, the first processing unit 12 can directly read page data from the local memory cache pool, or directly write page data to the local memory cache pool; it can also directly read metadata related to the memory cache data consistency maintenance process from the metadata of the local memory cache pool, or modify the metadata related to the memory cache data consistency maintenance process. Correspondingly, a second processing unit 22 is added to the memory node 20. The second processing unit 22 is interconnected with the second computing unit 21 via an interconnection channel. Based on the interconnection channel, the shared memory cache pool and its metadata can be directly accessed without passing through the second computing unit 21. For example, the second processing unit 22 can directly read page data from the shared memory cache pool in the memory node 20 to which it belongs, or directly write page data to the shared memory cache pool; it can also directly read metadata related to the memory cache data consistency maintenance process from the metadata of the shared memory cache pool, or modify the metadata related to the memory cache data consistency maintenance process.

[0038] In this embodiment, the implementation method of the interconnection channel is not limited, for example, it can be but not limited to: a peripheral component interconnect express (PCIe) channel, or a cache consistency channel. Preferably, the first processing unit 12 and the first computing unit 11, as well as the second processing unit 22 and the second computing unit 21 are interconnected using a cache consistency channel. The embodiment of the present application can adopt some existing cache consistency channels, such as the Ultra Path Interconnect (UPI) channel, the Compute Express Link (CXL) channel or the Cache Coherent Interconnect for Accelerators (CCIX) channel, or a self-developed cache consistency channel, which is not limited.

[0039] As the upper-layer application runs, the data it generates will increase. When the local memory cache pool is insufficient, the old page data can be swapped out of the local memory cache pool through the page replacement mechanism, and the swapped-out page data can be cached in the shared memory cache pool provided by one or more memory nodes 20. Among them, the page replacement mechanism can be executed by the first computing unit 11, or by the first processing unit 12, and there is no limitation on this. In the case where the page replacement mechanism is executed by the first computing unit 11, the first computing unit 11 can monitor the usage or attribute information of the page data in the local memory cache pool according to the relevant requirements of the page replacement mechanism, find the page data that needs to be replaced from the local memory cache pool, and then notify the first processing unit 12, which directly reads the page data that needs to be replaced from the local memory cache pool and provides the page data to the second processing unit 22 in the corresponding memory node 20, and the second processing unit 22 in the memory node 20 writes the page data into the shared memory cache pool of the memory node 20. Preferably, based on the direct access capability of the first processing unit 12 to the local memory cache pool, the page replacement mechanism can be executed by the first processing unit 12. Specifically, the first processing unit 12 can monitor the usage or attribute information of the page data in the local memory cache pool according to the relevant requirements of the page replacement mechanism, find the page data that needs to be replaced from the local memory cache pool, and then directly read the page data that needs to be replaced from the local memory cache pool and provide the page data to the second processing unit 22 in the corresponding memory node 20, and the second processing unit 22 in the memory node 20 writes the page data into the shared memory cache pool of the memory node 20. The embodiment of the present application does not limit the specific implementation method of the page replacement mechanism. For example, it can be a traditional least recently used (Least Recently Used, LRU) method, or it can flexibly define the page replacement mechanism used in combination with some information of the upper-layer application, so that the first computing unit 11 or the first processing unit 12 can perform page replacement based on some attribute information of the page data, such as page type.

[0040] In addition, in the storage and computing separation architecture, the same upper-layer application may need to run on multiple different computing nodes 10 at the same time, or multiple computing nodes 10 may need to cooperate with each other, which means that multiple computing nodes 10 need to share the same page data, which involves the issue of data consistency between the shared memory cache pool and the local memory cache pool, ensuring that each computing node 10 can use the correct page data.

[0041] In this embodiment, for any computing node 10, its first processing unit 12 has network communication capabilities and computing capabilities, is network-connected to the second processing unit 22 in at least one memory node 20, and can cooperate with the second processing unit 22 in at least one memory node 20. The cooperation here mainly refers to the first processing unit 12 and the second processing unit 22 performing data interaction to synchronize page data and / or page status between the local memory cache pool and the shared memory cache pool provided by at least one memory node 20 for the upper-layer application, thereby achieving memory cache data consistency. Correspondingly, for any memory node 20, its second processing unit 22 has network communication capabilities and computing capabilities, is network-connected to the first processing unit 12 in at least one computing node 10, and can interact with the first processing unit 12 to synchronize page data and / or page status between the shared memory cache pool and the local memory cache pool provided by at least one computing node 10 for the upper-layer application, thereby achieving data consistency.

[0042] Alternatively, as Figure 2 As shown, the first processing unit 12 can run a local cache pool manager to implement a memory cache consistency maintenance function. Specifically, the local cache pool manager is responsible for managing the local memory cache pool. When the local memory cache pool needs to refresh dirty page data or read new page data, it performs fast reading and writing to the shared memory cache pool, and synchronizes the page status during the reading and writing process. Figure 2 As shown, the second processing unit 22 can run a remote cache pool manager to maintain memory cache consistency. Specifically, the remote cache pool manager is responsible for receiving requests from the local cache pool manager for checkpoints, flushing dirty page data, reading new page data, and responding to these requests based on access to the shared memory cache pool. Furthermore, the remote cache pool manager synchronizes page states during read and write operations. Furthermore, the remote cache pool manager is also responsible for rapidly recovering compute nodes by utilizing page data and checkpoints in the remote shared memory cache pool in the event of a compute node failure. Accordingly, the remote cache pool manager is also responsible for reading checkpoints, WAL logs, and other data from the persistent shared storage node 30 to provide data support for compute node recovery in the event of a compute node failure.

[0043] In this embodiment, the first processing unit 12 is a hardware structure that can directly access the local memory cache pool on the computing node 10 where it is located through an interconnection channel (such as a cache consistency channel). The local memory cache pool stores user-state data generated by upper-layer applications. In other words, the first processing unit 12 can share user-state data generated by upper-layer applications, rather than kernel-state data, and the sharing of user-state data does not require the operating system (OS) of the computing node 10. Therefore, adding the first processing unit 12 to the computing node 10 enables the memory cache data consistency maintenance task to be implemented at the application layer, bypassing the operating system's protocol stack. During the cache data consistency maintenance process, the data access characteristics of the upper-layer applications can be fully utilized, thereby improving the transmission performance of data consistency maintenance. For example, in the page replacement mechanism, more application-layer data access characteristics can be considered, rather than simply based on information such as the time and number of page accesses. For example, based on the type of page data, some page data with a low access rate can be determined, and these page data can be preferentially replaced from the local memory cache pool without relying on information such as the access time and number of these page data.

[0044] Next, the process of synchronizing page data and / or page status between the local memory cache pool and the shared memory cache pool by cooperating with the first processing unit 12 and the second processing unit 22 will be described in detail. The first processing unit 12 and the second processing unit 22 cooperate with each other to synchronize page data and / or page status between the local memory cache pool and the shared memory cache pool, which can be summarized as follows:

[0045] Case 1: Writing page data to the shared memory cache pool;

[0046] Case 2: Read page data from the shared memory cache pool;

[0047] Case 3: Add a read lock to the page data;

[0048] Case 4: Add write lock to page data;

[0049] Case 5: Invalidate the page data.

[0050] The following describes in detail situations 1-5 from the perspective of maintaining data consistency between any compute node and any memory node.

[0051] For case 1: the first processing unit 12 of the first computing node reads the first page data from the local memory cache pool and sends the first page data to the second processing unit 22 in the first memory node; the second processing unit 22 in the first memory node writes the first page data to the shared memory cache pool in the first memory node.

[0052] For case 2: the second processing unit 22 in the second memory node reads the second page data from the shared memory cache pool of the second memory node and sends it to the first processing unit 12 of the first computing node; the first processing unit 12 of the first computing node receives the second page data sent by the second processing unit 22 in the second memory node, and writes the second page data into the local memory cache pool.

[0053] For case 3: Continuing from case 2, the first processing unit 12 of the first computing node sends a request for a read lock to the second processing unit 22 in the second memory node before receiving the second page data, so that the second processing unit 22 in the second memory node adds a read lock for the second page data.

[0054] For situations 4 and 5: before the first computing unit 12 in the third computing node rewrites the third page data in the local memory cache pool, a request for adding a write lock and invalidating the third page data is sent to the second processing unit 22 in the third memory node; the second processing unit 22 in the third memory node adds a write lock to the third page data in the shared memory cache pool and notifies other computing nodes in the local memory cache pool that contain the third page data to invalidate the third page data.

[0055] Further optionally, before the first computing unit 12 in the third computing node rewrites the third page data in the local memory cache pool, it sends a request for adding a write lock to the third page data to the second processing unit 22 in the third memory node; the second processing unit 22 in the third memory node adds a write lock to the third page data in the shared memory cache pool, and returns confirmation information of adding the write lock; the first computing unit 12 in the third computing node sends a request to invalidate the third page data to the second processing unit 22 in the third memory node; the second processing unit 22 in the third memory node notifies other computing nodes in the local memory cache pool that contain the third page data to invalidate the third page data, and returns confirmation information of the invalidation to the second processing unit 22 in the third memory node after receiving the confirmation information returned by the other computing nodes.

[0056] In the above, the first computing node, the second computing node, and the third computing node are any computing nodes, and may be the same computing node or different computing nodes; accordingly, the first memory node, the second memory node, and the third memory node are any memory nodes, and may be the same memory node or different memory nodes.

[0057] In this embodiment, the internal implementation forms of the first processing unit and the second processing unit are not limited. Figure 2 As shown, the first processing unit 12 includes a first processing module 121 and a first network interface card module 122; correspondingly, the second processing unit 22 includes a second processing module 221 and a second network interface card module 222. Furthermore, the first processing module 121 and the second processing module 221 can be any device with computing capabilities, such as a Domain Specific Architecture (DSA) module or chip. The first network interface card module 122 and the second network interface card module 222 can be NICs, but are not limited to such.

[0058] The following combination Figure 2 The detailed implementation structure of the first processing unit 12 and the second processing unit 22 is shown, and the processes of the above situations 1-5 are further described in detail.

[0059] For situation 1 of writing page data into the shared memory cache pool, the first processing module in the first computing node reads the first page data from the local memory cache pool, and transmits the first page data to the second processing module in the first memory node via the first network card module in the first computing node and the second network card module in the first memory node; the second processing module in the first memory node writes the first page data into the shared memory cache pool in the first memory node, thereby realizing the writing of page data from the local memory cache pool to the shared memory cache pool.

[0060] Exemplarily, in order to improve the write performance of writing page data into the shared memory cache pool, the first processing module in the first computing node is used to: read the first page data from the local memory cache pool, and send it to the second network card module in the first memory node through the first network card module, so that the second processing module in the first memory node writes the first page data into the shared memory cache pool in the first memory node.

[0061] Correspondingly, the second processing module in the second processing unit in the first memory node is used to: receive the first page data sent by the first network card module in the first computing node through the second network card module in the second processing unit, and write the first page data into the shared memory cache pool in the first memory node.

[0062] In this embodiment, the conditions under which the first processing module of the first computing node reads the first page data from the local memory cache pool are not limited. In an optional embodiment, the page replacement mechanism is executed by the first computing unit in the first computing node. The first computing unit in the first computing node can determine whether there is page data in the local memory cache pool that needs to be eliminated and is in a modified state based on the page replacement mechanism. If so, the page data that needs to be eliminated and is in a modified state is used as the first page data, and then send a dirty page write-back instruction to the first processing module in the first computing node. Accordingly, the first processing module in the first computing node is specifically configured to respond to the dirty page write-back instruction sent by the first computing unit in the first computing node and read the first page data from the local memory cache pool. The description of the "modified state" can be found in the description of the page data state example below and will not be described in detail here. Alternatively, in an optional embodiment, the page replacement mechanism is executed by the first processing module in the first computing node. The first processing module in the first computing node can determine whether there is first page data in the local memory cache pool that needs to be eliminated and is in a modified state based on the page replacement mechanism. If so, the first page data is read from the local memory cache pool. In the aforementioned example, the first page data is dirty page data that needs to be written back, but the scenario where page data needs to be written into the shared memory cache pool is not limited to writing back dirty page data.

[0063] For situation 2 of reading page data from the shared memory cache pool, the second processing module in the second memory node reads the second page data from the shared memory cache pool, and transmits it to the first network card module in the second computing node via the second network card module in the second memory node. The first network card module in the second computing node provides the second page data to the first processing module in the second computing node, and the first processing module in the second computing node writes the second page data to the local memory cache pool in the second computing node, thereby realizing the reading of page data from the shared memory cache pool on the memory node side.

[0064] Exemplarily, to improve the performance of reading page data from a shared memory cache pool, the second processing module in the second memory node is configured to: read the second page data from the shared memory cache pool, and send the second page data to the first network card module in the second computing node via the second network card module in the second memory node, so that the first processing module in the second computing node can write the second page data into the local memory cache pool of the second computing node. Correspondingly, the first processing module in the second computing node is configured to: receive the second page data sent by the second network card module in the second memory node via the first network card module in the second computing node, and write the second page data into the local memory cache pool.

[0065] In this embodiment, the conditions under which the second processing module in the second memory node reads the second page data from the shared memory cache pool are not limited. In an optional embodiment, the first processing module in the second computing node can respond to the page read instruction sent by the first computing unit in the first computing node and send a page read request to the second processing module in the second memory node through the first network interface card module of the first computing node, so that the second processing module in the second memory node reads the second page data from the shared memory cache pool of the second memory node and returns the second page data to the first processing module in the second computing node through the second network interface card module in the second memory node and the first network interface card module in the second computing node, and the first processing module in the second computing node writes the second page data to the local memory cache pool in the second computing node.

[0066] For the first computing unit in the second computing node, during the execution of the upper-layer application, the local memory cache pool can be queried based on the executed instruction code to determine whether the required page data exists in the local memory cache pool. In this embodiment, multiple states can be maintained for the page data in the local memory cache pool and the shared memory cache pool, including but not limited to: modified state, exclusive state, shared state, invalidated state, and write lock and read lock states. These page data states are stored in the metadata of the local memory cache pool and the metadata of the shared memory cache pool. Among them, the modified state indicates that the page data has been modified in the local memory cache pool of the current computing node, but has not been synchronized back to the shared memory cache pool; the exclusive state indicates that the page data is exclusively owned by the current computing node, and the same page data in the local memory cache pools of other computing nodes is in an invalid state; the shared state indicates that the page data can be shared by multiple computing nodes and is in a valid state; the invalidated state indicates that the page data is outdated and cannot be used; the write lock state is similar to the exclusive state, indicating that the page data is exclusively owned by the current computing node, and the current computing node can modify the page data, and the same page data in the local memory cache pools of other computing nodes is in an invalid state; the read lock state indicates that the page data can be read by the current computing node, and other computing nodes are not allowed to modify the page data.

[0067] Specifically, during the operation of the upper-layer application, when the second page data needs to be loaded, the first computing unit in the second computing node can query the local memory cache pool to determine whether there is readable second page data; if not, a page read instruction is sent to the first processing module in the second computing node to read the second page data from the shared memory cache pool of the second memory node. Alternatively, during the operation of the upper-layer application, when the second page data needs to be rewritten, the first computing unit in the second computing node can query the local memory cache pool to determine whether there is rewritable second page data; if so, the second page data in the local memory cache pool is directly rewritten; if not, a page read instruction is sent to the first processing module in the second computing node to read the second page data from the shared memory cache pool of the second memory node, and then the second page data read from the shared memory cache pool is rewritten.

[0068] In this embodiment, the situation where there is no readable second page data and no rewritable second page data in the local memory cache pool is exemplified, but is not limited to the following situations. For example, the situation where there is no readable second page data in the local memory cache pool includes any of the following situations: there is no second page data in the local memory cache pool; there is second page data in the local memory cache pool that has been added a write lock by other computing nodes; there is second page data in the local memory cache pool that is marked as invalid. Correspondingly, the situation where there is no rewritable second page data in the local memory cache pool includes any of the following situations: there is no second page data in the local memory cache pool; there is second page data in the local memory cache pool that has not been added a write lock by the second computing node. That is to say, in this example, in order to maintain data consistency, the second page data in the local memory cache pool can only be rewritten (or modified) by the first computing unit in the second computing node if a write lock is added by the second computing node.

[0069] Further optionally, in the above process, when the first computing unit in the second computing node needs to rewrite the second page, if the second page data does not exist in the local memory cache pool, the first computing unit can determine whether the second page data involved in this rewrite operation is existing page data based on the parameters of this rewrite operation; if the second page data is existing page data, send a page read instruction to the first processing module in the second computing node to read the second page data from the shared memory cache pool of the second memory node. If the second page data that the first computing unit in the second computing node needs to rewrite is not existing page data, that is, the second page data that the first computing unit in the second computing node needs to write to the local memory cache pool is new page data, then the second page data can be directly written to the local memory cache pool. Furthermore, the first computing unit in the second computing node may also determine whether the shared memory cache pool in the second memory node and the local memory cache pool are in an inclusion relationship. If the shared memory cache pool in the second memory node and the local memory cache pool are in a full inclusion relationship, the first computing unit may send a memory allocation request to the first processing module in the second computing node, so that the first processing module can send a memory allocation request to the second processing module in the second memory node via the first network card module of the second computing node, so that the second processing module in the second memory node can request the second computing unit in the second memory node to allocate memory space from the shared memory cache pool for the new second page data, to cache the second page data that is subsequently synchronized. If the shared memory cache pool in the second memory node and the local memory cache pool are in a partial inclusion relationship, the second computing unit in the second memory node may allocate memory space for the second page data in real time upon receiving the second page data synchronized from the second computing node. A full inclusion relationship means that all page data in the local memory cache pool of each computing node is stored in the shared memory cache pool of at least one memory node, and a partial inclusion relationship means that not all page data in the local memory cache pool of each computing node is necessarily stored in the shared memory cache pool. The inclusion relationship between the shared memory cache pool and the local memory cache pool may be pre-configured or determined.

[0070] For case 3 of adding a read lock to page data, the first processing module in the second computing node and the second processing module in the second memory node cooperate with each other to add a read lock to the second page data to be read in the shared memory cache pool.

[0071] Exemplarily, in order to improve the locking performance of read lock processing for page data, the first processing module in the second computing node is used to: before receiving the second page data, send a read lock request to the second processing module in the second memory node, so that the second processing module in the second memory node adds a read lock to the second page data.

[0072] Correspondingly, the second processing module in the second memory node is used to: before reading the second page data from the shared memory cache pool, receive the request for adding a read lock sent by the first network card module in the second computing node through the second network card module in the second memory node, and add a read lock for the second page data.

[0073] Exemplarily, the process of adding a read lock to the second page data by the second processing module in the second memory node includes: the second processing module in the second memory node determines whether a write lock has been added to the second page data by other computing nodes through the metadata of the shared memory cache pool; if a write lock has not been added to the second page data by other computing nodes, the second processing module can directly add a read lock to the second page data, and record relevant information about adding the read lock to the second page data in the metadata of the shared memory cache pool. The relevant information about adding the read lock includes information such as which computing node added the read lock to the second page data and the time when the read lock was added. In the case where the second page data has been write-locked by other computing nodes, the second processing module in the second memory node initiates an unlocking request to the computing node that has added the write lock to the second page data through the second network card module; the computing node that has added the write lock to the second page data receives the unlocking request through its first network card module, and its first processing module determines whether the second page data can be unlocked. If it is determined that the second page data can be unlocked, the first network card module sends an unlocking confirmation message to the second network card module of the second memory node. After receiving the unlocking confirmation message provided by the second network card module, the second processing module of the second memory node unlocks the second page data, that is, deletes the write lock on the second page data and synchronously updates the metadata of the shared memory cache pool, and then re-adds a read lock to the second page data, and records the relevant information of adding the read lock to the second page data in the metadata of the shared memory cache pool.

[0074] For example, with respect to situations 4 and 5 of page data write locking and invalidation, to ensure data consistency, before the first computing unit in the third computing node rewrites the third page data in the local memory cache pool, the first processing module in the third computing node and the second processing module in the third memory node can cooperate with each other to complete the write locking and invalidation operations on the third page data in the shared memory cache pool. Write locking the third page data refers to the process of adding a write lock to the third page data, and invalidating the third page data refers to the process of notifying other computing nodes using the third page data, except the third computing node, to invalidate the third page data in the local memory cache pool in order to wait for the latest third page data.

[0075] Exemplarily, in order to improve the performance of adding write locks and invalidating page data, the first processing module in the third computing node is used to: send a request for adding write locks and invalidating the third page data to the second processing module in the third memory node through the first network card module in the third computing node, so that the second processing module in the third memory node adds a write lock to the third page data in the shared memory cache pool and notifies other computing nodes in the local memory cache pool that contain the third page data to invalidate the third page data.

[0076] Correspondingly, the second processing module in the third memory node is used to: receive the request sent by the first processing module in the third computing node through the second network card module in the third memory node to add a write lock and invalidate the third page data in the shared memory cache pool, add a write lock to the third page data and notify other computing nodes in the local memory cache pool that contain the third page data to invalidate the third page data.

[0077] Optionally, the first processing module in the third computing node can send a request for adding and writing locks and a request for invalidation at the same time, and accordingly, the second processing module in the third memory node can perform add and write lock processing and invalidation processing on the third page data in sequence. Alternatively, optionally, the first processing module in the third computing node first sends a request for adding and writing locks to the second processing module in the third memory node, the second processing module in the third memory node performs add and write lock processing on the third page data, and notifies the first processing module in the third computing node after completing the add and write lock processing; then, the first processing module in the third computing node sends an invalidation request to the second processing module in the third memory node, the second processing module in the third memory node determines other computing nodes in the local memory cache pool that contain the third page data through the metadata in the shared memory cache pool, and sends an invalidation notification to the first processing modules of the other computing nodes to notify the first processing modules of the other computing nodes to invalidate the third page data in the local memory cache pool. Among them, invalidating the third page data in the local memory cache pool can specifically be marking the third page data in the local memory cache pool as invalid. Of course, other invalidation methods can also be used, such as deleting the third page data.

[0078] See also Figure 3 , taking the integrated CPU and CIPU in computing nodes and memory nodes as an example, the data consistency maintenance process involving multiple computing nodes is explained. Figure 3 Only the CIPU is shown in the figure, and the CPU is not shown. Figure 3In the present invention, a DSA module is integrated into the CIPU of the compute node and memory node, and a local cache pool management module or a remote cache pool management module runs on the DSA module. Of course, a network card module (such as a NIC) can also be integrated into the CIPU, and the network card module has two interfaces (not shown in the figure): receive (Rx) and transmit (Tx). The DSA module provides programmability, which enables greater flexibility in functional implementation. Relatively speaking, the first computing unit (such as the CPU) belongs to the compute (CPU) domain; the CIPU belongs to the network domain and can access the local memory cache pool in the compute (CPU) domain through a cache coherence channel. In this way, when the NIC receives page data transmitted from the network, it can directly process it by the local cache pool management module running on the DSA module instead of reporting it to the CPU through the input / output (IO) channel between the NIC and the CPU. Similarly, page data that needs to be sent after processing by the DSA module can also be sent directly through the NIC, without having to be uploaded to the CPU through the channel with the CPU for processing. The cache coherence channel provides a more efficient channel for the DSA module to access the local memory cache pool than the I / O channel, especially for data structures such as hash tables and linked lists that require indirect and discrete address access. Because the DSA and NIC are both located on the CIPU and are tightly coupled, the DSA can change the NIC's behavior in real time by adjusting the NIC's control information.

[0079] In this embodiment, the entire consistency maintenance operation is completed by CIPU, and there is no need to report to the CPU across IO channels. The entire consistency maintenance process omits the delay of IO channels. Specifically, when a computing node confirms a transaction, if the computing node finds that the page data involved in the transaction is not unique to the computing node, it needs to synchronize the status of other computing nodes. Figure 3 In ①, the local cache pool manager of computing node A needs to send a transaction request to the remote cache pool manager of remote memory node D. The transaction request includes the metadata of the page data involved in the transaction. Figure 3 As shown in ②, the remote cache pool manager of the remote memory node sends a transaction notification to the other computing nodes B and C involved in the transaction. After receiving the transaction notification, the other computing nodes B and C need to update the status of the page data involved. Figure 3 As shown in ③, other computing nodes B and C send confirmation information to the remote cache pool manager of the remote memory node D. Figure 3 As shown in ④, after receiving confirmation information from all other computing nodes B and C, the remote cache pool manager of the remote memory node D sends a confirmation message to the local cache pool manager on the computing node A that originally issued the request. Figure 3As shown in step ⑤, after receiving the confirmation information, the local cache pool manager of the computing node A that issued the request performs the transaction confirmation operation.

[0080] The data consistency maintenance transaction involving multiple computing nodes may be, but is not limited to, a transaction that invalidates page data. Taking invalidating page data as an example, Figure 3 The transaction process shown is as follows: The CIPU of compute node A sends a cancellation request to memory node D for the page data to be cancelled. Memory node D refers to the memory node in the shared memory cache pool that stores the page data to be cancelled. Compute node A can determine the memory node D where the page data to be cancelled is located based on the metadata of the local memory cache pool and other related information, such as the maintained correspondence between it and each memory node and the page data stored in the shared memory cache pool of each memory node. After receiving the cancellation request, the CIPU of memory node D determines the other compute nodes in the local memory cache pool that contain the page data to be cancelled, namely, compute nodes B and C, based on the metadata of the shared memory cache pool and other related information. It then sends cancellation notifications to compute nodes B and C respectively, and after receiving cancellation confirmations from compute nodes B and C, it sends a cancellation confirmation to compute node A. After receiving the cancellation confirmation from memory node D, compute node A notifies its CPU to perform a rewrite operation on the page data, completing the cancellation transaction.

[0081] It should be noted that the embodiment of the present application does not limit the internal processing logic of the first processing unit (such as CIPU) in the computing node and the second processing unit (such as CIPU) in the memory node after receiving the request or page data. Any data processing method that does not require reporting to the CPU across the IO channel is applicable to the embodiment of the present application. Figure 4 , an exemplary description is given of the internal processing process of the first processing unit in the computing node or the second processing unit (such as CIPU) in the memory node receiving the page data.

[0082] Specifically, Figure 4 The processing flow after a computing node receives a page status update request is shown. First, a network packet is received through the NIC interface. The metadata related to the page status update may be divided into one or more network packets for transmission. The number of network packets into which the page metadata is divided is related to the receiving capacity of the NIC and the size of the page metadata. It is explained here that when the computing node receives page data, the page data can also be divided into multiple network packets for transmission. In the embodiment of the present application, the DAS module has programmable capabilities, can support page data of various sizes, and can be flexibly adapted to upper-layer applications. Figure 4In this example, a page metadata is split into multiple network packets. On the DAS module, a background receiving thread assembles the network packets. After obtaining the entire page metadata, it pushes the page metadata onto the stack, writes it to the log metadata queue, and notifies the cache pool maintenance thread. The cache pool maintenance thread reads the page metadata from the log metadata queue in a first-in-first-out manner and updates the metadata of the CPU domain's local memory cache pool directly through the cache coherence channel, simultaneously updating the WAL log data. After completing the page status update, the cache pool maintenance thread returns an acknowledgment message to the background receiving thread. It should be noted that if acknowledgment information is required to be returned to the peer, a network packet containing the acknowledgment information can also be sent externally through the NIC interface. All of the above operations are performed on the DAS module and do not require reporting to the CPU via the I / O channel. In other words, most operations are completed in the CIPU domain, and the updated local memory cache pool metadata is immediately visible to the CPU domain. Furthermore, because the DAS module and NIC interface are tightly coupled on the CIPU, network packets are no longer reported to the CPU via the I / O channel for processing, eliminating the latency associated with I / O channel transmission and copying.

[0083] In some optional embodiments, there is at least one upper-layer application in each computing node, and each upper-layer application corresponds to a local memory cache pool. In this embodiment, the data consistency maintenance task is pushed down to the first processing unit, which means that the page data that needs to be written to the local memory cache pool corresponding to each upper-layer application or other data that needs to be given to each upper-layer application (such as notification messages) will be received by the first network card module in the first processing unit. Based on this, in order to improve the timeliness and efficiency of the first network card module receiving data, the first processing module in the computing node can poll the receiving queue of the first network card module; when there is data to be processed in the receiving queue, the data to be processed is read from the receiving queue, the upper-layer application to which the data to be processed belongs is determined, and the data to be processed is written to the local memory cache pool corresponding to the upper-layer application or the metadata of the local memory cache pool, so that the first computing unit can process the data to be processed, and the data to be processed includes page data or notification messages.

[0084] See also Figure 5, assuming that multiple virtual machine (VM) instances are deployed on a computing node, in the traditional mode, each virtual machine maintains its own receiving queue and adopts the pooling mode to send and receive network card messages. The pooling mode refers to the use of polling to send and receive network card messages, avoiding the response delay caused by the interruption method, so as to improve the network card sending and receiving performance. For delay-sensitive applications, the pooling operation requires an independent CPU core to complete, which will cause a waste of CPU resources. In an embodiment of the present application, after the relevant cache pool consistency maintenance logic is pushed down to the first processing unit or the second processing unit (such as CIPU), the pooling task of each VM instance is also pushed down according to the bandwidth of the network communication, and can be performed by the CPU core specified by the first processing unit or the second processing unit (such as the DSA module in the CIPU). At this time, the CPU core required to execute the pooling task on the DSA only needs to meet the bandwidth requirements, and multiple CPU cores are no longer required, which can further improve the energy efficiency of the pooling task and save CPU resources.

[0085] In practical applications, when a compute node's local memory cache pool contains a large amount of dirty page data, it is necessary to promptly write the dirty page data back to the remote memory node's shared memory cache pool. In this case, the dirty page refresh rate severely impacts system performance. Writing dirty page data back to the shared memory cache pool is a specific application scenario for writing page data to the shared memory cache pool. The first page data mentioned above can be the dirty page data that needs to be written back.

[0086] Based on the above, if the first page data in the above text is dirty page data that needs to be written back, the first processing module in the first computer node can write the first page data into the local double-write buffer area, and send the first page data in the local double-write buffer area (Doublewrite Buffer) to the second processing module on the first memory node through the first network card module in the first computer node, so that the second processing module in the first memory node writes the first page data into the double-write buffer area on the first memory node and points the address pointer pointing to the first page data in the shared memory buffer pool of the first memory node to the double-write buffer area of the first memory node. Correspondingly, the second processing module in the first memory node is also used to: when receiving the first page data, write the first page data into the local double-write buffer area, and point the address pointer pointing to the first page data in the shared memory buffer pool to the local double-write buffer area to read the latest first page data from the local double-write buffer area. By exchanging address pointers, one write operation can be reduced, which is conducive to improving the write-back efficiency of dirty page data.

[0087] in, Figure 6 The left side of the figure shows the traditional write-back process. To ensure the atomicity of page data, a double write mechanism is required. Specifically, in step 1, dirty page data in the compute node's local memory cache pool is written to the local Doublewrite Buffer. Then, in step 2, the dirty page data in the compute node's local Doublewrite Buffer is written to the Doublewrite Buffer on the remote memory node. Finally, in step 3, the dirty page data in the compute node's local Doublewrite Buffer is written to the shared memory cache pool on the remote memory node. This requires two write operations to the remote memory node for each dirty page write-back: steps 2 and 3, significantly increasing latency.

[0088] By analogy, in this embodiment, after adding processing units (such as CIPU) to the computing nodes and memory nodes, the problems existing in the traditional double write mechanism can be effectively eliminated. Figure 6The right side of the figure shows the improved write-back process of this embodiment. Referring to step ①, the dirty page data on the local memory cache pool of the computing node is written to the local Doublewrite Buffer; then, referring to step ②, the dirty page data in the local Doublewrite Buffer of the computing node is written to the Doublewrite Buffer on the remote memory node; then, as in step ③, the address information pointing to the dirty page data is modified in the metadata of the shared memory cache pool and the control information of the network card module (such as NIC). In the metadata of the shared memory cache pool, the address information drr1 pointing to the old page data is modified to the address information drr2 of the dirty page data just received in the local Doublewrite Buffer, so that the dirty page data that has been written back is used to replace the old page data previously stored in the shared memory cache pool. At the same time, the control information of the network card module (such as NIC) carries the address information drr1 of the old page data stored in the shared memory cache pool, so that the address information drr2 of the dirty page data that has been written back in the local Doublewrite Buffer is modified to the address information drr1 of the old page data previously stored in the shared memory cache pool. These two operations are atomic. Thus, the next time a dirty page is written back, when the compute node writes back to the same location drr2 in the remote memory node's Doublewrite Buffer, what is actually written is the address information drr1 in the shared memory cache pool after the modified mapping. Furthermore, when the compute node reads the same location drr1 in the remote memory node's shared memory cache pool, what is actually read is location drr2 in the remote memory node's Doublewrite Buffer after the modified mapping, ensuring that the latest page data is read. Because the second processing module (such as the DSA) and the second network card module (such as the NIC) are tightly coupled on the second processing unit of the memory node, an additional network data transmission can be replaced by efficient local address modification mapping, which helps improve write-back efficiency.

[0089] In addition to providing the above-mentioned storage and computing separation system, the embodiment of the present application also provides a memory cache pool maintenance method implemented based on the storage and computing separation system. The embodiment of the present application also provides a memory cache pool maintenance method. The method is applied to a computing node, and the computing node includes a first computing unit and a first processing unit. The first processing unit is interconnected with the first computing unit, and is network-interconnected with the second processing unit in at least one memory node. The method may include: the first processing unit cooperates with the second processing unit in at least one memory node to synchronize page data and / or page status between the local memory cache pool provided by the first computing unit for the upper-level application and the shared memory cache pool provided by at least one memory node for the upper-level application to achieve data consistency; wherein, the local memory cache pool can be directly accessed by the first processing unit.

[0090] Further optionally, synchronizing page data and / or page status between a local memory cache pool provided by the first computing unit for the upper-layer application and a shared memory cache pool provided by at least one memory node for the upper-layer application includes:

[0091] Reading first page data from the local memory cache pool and sending the first page data to the second processing unit in the first memory node, so that the second processing unit in the first memory node writes the first page data into the shared memory cache pool in the first memory node;

[0092] and / or,

[0093] receiving second page data sent by the second processing unit in the second memory node, and writing the second page data into the local memory cache pool, wherein the second processing unit in the second memory node reads the second page data from the shared memory cache pool of the second memory node and sends the second page data to the first processing unit;

[0094] and / or,

[0095] Before receiving the second page data, sending a request for adding a read lock to the second processing unit in the second memory node, so that the second processing unit in the second memory node adds a read lock to the second page data;

[0096] and / or,

[0097] Before the first computing unit rewrites the third page data in the local memory cache pool, a request for adding a write lock and invalidating the third page data is sent to the second processing unit in the third memory node, so that the second processing unit in the third memory node adds a write lock to the third page data in the shared memory cache pool and notifies other computing nodes in the local memory cache pool that contain the third page data to invalidate the third page data.

[0098] Optionally, the above method further includes:

[0099] In response to the page read instruction sent by the first computing unit, a page read request is sent to the second processing unit in the second memory node, so that the second processing unit in the second memory node reads the second page data from the shared memory cache pool of the second memory node and returns it.

[0100] Further optionally, reading the first page data from the local memory cache pool includes: reading the first page data from the local memory cache pool in response to a dirty page write-back instruction sent by the first computing unit, where the dirty page write-back instruction is sent by the first computing unit when determining, according to a page replacement mechanism, that there is first page data that needs to be eliminated and is in a modified state;

[0101] or,

[0102] According to the page replacement mechanism, it is determined that there is first page data in the local memory cache pool that needs to be eliminated and is in a modified state, and the first page data is read from the local memory cache pool.

[0103] Further optionally, sending the first page data to the second processing unit in the first memory node includes:

[0104] The first page data is written into the local double-write cache area, and the first page data in the local double-write cache area is sent to the second processing unit on the first memory node, so that the second processing unit writes the first page data into the double-write cache area on the first memory node and points the address pointer pointing to the first page data in the shared memory cache pool of the first memory node to the double-write cache area of the first memory node.

[0105] Further optionally, there is at least one upper-layer application, and one upper-layer application corresponds to a local memory cache pool; the method also includes: polling the receiving queue of the first network card module in the first processing unit; when there is data to be processed in the receiving queue, reading the data to be processed from the receiving queue; determining the upper-layer application to which the data to be processed belongs, and writing it into the local memory cache pool corresponding to the upper-layer application to which it belongs, so that the first computing unit can process the data to be processed, and the data to be processed includes page data or notification messages.

[0106] An embodiment of the present application also provides a flowchart of a memory cache pool maintenance method, which is applied to a memory node. The memory node includes a second computing unit and a second processing unit. The second processing unit is interconnected with the second computing unit, and is also network-interconnected with the first processing unit in at least one computing node. The method includes: the second processing unit cooperates with the first processing unit in at least one computing node to synchronize page data and / or page status between a shared memory cache pool provided by the memory node for an upper-level application and a local memory cache pool provided by at least one computing node for an upper-level application to achieve data consistency; wherein, the shared memory cache pool can be directly accessed by the second processing unit.

[0107] Further optionally, synchronizing page data and / or page status between a shared memory cache pool provided by a memory node for an upper-layer application and a local memory cache pool provided by at least one computing node for the upper-layer application includes: receiving first page data sent by a first processing unit in a first computing node, and writing the first page data into the shared memory cache pool;

[0108] and / or,

[0109] Reading the second page data from the shared memory cache pool and sending the second page data to the first processing unit in the second computing node, so that the first processing unit in the second computing node writes the second page data into the local memory cache pool of the second computing node;

[0110] and / or,

[0111] Before reading the second page data, receiving a request for adding a read lock sent by the first processing unit in the second computing node, and adding a read lock for the second page data;

[0112] and / or,

[0113] Receive a request from the first processing unit in the third computing node to add a write lock and invalidate the third page data in the shared memory cache pool, add a write lock to the third page data and notify other computing nodes in the local memory cache pool that contain the third page data to invalidate the third page data.

[0114] Further optionally, the above method also includes: receiving a page read request sent by the first processing unit in the second computing node, and based on the page read request, querying whether there is readable second page data in the shared memory cache pool; if not, controlling other computing nodes with readable second page data to write the second page data back to the shared memory cache pool.

[0115] Further optionally, the above method also includes: determining whether a write lock is added to the second page data; if a write lock is added, sending an unlock request to the computing node that adds the write lock to the second page data; after the computing node that adds the write lock to the second page data returns the unlock confirmation information, deleting the write lock of the second page data and adding a read lock to the second page data.

[0116] Further optionally, the above method also includes: in the case of writing back the first page data, writing the first page data into the local double-write cache area; pointing the address pointer pointing to the first page data in the shared memory cache pool to the local double-write cache area to read the written-back first page data from the local double-write cache area.

[0117] For a better understanding, the following describes the signaling interaction process between computing nodes and memory nodes.

[0118] Figure 7 This is a signaling interaction diagram of an exemplary memory cache pool maintenance method provided in an embodiment of the present application. Figure 7 , the method may include:

[0119] S71. A first processing unit in a first computing node reads first page data from a local memory cache pool.

[0120] The local memory cache pool is located in the first computing unit of the first computing node.

[0121] S72. The first processing unit in the first computing node sends the first page data to the second processing unit in the first memory node.

[0122] S73. The second processing unit in the first memory node writes the first page data into the shared memory cache pool.

[0123] The shared memory cache pool is located in the second computing unit of the first memory node.

[0124] Figure 8 This is a signaling interaction diagram of another memory cache pool maintenance method exemplified in this application. Figure 8 , the method may include:

[0125] S81. The second processing unit in the second memory node reads second page data from the shared memory cache pool.

[0126] S82. The second computing node sends a request for adding a read lock to the second processing unit in the second memory node.

[0127] S83. The second processing unit in the second memory node adds a read lock for the second page data.

[0128] S84. The second processing unit in the second memory node sends the second page data to the first processing unit in the second computing node.

[0129] S85. The first processing unit in the second computing node writes the second page data into the local memory cache pool.

[0130] The local memory cache pool is located in the first computing unit of the second computing node.

[0131] Figure 9 This is a signaling interaction diagram of another memory cache pool maintenance method exemplified in this application. Figure 9 , the method may include:

[0132] S91. Before the first computing unit rewrites the third page data in the local memory cache pool, the first processing unit in the third computing node sends a request to the second processing unit in the third memory node to add a write lock and invalidate the third page data.

[0133] S92: The second processing unit in the third memory node adds a write lock to the third page data in the shared memory cache pool.

[0134] S93: The second processing unit in the third memory node notifies other third computing nodes in the local memory cache pool that contain the third page data to invalidate the third page data.

[0135] The detailed implementation and beneficial effects of each step in the above embodiment method have been described in detail in the above embodiments and will not be elaborated here.

[0136] Figure 10 This is a schematic diagram of the structure of a processing unit provided in an embodiment of the present application. The processing unit can be implemented as the first processing unit in the computing node in the aforementioned embodiment, or as the second processing unit in the memory node in the aforementioned embodiment. Figure 10 As shown, the processing unit includes: a processing module 100 , a network card module 110 and a storage module 120 .

[0137] The storage module 120 is used to store computer programs and can be configured to store various other data to support operations on the processing unit. Examples of such data include instructions for any application or method operating on the processing unit, messages, pictures, videos, etc.

[0138] The processing module 100 can be implemented by any type of volatile or non-volatile memory device or a combination thereof, such as static random-access memory (SRAM), electrically erasable programmable read only memory (EEPROM), erasable programmable read only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.

[0139] The processing module 100 is coupled to the storage module 120 and is configured to execute the computer program in the storage module 120 to execute the steps of the memory cache pool maintenance method in the above embodiment that can be executed by the first processing unit or the second processing unit.

[0140] Further, if Figure 10 As shown, the processing unit also includes: a communication component 130, a display 140, a power component 150, an audio component 160 and other components. Figure 10 Only some components are shown schematically, which does not mean that the processing unit only includes Figure 10 In addition, Figure 10 The components in the dotted box are optional components, not mandatory components, and the specific components depend on the product form of the processing unit.

[0141] The detailed implementation process of the processing module performing each action can be found in the relevant description in the aforementioned method embodiment or device embodiment, and will not be repeated here.

[0142] Accordingly, an embodiment of the present application further provides a computer-readable storage medium storing a computer program, which, when executed, can implement the steps that can be performed by the first processing unit or the second processing unit in the above method embodiment.

[0143] Accordingly, an embodiment of the present application also provides a computer program product, including a computer program / instruction. When the computer program / instruction is executed by a processor, the processor is enabled to implement the steps in the above method embodiment that can be performed by the first processing unit or the second processing unit.

[0144] The above-mentioned communication component is configured to facilitate wired or wireless communication between the device where the communication component is located and other devices. The device where the communication component is located can access a wireless network based on a communication standard, such as WiFi (Wireless Fidelity), 2G (2 Generation, 2 Generation), 3G (3 Generation, 3 Generation), 4G (4 Generation, 4 Generation) / LTE (Long Term Evolution), 5G (5 Generation, 5 Generation) and other mobile communication networks, or a combination thereof. In an exemplary embodiment, the communication component receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component also includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wide band (UWB) technology, Bluetooth (BT) technology and other technologies.

[0145] The display includes a screen, which may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from a user. The touch panel includes one or more touch sensors to sense touches, slides, and gestures on the touch panel. The touch sensor may not only sense the boundaries of a touch or slide action, but also detect the duration and pressure associated with the touch or slide operation.

[0146] The power supply assembly provides power to various components of the device in which the power supply assembly is located. The power supply assembly may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the device in which the power supply assembly is located.

[0147] The above-mentioned audio component can be configured to output and / or input audio signals. For example, the audio component includes a microphone (MIC), and when the device where the audio component is located is in an operating mode, such as call mode, recording mode, and voice recognition mode, the microphone is configured to receive external audio signals. The received audio signal can be further stored in a memory or sent via a communication component. In some embodiments, the audio component also includes a speaker for outputting audio signals.

[0148] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-readable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0149] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the steps in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0150] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0151] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 The steps for the function specified in one or more boxes.

[0152] In a typical configuration, a computing device includes one or more processors (central processing units, CPUs), input / output interfaces, network interfaces, and memory.

[0153] Memory may include non-permanent storage in a computer-readable medium, random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of a computer-readable medium.

[0154] Computer-readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. The information can be computer-readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, Phase Change RAM (PRAM), Static Random-Access Memory (SRAM), Dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), Read Only Memory (ROM), Electrically-Erasable Programmable Read-Only Memory (EEPROM), flash memory or other memory technology, CD-ROM, Digital Versatile Disc (DVD) or other optical storage, magnetic cassettes, magnetic tape disk storage or other magnetic storage devices or any other non-transmission medium that can be used to store information that can be accessed by a computing device. According to the definition in this article, computer-readable media does not include transitory media such as modulated data signals and carrier waves.

[0155] It should also be noted that the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a series of elements includes not only those elements but also other elements not explicitly listed, or includes elements inherent to such process, method, commodity, or apparatus. In the absence of further limitations, an element defined by the phrase "comprises a ..." does not exclude the presence of other identical elements in the process, method, commodity, or apparatus that includes the element.

[0156] The foregoing is merely an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should all be included within the scope of the claims of the present application.

Claims

1. A computing node, characterized in that: include: a first computing unit and a first processing unit, wherein the first computing unit and the first processing unit are interconnected; The first computing unit is configured to run an upper-layer application and provide a local memory cache pool for caching page data for the upper-layer application, wherein the local memory cache pool can be directly accessed by the first processing unit; The first processing unit is further network-interconnected with a second processing unit in at least one memory node, and is configured to interact with the second processing unit to synchronize page data and / or page status between a local memory cache pool and a shared memory cache pool provided by the at least one memory node for the upper-layer application; There is at least one upper-layer application, and one upper-layer application corresponds to one local memory cache pool; The computing node further polls the receiving queue of the first network card module in the first processing unit; and if there is data to be processed in the receiving queue, reads the data to be processed from the receiving queue; Determine the upper layer application to which the data to be processed belongs, and write the data to be processed into a local memory cache pool corresponding to the upper layer application to which it belongs, so that the first computing unit can process the data to be processed, wherein the data to be processed includes page data or notification messages.

2. The computing node according to claim 1, wherein: The first processing unit includes: a first processing module and a first network card module. The first processing module is interconnected with the first computing unit through an interconnection channel, and the first network card module is interconnected with the second processing unit through a network.

3. The computing node according to claim 2, characterized in that The first processing module is configured to: Reading first page data from the local memory cache pool and sending the data to the second processing unit in the first memory node through the first network card module, so that the second processing unit in the first memory node writes the first page data into the shared memory cache pool in the first memory node; and / or, receiving, through the first network card module, second page data sent by the second processing unit in the second memory node, and writing the second page data into a local memory cache pool, wherein the second processing unit in the second memory node reads the second page data from the shared memory cache pool of the second memory node and sends the data to the first network card module; and / or, Before receiving the second page data, sending a request for adding a read lock to the second processing unit in the second memory node, so that the second processing unit in the second memory node adds a read lock to the second page data; and / or, Before the first computing unit rewrites the third page data in the local memory cache pool, a request for adding a write lock and invalidating the third page data is sent to the second processing unit in the third memory node through the first network card module, so that the second processing unit in the third memory node adds a write lock to the third page data in the shared memory cache pool and notifies other computing nodes in the local memory cache pool that contain the third page data to invalidate the third page data.

4. A memory node, characterized in that: include: a second computing unit and a second processing unit, wherein the second computing unit and the second processing unit are interconnected; The second computing unit is configured to provide a shared memory cache pool for upper-layer applications running on at least one computing node, wherein the shared memory cache pool can be directly accessed by the second processing unit; The second processing unit is further interconnected with the first processing unit in the at least one computing node, and is configured to interact with the first processing unit to synchronize page data and / or page status between a shared memory cache pool and a local memory cache pool provided by the at least one computing node for the upper-layer application; There is at least one upper-layer application, and one upper-layer application corresponds to one local memory cache pool; The computing node further polls the receiving queue of the first network card module in the first processing unit; and if there is data to be processed in the receiving queue, reads the data to be processed from the receiving queue; Determine the upper layer application to which the data to be processed belongs, and write the data to be processed into a local memory cache pool corresponding to the upper layer application to which it belongs, so that the first computing unit processes the data to be processed, wherein the data to be processed includes page data or notification messages.

5. A memory cache pool maintenance method, characterized in that: Applied to a computing node, the computing node includes a first computing unit and a first processing unit, the first processing unit is interconnected with the first computing unit, and is network-interconnected with a second processing unit in at least one memory node, the method comprising: The first processing unit interacts with the second processing unit in the at least one memory node to synchronize page data and / or page status between a local memory cache pool provided by the first computing unit for an upper-layer application and a shared memory cache pool provided by the at least one memory node for the upper-layer application; wherein the local memory cache pool can be directly accessed by the first processing unit; There is at least one upper-layer application, and each upper-layer application corresponds to one local memory cache pool; the method further includes: Polling a receiving queue of the first network card module in the first processing unit; if there is data to be processed in the receiving queue, reading the data to be processed from the receiving queue; Determine the upper layer application to which the data to be processed belongs, and write the data to be processed into a local memory cache pool corresponding to the upper layer application to which it belongs, so that the first computing unit can process the data to be processed, wherein the data to be processed includes page data or notification messages.

6. The method according to claim 5, characterized in that The first processing unit interacts with the second processing unit in the at least one memory node to synchronize page data and / or page status between a local memory cache pool provided by the first computing unit for an upper-layer application and a shared memory cache pool provided by the at least one memory node for the upper-layer application, including: Reading first page data from the local memory cache pool, and sending the first page data to the second processing unit in the first memory node, so that the second processing unit in the first memory node writes the first page data into the shared memory cache pool in the first memory node; and / or, receiving second page data sent by a second processing unit in a second memory node, and writing the second page data into a local memory cache pool, wherein the second processing unit in the second memory node reads the second page data from a shared memory cache pool of the second memory node and sends the second page data to the first processing unit; and / or, Before receiving the second page data, sending a request for adding a read lock to the second processing unit in the second memory node, so that the second processing unit in the second memory node adds a read lock to the second page data; and / or, Before the first computing unit rewrites the third page data in the local memory cache pool, a request for adding a write lock and invalidating the third page data is sent to the second processing unit in the third memory node, so that the second processing unit in the third memory node adds a write lock to the third page data in the shared memory cache pool and notifies other computing nodes in the local memory cache pool that contain the third page data to invalidate the third page data.

7. The method according to claim 6, characterized in that Read the first page of data from the local memory cache pool, including: In response to a dirty page write-back instruction sent by the first computing unit, read the first page data from the local memory cache pool, wherein the dirty page write-back instruction is sent by the first computing unit when the first computing unit determines, according to a page replacement mechanism, that there is first page data that needs to be eliminated and is in a modified state; or, According to the page replacement mechanism, it is determined that page data in the local memory cache pool that needs to be eliminated and is in a modified state is the first page data, and the first page data is read from the local memory cache pool.

8. The method according to claim 6, characterized in that Sending the first page data to the second processing unit in the first memory node includes: The first page data is written into a local double-write buffer area, and the first page data in the local double-write buffer area is sent to a second processing unit on the first memory node, so that the second processing unit writes the first page data into the double-write buffer area on the first memory node, and points the address pointer pointing to the first page data in the shared memory buffer pool of the first memory node to the double-write buffer area.

9. A memory cache pool maintenance method, characterized in that: Applied to a memory node, the memory node includes a second computing unit and a second processing unit, the second processing unit is interconnected with the second computing unit, and is network-interconnected with a first processing unit in at least one computing node, the method comprising: The second processing unit interacts with the first processing unit in the at least one computing node to synchronize page data and / or page status between a shared memory cache pool provided by the memory node for the upper-layer application and a local memory cache pool provided by the at least one computing node for the upper-layer application; wherein the shared memory buffer pool can be directly accessed by the second processing unit; There is at least one upper-layer application, and each upper-layer application corresponds to a local memory cache pool; the computing node also polls the receiving queue of the first network card module in the first processing unit; if there is data to be processed in the receiving queue, the data to be processed is read from the receiving queue; the upper-layer application to which the data to be processed belongs is determined, and the data to be processed is written into the local memory cache pool corresponding to the upper-layer application to which it belongs, so that the first computing unit can process the data to be processed, and the data to be processed includes page data or notification messages.

10. The method according to claim 9, characterized in that The second processing unit interacts with the first processing unit in the at least one computing node to synchronize page data and / or page status between a shared memory cache pool provided by the memory node for the upper-layer application and a local memory cache pool provided by the at least one computing node for the upper-layer application, including: receiving first page data sent by a first processing unit in a first computing node, and writing the first page data into the shared memory cache pool; and / or, Reading second page data from the shared memory cache pool, and sending the second page data to the first processing unit in the second computing node, so that the first processing unit in the second computing node writes the second page data into the local memory cache pool of the second computing node; and / or, Before reading the second page data, receiving a request for adding a read lock sent by the first processing unit in the second computing node, and adding a read lock to the second page data; and / or, Receive a request from the first processing unit in the third computing node to add a write lock and invalidate the third page data in the shared memory cache pool, add a write lock to the third page data and notify other computing nodes in the local memory cache pool that contain the third page data to invalidate the third page data.

11. The method according to claim 10, characterized in that Also includes: In the case of writing back the first page data, writing the first page data into a local double-write buffer area; The address pointer pointing to the first page data in the shared memory buffer pool is pointed to the local double-write buffer area, so as to read the first page data to be written back from the local double-write buffer area.

12. A storage and computing separation system, characterized in that: include: A plurality of computing nodes according to any one of claims 1 to 3, at least one memory node according to claim 4, and at least one storage node; The at least one storage node is used to persistently store page data in the shared memory cache pool and / or the local memory cache pool.

13. A processing unit, characterized in that: The processing unit includes: a processing module, a network card module and a storage module, wherein the storage module stores a computer program, and the processing module executes the computer program stored in the storage module to implement the steps in the method described in any one of claims 5-8 and claims 9-11.

14. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the processor is enabled to implement the steps of the method according to any one of claims 5 to 8 and claims 9 to 11.

Images